1 /* 2 * Configuation settings for the Freescale MCF5208EVBe. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _M5208EVBE_H 11 #define _M5208EVBE_H 12 13 /* 14 * High Level Configuration Options 15 * (easy to change) 16 */ 17 #define CONFIG_MCFUART 18 #define CONFIG_SYS_UART_PORT (0) 19 #define CONFIG_BAUDRATE 115200 20 21 #undef CONFIG_WATCHDOG 22 #define CONFIG_WATCHDOG_TIMEOUT 5000 23 24 /* Command line configuration */ 25 #define CONFIG_CMD_CACHE 26 #define CONFIG_CMD_ELF 27 #undef CONFIG_CMD_I2C 28 #define CONFIG_CMD_MII 29 #define CONFIG_CMD_PING 30 #define CONFIG_CMD_REGINFO 31 32 #define CONFIG_MCFFEC 33 #ifdef CONFIG_MCFFEC 34 # define CONFIG_MII 1 35 # define CONFIG_MII_INIT 1 36 # define CONFIG_SYS_DISCOVER_PHY 37 # define CONFIG_SYS_RX_ETH_BUFFER 8 38 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 39 # define CONFIG_HAS_ETH1 40 41 # define CONFIG_SYS_FEC0_PINMUX 0 42 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 43 # define MCFFEC_TOUT_LOOP 50000 44 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 45 # ifndef CONFIG_SYS_DISCOVER_PHY 46 # define FECDUPLEX FULL 47 # define FECSPEED _100BASET 48 # else 49 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 50 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 51 # endif 52 # endif /* CONFIG_SYS_DISCOVER_PHY */ 53 #endif 54 55 /* Timer */ 56 #define CONFIG_MCFTMR 57 #undef CONFIG_MCFPIT 58 59 /* I2C */ 60 #define CONFIG_SYS_I2C 61 #define CONFIG_SYS_I2C_FSL 62 #define CONFIG_SYS_FSL_I2C_SPEED 80000 63 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 64 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 65 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 66 67 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 68 #define CONFIG_UDP_CHECKSUM 69 70 #ifdef CONFIG_MCFFEC 71 # define CONFIG_IPADDR 192.162.1.2 72 # define CONFIG_NETMASK 255.255.255.0 73 # define CONFIG_SERVERIP 192.162.1.1 74 # define CONFIG_GATEWAYIP 192.162.1.1 75 #endif /* CONFIG_MCFFEC */ 76 77 #define CONFIG_HOSTNAME M5208EVBe 78 #define CONFIG_EXTRA_ENV_SETTINGS \ 79 "netdev=eth0\0" \ 80 "loadaddr=40010000\0" \ 81 "u-boot=u-boot.bin\0" \ 82 "load=tftp ${loadaddr) ${u-boot}\0" \ 83 "upd=run load; run prog\0" \ 84 "prog=prot off 0 3ffff;" \ 85 "era 0 3ffff;" \ 86 "cp.b ${loadaddr} 0 ${filesize};" \ 87 "save\0" \ 88 "" 89 90 #define CONFIG_PRAM 512 /* 512 KB */ 91 #define CONFIG_SYS_PROMPT "-> " 92 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 93 94 #ifdef CONFIG_CMD_KGDB 95 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 96 #else 97 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 98 #endif 99 100 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 101 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 102 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ 103 #define CONFIG_SYS_LOAD_ADDR 0x40010000 104 105 #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ 106 #define CONFIG_SYS_PLL_ODR 0x36 107 #define CONFIG_SYS_PLL_FDR 0x7D 108 109 #define CONFIG_SYS_MBAR 0xFC000000 110 111 /* 112 * Low Level Configuration Settings 113 * (address mappings, register initial values, etc.) 114 * You should know what you are doing if you make changes here. 115 */ 116 /* Definitions for initial stack pointer and data area (in DPRAM) */ 117 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 118 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ 119 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 120 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 121 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 122 123 /* 124 * Start addresses for the final memory configuration 125 * (Set up by the startup code) 126 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 127 */ 128 #define CONFIG_SYS_SDRAM_BASE 0x40000000 129 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 130 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 131 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 132 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000 133 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 134 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 135 136 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 137 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 138 139 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 140 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 141 142 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 143 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 144 145 /* 146 * For booting Linux, the board info and command line data 147 * have to be in the first 8 MB of memory, since this is 148 * the maximum mapped by the Linux kernel during initialization ?? 149 */ 150 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 151 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 152 153 /* FLASH organization */ 154 #define CONFIG_SYS_FLASH_CFI 155 #ifdef CONFIG_SYS_FLASH_CFI 156 # define CONFIG_FLASH_CFI_DRIVER 1 157 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 158 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 159 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 160 # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ 161 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 162 #endif 163 164 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 165 166 /* 167 * Configuration for environment 168 * Environment is embedded in u-boot in the second sector of the flash 169 */ 170 #define CONFIG_ENV_OFFSET 0x2000 171 #define CONFIG_ENV_SIZE 0x1000 172 #define CONFIG_ENV_SECT_SIZE 0x2000 173 #define CONFIG_ENV_IS_IN_FLASH 1 174 175 #define LDS_BOARD_TEXT \ 176 . = DEFINED(env_offset) ? env_offset : .; \ 177 common/env_embedded.o (.text*); 178 179 /* Cache Configuration */ 180 #define CONFIG_SYS_CACHELINE_SIZE 16 181 182 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 183 CONFIG_SYS_INIT_RAM_SIZE - 8) 184 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 185 CONFIG_SYS_INIT_RAM_SIZE - 4) 186 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 187 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 188 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 189 CF_ACR_EN | CF_ACR_SM_ALL) 190 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 191 CF_CACR_DISD | CF_CACR_INVI | \ 192 CF_CACR_CEIB | CF_CACR_DCM | \ 193 CF_CACR_EUSP) 194 195 /* Chipselect bank definitions */ 196 /* 197 * CS0 - NOR Flash 198 * CS1 - Available 199 * CS2 - Available 200 * CS3 - Available 201 * CS4 - Available 202 * CS5 - Available 203 */ 204 #define CONFIG_SYS_CS0_BASE 0 205 #define CONFIG_SYS_CS0_MASK 0x007F0001 206 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 207 208 #endif /* _M5208EVBE_H */ 209