1 /* 2 * Configuation settings for the Freescale MCF5208EVBe. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _M5208EVBE_H 11 #define _M5208EVBE_H 12 13 /* 14 * High Level Configuration Options 15 * (easy to change) 16 */ 17 #define CONFIG_MCFUART 18 #define CONFIG_SYS_UART_PORT (0) 19 20 #undef CONFIG_WATCHDOG 21 #define CONFIG_WATCHDOG_TIMEOUT 5000 22 23 /* Command line configuration */ 24 #define CONFIG_CMD_REGINFO 25 26 #define CONFIG_MCFFEC 27 #ifdef CONFIG_MCFFEC 28 # define CONFIG_MII 1 29 # define CONFIG_MII_INIT 1 30 # define CONFIG_SYS_DISCOVER_PHY 31 # define CONFIG_SYS_RX_ETH_BUFFER 8 32 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 33 # define CONFIG_HAS_ETH1 34 35 # define CONFIG_SYS_FEC0_PINMUX 0 36 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 37 # define MCFFEC_TOUT_LOOP 50000 38 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 39 # ifndef CONFIG_SYS_DISCOVER_PHY 40 # define FECDUPLEX FULL 41 # define FECSPEED _100BASET 42 # else 43 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 44 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 45 # endif 46 # endif /* CONFIG_SYS_DISCOVER_PHY */ 47 #endif 48 49 /* Timer */ 50 #define CONFIG_MCFTMR 51 #undef CONFIG_MCFPIT 52 53 /* I2C */ 54 #define CONFIG_SYS_I2C 55 #define CONFIG_SYS_I2C_FSL 56 #define CONFIG_SYS_FSL_I2C_SPEED 80000 57 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 58 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 59 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 60 61 #define CONFIG_UDP_CHECKSUM 62 63 #ifdef CONFIG_MCFFEC 64 # define CONFIG_IPADDR 192.162.1.2 65 # define CONFIG_NETMASK 255.255.255.0 66 # define CONFIG_SERVERIP 192.162.1.1 67 # define CONFIG_GATEWAYIP 192.162.1.1 68 #endif /* CONFIG_MCFFEC */ 69 70 #define CONFIG_HOSTNAME M5208EVBe 71 #define CONFIG_EXTRA_ENV_SETTINGS \ 72 "netdev=eth0\0" \ 73 "loadaddr=40010000\0" \ 74 "u-boot=u-boot.bin\0" \ 75 "load=tftp ${loadaddr) ${u-boot}\0" \ 76 "upd=run load; run prog\0" \ 77 "prog=prot off 0 3ffff;" \ 78 "era 0 3ffff;" \ 79 "cp.b ${loadaddr} 0 ${filesize};" \ 80 "save\0" \ 81 "" 82 83 #define CONFIG_PRAM 512 /* 512 KB */ 84 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 85 86 #ifdef CONFIG_CMD_KGDB 87 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 88 #else 89 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 90 #endif 91 92 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 93 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 94 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ 95 #define CONFIG_SYS_LOAD_ADDR 0x40010000 96 97 #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ 98 #define CONFIG_SYS_PLL_ODR 0x36 99 #define CONFIG_SYS_PLL_FDR 0x7D 100 101 #define CONFIG_SYS_MBAR 0xFC000000 102 103 /* 104 * Low Level Configuration Settings 105 * (address mappings, register initial values, etc.) 106 * You should know what you are doing if you make changes here. 107 */ 108 /* Definitions for initial stack pointer and data area (in DPRAM) */ 109 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 110 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ 111 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 112 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 113 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 114 115 /* 116 * Start addresses for the final memory configuration 117 * (Set up by the startup code) 118 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 119 */ 120 #define CONFIG_SYS_SDRAM_BASE 0x40000000 121 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 122 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 123 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 124 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000 125 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 126 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 127 128 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 129 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 130 131 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 132 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 133 134 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 135 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 136 137 /* 138 * For booting Linux, the board info and command line data 139 * have to be in the first 8 MB of memory, since this is 140 * the maximum mapped by the Linux kernel during initialization ?? 141 */ 142 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 143 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 144 145 /* FLASH organization */ 146 #define CONFIG_SYS_FLASH_CFI 147 #ifdef CONFIG_SYS_FLASH_CFI 148 # define CONFIG_FLASH_CFI_DRIVER 1 149 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 150 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 151 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 152 # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ 153 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 154 #endif 155 156 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 157 158 /* 159 * Configuration for environment 160 * Environment is embedded in u-boot in the second sector of the flash 161 */ 162 #define CONFIG_ENV_OFFSET 0x2000 163 #define CONFIG_ENV_SIZE 0x1000 164 #define CONFIG_ENV_SECT_SIZE 0x2000 165 #define CONFIG_ENV_IS_IN_FLASH 1 166 167 #define LDS_BOARD_TEXT \ 168 . = DEFINED(env_offset) ? env_offset : .; \ 169 common/env_embedded.o (.text*); 170 171 /* Cache Configuration */ 172 #define CONFIG_SYS_CACHELINE_SIZE 16 173 174 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 175 CONFIG_SYS_INIT_RAM_SIZE - 8) 176 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 177 CONFIG_SYS_INIT_RAM_SIZE - 4) 178 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 179 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 180 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 181 CF_ACR_EN | CF_ACR_SM_ALL) 182 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 183 CF_CACR_DISD | CF_CACR_INVI | \ 184 CF_CACR_CEIB | CF_CACR_DCM | \ 185 CF_CACR_EUSP) 186 187 /* Chipselect bank definitions */ 188 /* 189 * CS0 - NOR Flash 190 * CS1 - Available 191 * CS2 - Available 192 * CS3 - Available 193 * CS4 - Available 194 * CS5 - Available 195 */ 196 #define CONFIG_SYS_CS0_BASE 0 197 #define CONFIG_SYS_CS0_MASK 0x007F0001 198 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 199 200 #endif /* _M5208EVBE_H */ 201