1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_SPIFLASH 15 #define CONFIG_RAMBOOT_SPIFLASH 16 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 17 #endif 18 19 #ifdef CONFIG_NAND 20 #ifdef CONFIG_TPL_BUILD 21 #define CONFIG_SPL_NAND_BOOT 22 #define CONFIG_SPL_FLUSH_IMAGE 23 #define CONFIG_SPL_NAND_INIT 24 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT 25 #define CONFIG_SPL_COMMON_INIT_DDR 26 #define CONFIG_SPL_MAX_SIZE (128 << 10) 27 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 28 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 29 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 30 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 31 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 32 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 33 #elif defined(CONFIG_SPL_BUILD) 34 #define CONFIG_SPL_INIT_MINIMAL 35 #define CONFIG_SPL_NAND_MINIMAL 36 #define CONFIG_SPL_FLUSH_IMAGE 37 #define CONFIG_SPL_TEXT_BASE 0xff800000 38 #define CONFIG_SPL_MAX_SIZE 8192 39 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 40 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 41 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 42 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 43 #endif 44 #define CONFIG_SPL_PAD_TO 0x20000 45 #define CONFIG_TPL_PAD_TO 0x20000 46 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 47 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 48 #endif 49 50 #ifndef CONFIG_RESET_VECTOR_ADDRESS 51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 52 #endif 53 54 #ifdef CONFIG_SPL_BUILD 55 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 56 #else 57 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 58 #endif 59 60 #ifdef CONFIG_SPL_BUILD 61 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 62 #endif 63 64 /* High Level Configuration Options */ 65 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 66 67 #ifdef CONFIG_PCI 68 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 69 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 70 #define CONFIG_PCI_INDIRECT_BRIDGE 71 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 72 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 73 74 /* 75 * PCI Windows 76 * Memory space is mapped 1-1, but I/O space must start from 0. 77 */ 78 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 79 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 80 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 81 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 82 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 83 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 84 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 85 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 86 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 87 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 88 89 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 90 #endif 91 92 #define CONFIG_ENV_OVERWRITE 93 94 #define CONFIG_DDR_CLK_FREQ 100000000 95 #define CONFIG_SYS_CLK_FREQ 66666666 96 97 #define CONFIG_HWCONFIG 98 99 /* 100 * These can be toggled for performance analysis, otherwise use default. 101 */ 102 #define CONFIG_L2_CACHE /* toggle L2 cache */ 103 #define CONFIG_BTB /* toggle branch predition */ 104 105 106 #define CONFIG_ENABLE_36BIT_PHYS 107 108 #define CONFIG_ADDR_MAP 1 109 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 110 111 #define CONFIG_SYS_MEMTEST_START 0x00200000 112 #define CONFIG_SYS_MEMTEST_END 0x00400000 113 114 /* DDR Setup */ 115 #define CONFIG_DDR_SPD 116 #define CONFIG_SYS_SPD_BUS_NUM 0 117 #define SPD_EEPROM_ADDRESS 0x50 118 #define CONFIG_SYS_DDR_RAW_TIMING 119 120 /* DDR ECC Setup*/ 121 #define CONFIG_DDR_ECC 122 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 123 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 124 125 #define CONFIG_SYS_SDRAM_SIZE 512 126 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 127 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 128 129 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 130 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 131 132 #define CONFIG_SYS_CCSRBAR 0xffe00000 133 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 134 135 /* Platform SRAM setting */ 136 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 137 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 138 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 139 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 140 141 /* 142 * IFC Definitions 143 */ 144 /* NOR Flash on IFC */ 145 #define CONFIG_SYS_FLASH_BASE 0xec000000 146 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 147 148 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 149 150 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 151 #define CONFIG_SYS_MAX_FLASH_BANKS 1 152 153 #define CONFIG_SYS_FLASH_QUIET_TEST 154 #define CONFIG_FLASH_SHOW_PROGRESS 45 155 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 156 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 157 158 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 159 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 160 CSPR_PORT_SIZE_16 | \ 161 CSPR_MSEL_NOR | \ 162 CSPR_V) 163 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 164 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 165 166 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 167 FTIM0_NOR_TEADC(0x5) | \ 168 FTIM0_NOR_TEAHC(0x5)) 169 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 170 FTIM1_NOR_TRAD_NOR(0x1A) |\ 171 FTIM1_NOR_TSEQRAD_NOR(0x13)) 172 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 173 FTIM2_NOR_TCH(0x4) | \ 174 FTIM2_NOR_TWPH(0x0E) | \ 175 FTIM2_NOR_TWP(0x1c)) 176 #define CONFIG_SYS_NOR_FTIM3 0x0 177 178 /* CFI for NOR Flash */ 179 #define CONFIG_FLASH_CFI_DRIVER 180 #define CONFIG_SYS_FLASH_CFI 181 #define CONFIG_SYS_FLASH_EMPTY_INFO 182 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 183 184 /* NAND Flash on IFC */ 185 #define CONFIG_NAND_FSL_IFC 186 #define CONFIG_SYS_NAND_BASE 0xff800000 187 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 188 189 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 190 191 #define CONFIG_SYS_MAX_NAND_DEVICE 1 192 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 193 194 /* 8Bit NAND Flash - K9F1G08U0B */ 195 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 196 | CSPR_PORT_SIZE_8 \ 197 | CSPR_MSEL_NAND \ 198 | CSPR_V) 199 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 200 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 201 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 202 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 203 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 204 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 205 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 206 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 207 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 208 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 209 FTIM0_NAND_TWP(0x0c) | \ 210 FTIM0_NAND_TWCHT(0x08) | \ 211 FTIM0_NAND_TWH(0x06)) 212 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 213 FTIM1_NAND_TWBE(0x1d) | \ 214 FTIM1_NAND_TRR(0x08) | \ 215 FTIM1_NAND_TRP(0x0c)) 216 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 217 FTIM2_NAND_TREH(0x0a) | \ 218 FTIM2_NAND_TWHRE(0x18)) 219 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 220 221 #define CONFIG_SYS_NAND_DDR_LAW 11 222 223 /* Set up IFC registers for boot location NOR/NAND */ 224 #ifdef CONFIG_NAND 225 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 226 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 227 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 228 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 229 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 230 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 231 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 232 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 233 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 234 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 235 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 236 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 237 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 238 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 239 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 240 #else 241 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 242 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 243 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 244 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 245 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 246 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 247 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 248 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 249 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 250 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 251 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 252 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 253 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 254 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 255 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 256 #endif 257 258 /* CPLD on IFC, selected by CS2 */ 259 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 260 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 261 | CONFIG_SYS_CPLD_BASE) 262 263 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 264 | CSPR_PORT_SIZE_8 \ 265 | CSPR_MSEL_GPCM \ 266 | CSPR_V) 267 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 268 #define CONFIG_SYS_CSOR2 0x0 269 /* CPLD Timing parameters for IFC CS2 */ 270 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 271 FTIM0_GPCM_TEADC(0x0e) | \ 272 FTIM0_GPCM_TEAHC(0x0e)) 273 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 274 FTIM1_GPCM_TRAD(0x1f)) 275 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 276 FTIM2_GPCM_TCH(0x8) | \ 277 FTIM2_GPCM_TWP(0x1f)) 278 #define CONFIG_SYS_CS2_FTIM3 0x0 279 280 #if defined(CONFIG_RAMBOOT_SPIFLASH) 281 #define CONFIG_SYS_RAMBOOT 282 #define CONFIG_SYS_EXTRA_ENV_RELOC 283 #endif 284 285 #define CONFIG_SYS_INIT_RAM_LOCK 286 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 287 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 288 289 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 290 - GENERATED_GBL_DATA_SIZE) 291 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 292 293 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 294 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 295 296 /* 297 * Config the L2 Cache as L2 SRAM 298 */ 299 #if defined(CONFIG_SPL_BUILD) 300 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 301 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 302 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 303 #define CONFIG_SYS_L2_SIZE (256 << 10) 304 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 305 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 306 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 307 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 308 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 309 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 310 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 311 #elif defined(CONFIG_NAND) 312 #ifdef CONFIG_TPL_BUILD 313 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 314 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 315 #define CONFIG_SYS_L2_SIZE (256 << 10) 316 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 317 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 318 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 319 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 320 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 321 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 322 #else 323 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 324 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 325 #define CONFIG_SYS_L2_SIZE (256 << 10) 326 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 327 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 328 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 329 #endif 330 #endif 331 #endif 332 333 /* Serial Port */ 334 #define CONFIG_SYS_NS16550_SERIAL 335 #define CONFIG_SYS_NS16550_REG_SIZE 1 336 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 337 338 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 339 #define CONFIG_NS16550_MIN_FUNCTIONS 340 #endif 341 342 #define CONFIG_SYS_BAUDRATE_TABLE \ 343 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 344 345 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 346 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 347 348 #define CONFIG_SYS_I2C 349 #define CONFIG_SYS_I2C_FSL 350 #define CONFIG_SYS_FSL_I2C_SPEED 400000 351 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 352 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 353 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 354 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 355 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 356 357 /* I2C EEPROM */ 358 /* enable read and write access to EEPROM */ 359 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 360 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 361 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 362 363 /* eSPI - Enhanced SPI */ 364 #define CONFIG_SF_DEFAULT_SPEED 10000000 365 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 366 367 #ifdef CONFIG_TSEC_ENET 368 #define CONFIG_MII /* MII PHY management */ 369 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 370 #define CONFIG_TSEC1 1 371 #define CONFIG_TSEC1_NAME "eTSEC1" 372 #define CONFIG_TSEC2 1 373 #define CONFIG_TSEC2_NAME "eTSEC2" 374 375 /* Default mode is RGMII mode */ 376 #define TSEC1_PHY_ADDR 0 377 #define TSEC2_PHY_ADDR 2 378 379 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 380 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 381 382 #define CONFIG_ETHPRIME "eTSEC1" 383 #endif /* CONFIG_TSEC_ENET */ 384 385 /* 386 * Environment 387 */ 388 #if defined(CONFIG_SYS_RAMBOOT) 389 #if defined(CONFIG_RAMBOOT_SPIFLASH) 390 #define CONFIG_ENV_SPI_BUS 0 391 #define CONFIG_ENV_SPI_CS 0 392 #define CONFIG_ENV_SPI_MAX_HZ 10000000 393 #define CONFIG_ENV_SPI_MODE 0 394 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 395 #define CONFIG_ENV_SECT_SIZE 0x10000 396 #define CONFIG_ENV_SIZE 0x2000 397 #endif 398 #elif defined(CONFIG_NAND) 399 #ifdef CONFIG_TPL_BUILD 400 #define CONFIG_ENV_SIZE 0x2000 401 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 402 #else 403 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 404 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 405 #endif 406 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE 407 #else 408 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 409 #define CONFIG_ENV_SIZE 0x2000 410 #define CONFIG_ENV_SECT_SIZE 0x20000 411 #endif 412 413 #define CONFIG_LOADS_ECHO 414 #define CONFIG_SYS_LOADS_BAUD_CHANGE 415 416 /* 417 * Miscellaneous configurable options 418 */ 419 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 420 421 /* 422 * For booting Linux, the board info and command line data 423 * have to be in the first 64 MB of memory, since this is 424 * the maximum mapped by the Linux kernel during initialization. 425 */ 426 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 427 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 428 429 /* 430 * Environment Configuration 431 */ 432 433 #ifdef CONFIG_TSEC_ENET 434 #define CONFIG_HAS_ETH0 435 #define CONFIG_HAS_ETH1 436 #endif 437 438 #define CONFIG_ROOTPATH "/opt/nfsroot" 439 #define CONFIG_BOOTFILE "uImage" 440 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 441 442 /* default location for tftp and bootm */ 443 #define CONFIG_LOADADDR 1000000 444 445 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 446 447 #define CONFIG_EXTRA_ENV_SETTINGS \ 448 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 449 "netdev=eth0\0" \ 450 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 451 "loadaddr=1000000\0" \ 452 "consoledev=ttyS0\0" \ 453 "ramdiskaddr=2000000\0" \ 454 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 455 "fdtaddr=1e00000\0" \ 456 "fdtfile=name/of/device-tree.dtb\0" \ 457 "othbootargs=ramdisk_size=600000\0" \ 458 459 #define CONFIG_RAMBOOTCOMMAND \ 460 "setenv bootargs root=/dev/ram rw " \ 461 "console=$consoledev,$baudrate $othbootargs; " \ 462 "tftp $ramdiskaddr $ramdiskfile;" \ 463 "tftp $loadaddr $bootfile;" \ 464 "tftp $fdtaddr $fdtfile;" \ 465 "bootm $loadaddr $ramdiskaddr $fdtaddr" 466 467 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 468 469 #include <asm/fsl_secure_boot.h> 470 471 #endif /* __CONFIG_H */ 472