1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_PHYS_64BIT 15 #define CONFIG_DISPLAY_BOARDINFO 16 17 #ifdef CONFIG_C29XPCIE 18 #define CONFIG_PPC_C29X 19 #endif 20 21 #ifdef CONFIG_SPIFLASH 22 #define CONFIG_RAMBOOT_SPIFLASH 23 #define CONFIG_SYS_TEXT_BASE 0x11000000 24 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 25 #endif 26 27 #ifdef CONFIG_NAND 28 #ifdef CONFIG_TPL_BUILD 29 #define CONFIG_SPL_NAND_BOOT 30 #define CONFIG_SPL_FLUSH_IMAGE 31 #define CONFIG_SPL_ENV_SUPPORT 32 #define CONFIG_SPL_NAND_INIT 33 #define CONFIG_SPL_SERIAL_SUPPORT 34 #define CONFIG_SPL_LIBGENERIC_SUPPORT 35 #define CONFIG_SPL_LIBCOMMON_SUPPORT 36 #define CONFIG_SPL_I2C_SUPPORT 37 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 38 #define CONFIG_SPL_NAND_SUPPORT 39 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 40 #define CONFIG_SPL_COMMON_INIT_DDR 41 #define CONFIG_SPL_MAX_SIZE (128 << 10) 42 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 43 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 44 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 45 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 46 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 47 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 48 #elif defined(CONFIG_SPL_BUILD) 49 #define CONFIG_SPL_INIT_MINIMAL 50 #define CONFIG_SPL_SERIAL_SUPPORT 51 #define CONFIG_SPL_NAND_SUPPORT 52 #define CONFIG_SPL_NAND_MINIMAL 53 #define CONFIG_SPL_FLUSH_IMAGE 54 #define CONFIG_SPL_TEXT_BASE 0xff800000 55 #define CONFIG_SPL_MAX_SIZE 8192 56 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 57 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 58 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 59 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 60 #endif 61 #define CONFIG_SPL_PAD_TO 0x20000 62 #define CONFIG_TPL_PAD_TO 0x20000 63 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 64 #define CONFIG_SYS_TEXT_BASE 0x11001000 65 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 66 #endif 67 68 #ifndef CONFIG_SYS_TEXT_BASE 69 #define CONFIG_SYS_TEXT_BASE 0xeff40000 70 #endif 71 72 #ifndef CONFIG_RESET_VECTOR_ADDRESS 73 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 74 #endif 75 76 #ifdef CONFIG_SPL_BUILD 77 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 78 #else 79 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 80 #endif 81 82 #ifdef CONFIG_SPL_BUILD 83 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 84 #endif 85 86 /* High Level Configuration Options */ 87 #define CONFIG_BOOKE /* BOOKE */ 88 #define CONFIG_E500 /* BOOKE e500 family */ 89 #define CONFIG_FSL_IFC /* Enable IFC Support */ 90 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 91 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 92 93 #define CONFIG_PCI /* Enable PCI/PCIE */ 94 #ifdef CONFIG_PCI 95 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 96 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 97 #define CONFIG_PCI_INDIRECT_BRIDGE 98 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 99 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 100 101 #define CONFIG_CMD_PCI 102 103 104 /* 105 * PCI Windows 106 * Memory space is mapped 1-1, but I/O space must start from 0. 107 */ 108 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 109 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 110 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 111 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 112 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 113 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 114 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 115 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 116 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 117 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 118 119 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 120 121 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 122 #define CONFIG_DOS_PARTITION 123 #endif 124 125 #define CONFIG_FSL_LAW /* Use common FSL init code */ 126 #define CONFIG_TSEC_ENET 127 #define CONFIG_ENV_OVERWRITE 128 129 #define CONFIG_DDR_CLK_FREQ 100000000 130 #define CONFIG_SYS_CLK_FREQ 66666666 131 132 #define CONFIG_HWCONFIG 133 134 /* 135 * These can be toggled for performance analysis, otherwise use default. 136 */ 137 #define CONFIG_L2_CACHE /* toggle L2 cache */ 138 #define CONFIG_BTB /* toggle branch predition */ 139 140 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 141 142 #define CONFIG_ENABLE_36BIT_PHYS 143 144 #define CONFIG_ADDR_MAP 1 145 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 146 147 #define CONFIG_SYS_MEMTEST_START 0x00200000 148 #define CONFIG_SYS_MEMTEST_END 0x00400000 149 #define CONFIG_PANIC_HANG 150 151 /* DDR Setup */ 152 #define CONFIG_SYS_FSL_DDR3 153 #define CONFIG_DDR_SPD 154 #define CONFIG_SYS_SPD_BUS_NUM 0 155 #define SPD_EEPROM_ADDRESS 0x50 156 #define CONFIG_SYS_DDR_RAW_TIMING 157 158 /* DDR ECC Setup*/ 159 #define CONFIG_DDR_ECC 160 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 161 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 162 163 #define CONFIG_SYS_SDRAM_SIZE 512 164 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 165 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 166 167 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 168 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 169 170 #define CONFIG_SYS_CCSRBAR 0xffe00000 171 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 172 173 /* Platform SRAM setting */ 174 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 175 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 176 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 177 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 178 179 #ifdef CONFIG_SPL_BUILD 180 #define CONFIG_SYS_NO_FLASH 181 #endif 182 183 /* 184 * IFC Definitions 185 */ 186 /* NOR Flash on IFC */ 187 #define CONFIG_SYS_FLASH_BASE 0xec000000 188 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 189 190 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 191 192 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 193 #define CONFIG_SYS_MAX_FLASH_BANKS 1 194 195 #define CONFIG_SYS_FLASH_QUIET_TEST 196 #define CONFIG_FLASH_SHOW_PROGRESS 45 197 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 198 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 199 200 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 201 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 202 CSPR_PORT_SIZE_16 | \ 203 CSPR_MSEL_NOR | \ 204 CSPR_V) 205 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 206 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 207 208 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 209 FTIM0_NOR_TEADC(0x5) | \ 210 FTIM0_NOR_TEAHC(0x5)) 211 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 212 FTIM1_NOR_TRAD_NOR(0x1A) |\ 213 FTIM1_NOR_TSEQRAD_NOR(0x13)) 214 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 215 FTIM2_NOR_TCH(0x4) | \ 216 FTIM2_NOR_TWPH(0x0E) | \ 217 FTIM2_NOR_TWP(0x1c)) 218 #define CONFIG_SYS_NOR_FTIM3 0x0 219 220 /* CFI for NOR Flash */ 221 #define CONFIG_FLASH_CFI_DRIVER 222 #define CONFIG_SYS_FLASH_CFI 223 #define CONFIG_SYS_FLASH_EMPTY_INFO 224 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 225 226 /* NAND Flash on IFC */ 227 #define CONFIG_NAND_FSL_IFC 228 #define CONFIG_SYS_NAND_BASE 0xff800000 229 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 230 231 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 232 233 #define CONFIG_SYS_MAX_NAND_DEVICE 1 234 #define CONFIG_CMD_NAND 235 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 236 237 /* 8Bit NAND Flash - K9F1G08U0B */ 238 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 239 | CSPR_PORT_SIZE_8 \ 240 | CSPR_MSEL_NAND \ 241 | CSPR_V) 242 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 243 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 244 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 245 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 246 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 247 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 248 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 249 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 250 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 251 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 252 FTIM0_NAND_TWP(0x0c) | \ 253 FTIM0_NAND_TWCHT(0x08) | \ 254 FTIM0_NAND_TWH(0x06)) 255 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 256 FTIM1_NAND_TWBE(0x1d) | \ 257 FTIM1_NAND_TRR(0x08) | \ 258 FTIM1_NAND_TRP(0x0c)) 259 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 260 FTIM2_NAND_TREH(0x0a) | \ 261 FTIM2_NAND_TWHRE(0x18)) 262 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 263 264 #define CONFIG_SYS_NAND_DDR_LAW 11 265 266 /* Set up IFC registers for boot location NOR/NAND */ 267 #ifdef CONFIG_NAND 268 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 269 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 270 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 271 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 272 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 273 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 274 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 275 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 276 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 277 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 278 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 279 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 280 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 281 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 282 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 283 #else 284 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 285 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 286 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 287 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 288 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 289 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 290 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 291 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 292 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 293 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 294 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 295 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 296 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 297 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 298 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 299 #endif 300 301 /* CPLD on IFC, selected by CS2 */ 302 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 303 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 304 | CONFIG_SYS_CPLD_BASE) 305 306 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 307 | CSPR_PORT_SIZE_8 \ 308 | CSPR_MSEL_GPCM \ 309 | CSPR_V) 310 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 311 #define CONFIG_SYS_CSOR2 0x0 312 /* CPLD Timing parameters for IFC CS2 */ 313 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 314 FTIM0_GPCM_TEADC(0x0e) | \ 315 FTIM0_GPCM_TEAHC(0x0e)) 316 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 317 FTIM1_GPCM_TRAD(0x1f)) 318 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 319 FTIM2_GPCM_TCH(0x8) | \ 320 FTIM2_GPCM_TWP(0x1f)) 321 #define CONFIG_SYS_CS2_FTIM3 0x0 322 323 #if defined(CONFIG_RAMBOOT_SPIFLASH) 324 #define CONFIG_SYS_RAMBOOT 325 #define CONFIG_SYS_EXTRA_ENV_RELOC 326 #endif 327 328 #define CONFIG_BOARD_EARLY_INIT_R 329 330 #define CONFIG_SYS_INIT_RAM_LOCK 331 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 332 #define CONFIG_SYS_INIT_RAM_END 0x00004000 333 334 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 335 - GENERATED_GBL_DATA_SIZE) 336 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 337 338 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 339 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 340 341 /* 342 * Config the L2 Cache as L2 SRAM 343 */ 344 #if defined(CONFIG_SPL_BUILD) 345 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 346 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 347 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 348 #define CONFIG_SYS_L2_SIZE (256 << 10) 349 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 350 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 351 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 352 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 353 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 354 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 355 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 356 #elif defined(CONFIG_NAND) 357 #ifdef CONFIG_TPL_BUILD 358 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 359 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 360 #define CONFIG_SYS_L2_SIZE (256 << 10) 361 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 362 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 363 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 364 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 365 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 366 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 367 #else 368 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 369 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 370 #define CONFIG_SYS_L2_SIZE (256 << 10) 371 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 372 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 373 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 374 #endif 375 #endif 376 #endif 377 378 /* Serial Port */ 379 #define CONFIG_CONS_INDEX 1 380 #define CONFIG_SYS_NS16550 381 #define CONFIG_SYS_NS16550_SERIAL 382 #define CONFIG_SYS_NS16550_REG_SIZE 1 383 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 384 385 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 386 #define CONFIG_NS16550_MIN_FUNCTIONS 387 #endif 388 389 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 390 391 #define CONFIG_SYS_BAUDRATE_TABLE \ 392 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 393 394 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 395 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 396 397 /* Use the HUSH parser */ 398 #define CONFIG_SYS_HUSH_PARSER 399 400 /* 401 * Pass open firmware flat tree 402 */ 403 #define CONFIG_OF_LIBFDT 404 #define CONFIG_OF_BOARD_SETUP 405 #define CONFIG_OF_STDOUT_VIA_ALIAS 406 407 /* new uImage format support */ 408 #define CONFIG_FIT 409 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 410 411 #define CONFIG_SYS_I2C 412 #define CONFIG_SYS_I2C_FSL 413 #define CONFIG_SYS_FSL_I2C_SPEED 400000 414 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 415 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 416 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 417 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 418 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 419 420 /* I2C EEPROM */ 421 /* enable read and write access to EEPROM */ 422 #define CONFIG_CMD_EEPROM 423 #define CONFIG_SYS_I2C_MULTI_EEPROMS 424 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 425 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 426 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 427 428 #define CONFIG_CMD_I2C 429 430 /* eSPI - Enhanced SPI */ 431 #define CONFIG_FSL_ESPI 432 #define CONFIG_SPI_FLASH_SPANSION 433 #define CONFIG_SPI_FLASH_EON 434 #define CONFIG_CMD_SF 435 #define CONFIG_SF_DEFAULT_SPEED 10000000 436 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 437 438 #ifdef CONFIG_TSEC_ENET 439 #define CONFIG_MII /* MII PHY management */ 440 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 441 #define CONFIG_TSEC1 1 442 #define CONFIG_TSEC1_NAME "eTSEC1" 443 #define CONFIG_TSEC2 1 444 #define CONFIG_TSEC2_NAME "eTSEC2" 445 446 /* Default mode is RGMII mode */ 447 #define TSEC1_PHY_ADDR 0 448 #define TSEC2_PHY_ADDR 2 449 450 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 451 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 452 453 #define CONFIG_ETHPRIME "eTSEC1" 454 455 #define CONFIG_PHY_GIGE 456 #endif /* CONFIG_TSEC_ENET */ 457 458 /* 459 * Environment 460 */ 461 #if defined(CONFIG_SYS_RAMBOOT) 462 #if defined(CONFIG_RAMBOOT_SPIFLASH) 463 #define CONFIG_ENV_IS_IN_SPI_FLASH 464 #define CONFIG_ENV_SPI_BUS 0 465 #define CONFIG_ENV_SPI_CS 0 466 #define CONFIG_ENV_SPI_MAX_HZ 10000000 467 #define CONFIG_ENV_SPI_MODE 0 468 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 469 #define CONFIG_ENV_SECT_SIZE 0x10000 470 #define CONFIG_ENV_SIZE 0x2000 471 #endif 472 #elif defined(CONFIG_NAND) 473 #define CONFIG_ENV_IS_IN_NAND 474 #ifdef CONFIG_TPL_BUILD 475 #define CONFIG_ENV_SIZE 0x2000 476 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 477 #else 478 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 479 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 480 #endif 481 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE 482 #else 483 #define CONFIG_ENV_IS_IN_FLASH 484 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 485 #define CONFIG_ENV_SIZE 0x2000 486 #define CONFIG_ENV_SECT_SIZE 0x20000 487 #endif 488 489 #define CONFIG_LOADS_ECHO 490 #define CONFIG_SYS_LOADS_BAUD_CHANGE 491 492 /* 493 * Command line configuration. 494 */ 495 #define CONFIG_CMD_ERRATA 496 #define CONFIG_CMD_IRQ 497 #define CONFIG_CMD_MII 498 #define CONFIG_CMD_PING 499 #define CONFIG_CMD_REGINFO 500 501 /* Hash command with SHA acceleration supported in hardware */ 502 #ifdef CONFIG_FSL_CAAM 503 #define CONFIG_CMD_HASH 504 #define CONFIG_SHA_HW_ACCEL 505 #endif 506 507 /* 508 * Miscellaneous configurable options 509 */ 510 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 511 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 512 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 513 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 514 515 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 516 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 517 /* Print Buffer Size */ 518 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 519 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 520 521 /* 522 * For booting Linux, the board info and command line data 523 * have to be in the first 64 MB of memory, since this is 524 * the maximum mapped by the Linux kernel during initialization. 525 */ 526 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 527 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 528 529 /* 530 * Environment Configuration 531 */ 532 533 #ifdef CONFIG_TSEC_ENET 534 #define CONFIG_HAS_ETH0 535 #define CONFIG_HAS_ETH1 536 #endif 537 538 #define CONFIG_ROOTPATH "/opt/nfsroot" 539 #define CONFIG_BOOTFILE "uImage" 540 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 541 542 /* default location for tftp and bootm */ 543 #define CONFIG_LOADADDR 1000000 544 545 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 546 547 #define CONFIG_BAUDRATE 115200 548 549 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 550 551 #define CONFIG_EXTRA_ENV_SETTINGS \ 552 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 553 "netdev=eth0\0" \ 554 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 555 "loadaddr=1000000\0" \ 556 "consoledev=ttyS0\0" \ 557 "ramdiskaddr=2000000\0" \ 558 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 559 "fdtaddr=c00000\0" \ 560 "fdtfile=name/of/device-tree.dtb\0" \ 561 "othbootargs=ramdisk_size=600000\0" \ 562 563 #define CONFIG_RAMBOOTCOMMAND \ 564 "setenv bootargs root=/dev/ram rw " \ 565 "console=$consoledev,$baudrate $othbootargs; " \ 566 "tftp $ramdiskaddr $ramdiskfile;" \ 567 "tftp $loadaddr $bootfile;" \ 568 "tftp $fdtaddr $fdtfile;" \ 569 "bootm $loadaddr $ramdiskaddr $fdtaddr" 570 571 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 572 573 #include <asm/fsl_secure_boot.h> 574 575 #endif /* __CONFIG_H */ 576