1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_SPIFLASH 15 #define CONFIG_RAMBOOT_SPIFLASH 16 #define CONFIG_SYS_TEXT_BASE 0x11000000 17 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 18 #endif 19 20 #ifdef CONFIG_NAND 21 #ifdef CONFIG_TPL_BUILD 22 #define CONFIG_SPL_NAND_BOOT 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_NAND_INIT 25 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT 26 #define CONFIG_SPL_COMMON_INIT_DDR 27 #define CONFIG_SPL_MAX_SIZE (128 << 10) 28 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 30 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 31 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 32 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 33 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 34 #elif defined(CONFIG_SPL_BUILD) 35 #define CONFIG_SPL_INIT_MINIMAL 36 #define CONFIG_SPL_NAND_MINIMAL 37 #define CONFIG_SPL_FLUSH_IMAGE 38 #define CONFIG_SPL_TEXT_BASE 0xff800000 39 #define CONFIG_SPL_MAX_SIZE 8192 40 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 41 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 42 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 43 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 44 #endif 45 #define CONFIG_SPL_PAD_TO 0x20000 46 #define CONFIG_TPL_PAD_TO 0x20000 47 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 48 #define CONFIG_SYS_TEXT_BASE 0x11001000 49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 50 #endif 51 52 #ifndef CONFIG_SYS_TEXT_BASE 53 #define CONFIG_SYS_TEXT_BASE 0xeff40000 54 #endif 55 56 #ifndef CONFIG_RESET_VECTOR_ADDRESS 57 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 58 #endif 59 60 #ifdef CONFIG_SPL_BUILD 61 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 62 #else 63 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 64 #endif 65 66 #ifdef CONFIG_SPL_BUILD 67 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 68 #endif 69 70 /* High Level Configuration Options */ 71 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 72 73 #ifdef CONFIG_PCI 74 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 75 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 76 #define CONFIG_PCI_INDIRECT_BRIDGE 77 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 78 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 79 80 /* 81 * PCI Windows 82 * Memory space is mapped 1-1, but I/O space must start from 0. 83 */ 84 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 85 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 86 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 87 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 88 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 89 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 90 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 91 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 92 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 93 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 94 95 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 96 #endif 97 98 #define CONFIG_TSEC_ENET 99 #define CONFIG_ENV_OVERWRITE 100 101 #define CONFIG_DDR_CLK_FREQ 100000000 102 #define CONFIG_SYS_CLK_FREQ 66666666 103 104 #define CONFIG_HWCONFIG 105 106 /* 107 * These can be toggled for performance analysis, otherwise use default. 108 */ 109 #define CONFIG_L2_CACHE /* toggle L2 cache */ 110 #define CONFIG_BTB /* toggle branch predition */ 111 112 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 113 114 #define CONFIG_ENABLE_36BIT_PHYS 115 116 #define CONFIG_ADDR_MAP 1 117 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 118 119 #define CONFIG_SYS_MEMTEST_START 0x00200000 120 #define CONFIG_SYS_MEMTEST_END 0x00400000 121 #define CONFIG_PANIC_HANG 122 123 /* DDR Setup */ 124 #define CONFIG_DDR_SPD 125 #define CONFIG_SYS_SPD_BUS_NUM 0 126 #define SPD_EEPROM_ADDRESS 0x50 127 #define CONFIG_SYS_DDR_RAW_TIMING 128 129 /* DDR ECC Setup*/ 130 #define CONFIG_DDR_ECC 131 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 132 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 133 134 #define CONFIG_SYS_SDRAM_SIZE 512 135 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 136 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 137 138 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 139 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 140 141 #define CONFIG_SYS_CCSRBAR 0xffe00000 142 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 143 144 /* Platform SRAM setting */ 145 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 146 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 147 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 148 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 149 150 /* 151 * IFC Definitions 152 */ 153 /* NOR Flash on IFC */ 154 #define CONFIG_SYS_FLASH_BASE 0xec000000 155 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 156 157 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 158 159 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 160 #define CONFIG_SYS_MAX_FLASH_BANKS 1 161 162 #define CONFIG_SYS_FLASH_QUIET_TEST 163 #define CONFIG_FLASH_SHOW_PROGRESS 45 164 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 165 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 166 167 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 168 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 169 CSPR_PORT_SIZE_16 | \ 170 CSPR_MSEL_NOR | \ 171 CSPR_V) 172 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 173 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 174 175 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 176 FTIM0_NOR_TEADC(0x5) | \ 177 FTIM0_NOR_TEAHC(0x5)) 178 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 179 FTIM1_NOR_TRAD_NOR(0x1A) |\ 180 FTIM1_NOR_TSEQRAD_NOR(0x13)) 181 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 182 FTIM2_NOR_TCH(0x4) | \ 183 FTIM2_NOR_TWPH(0x0E) | \ 184 FTIM2_NOR_TWP(0x1c)) 185 #define CONFIG_SYS_NOR_FTIM3 0x0 186 187 /* CFI for NOR Flash */ 188 #define CONFIG_FLASH_CFI_DRIVER 189 #define CONFIG_SYS_FLASH_CFI 190 #define CONFIG_SYS_FLASH_EMPTY_INFO 191 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 192 193 /* NAND Flash on IFC */ 194 #define CONFIG_NAND_FSL_IFC 195 #define CONFIG_SYS_NAND_BASE 0xff800000 196 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 197 198 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 199 200 #define CONFIG_SYS_MAX_NAND_DEVICE 1 201 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 202 203 /* 8Bit NAND Flash - K9F1G08U0B */ 204 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 205 | CSPR_PORT_SIZE_8 \ 206 | CSPR_MSEL_NAND \ 207 | CSPR_V) 208 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 209 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 210 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 211 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 212 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 213 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 214 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 215 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 216 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 217 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 218 FTIM0_NAND_TWP(0x0c) | \ 219 FTIM0_NAND_TWCHT(0x08) | \ 220 FTIM0_NAND_TWH(0x06)) 221 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 222 FTIM1_NAND_TWBE(0x1d) | \ 223 FTIM1_NAND_TRR(0x08) | \ 224 FTIM1_NAND_TRP(0x0c)) 225 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 226 FTIM2_NAND_TREH(0x0a) | \ 227 FTIM2_NAND_TWHRE(0x18)) 228 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 229 230 #define CONFIG_SYS_NAND_DDR_LAW 11 231 232 /* Set up IFC registers for boot location NOR/NAND */ 233 #ifdef CONFIG_NAND 234 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 235 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 236 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 237 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 238 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 239 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 240 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 241 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 242 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 243 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 244 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 245 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 246 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 247 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 248 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 249 #else 250 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 251 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 252 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 253 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 254 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 255 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 256 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 257 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 258 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 259 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 260 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 261 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 262 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 263 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 264 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 265 #endif 266 267 /* CPLD on IFC, selected by CS2 */ 268 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 269 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 270 | CONFIG_SYS_CPLD_BASE) 271 272 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 273 | CSPR_PORT_SIZE_8 \ 274 | CSPR_MSEL_GPCM \ 275 | CSPR_V) 276 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 277 #define CONFIG_SYS_CSOR2 0x0 278 /* CPLD Timing parameters for IFC CS2 */ 279 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 280 FTIM0_GPCM_TEADC(0x0e) | \ 281 FTIM0_GPCM_TEAHC(0x0e)) 282 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 283 FTIM1_GPCM_TRAD(0x1f)) 284 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 285 FTIM2_GPCM_TCH(0x8) | \ 286 FTIM2_GPCM_TWP(0x1f)) 287 #define CONFIG_SYS_CS2_FTIM3 0x0 288 289 #if defined(CONFIG_RAMBOOT_SPIFLASH) 290 #define CONFIG_SYS_RAMBOOT 291 #define CONFIG_SYS_EXTRA_ENV_RELOC 292 #endif 293 294 #define CONFIG_BOARD_EARLY_INIT_R 295 296 #define CONFIG_SYS_INIT_RAM_LOCK 297 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 298 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 299 300 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 301 - GENERATED_GBL_DATA_SIZE) 302 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 303 304 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 305 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 306 307 /* 308 * Config the L2 Cache as L2 SRAM 309 */ 310 #if defined(CONFIG_SPL_BUILD) 311 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 312 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 313 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 314 #define CONFIG_SYS_L2_SIZE (256 << 10) 315 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 316 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 317 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 318 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 319 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 320 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 321 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 322 #elif defined(CONFIG_NAND) 323 #ifdef CONFIG_TPL_BUILD 324 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 325 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 326 #define CONFIG_SYS_L2_SIZE (256 << 10) 327 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 328 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 329 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 330 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 331 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 332 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 333 #else 334 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 335 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 336 #define CONFIG_SYS_L2_SIZE (256 << 10) 337 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 338 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 339 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 340 #endif 341 #endif 342 #endif 343 344 /* Serial Port */ 345 #define CONFIG_CONS_INDEX 1 346 #define CONFIG_SYS_NS16550_SERIAL 347 #define CONFIG_SYS_NS16550_REG_SIZE 1 348 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 349 350 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 351 #define CONFIG_NS16550_MIN_FUNCTIONS 352 #endif 353 354 #define CONFIG_SYS_BAUDRATE_TABLE \ 355 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 356 357 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 358 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 359 360 #define CONFIG_SYS_I2C 361 #define CONFIG_SYS_I2C_FSL 362 #define CONFIG_SYS_FSL_I2C_SPEED 400000 363 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 364 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 365 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 366 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 367 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 368 369 /* I2C EEPROM */ 370 /* enable read and write access to EEPROM */ 371 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 372 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 373 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 374 375 /* eSPI - Enhanced SPI */ 376 #define CONFIG_SF_DEFAULT_SPEED 10000000 377 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 378 379 #ifdef CONFIG_TSEC_ENET 380 #define CONFIG_MII /* MII PHY management */ 381 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 382 #define CONFIG_TSEC1 1 383 #define CONFIG_TSEC1_NAME "eTSEC1" 384 #define CONFIG_TSEC2 1 385 #define CONFIG_TSEC2_NAME "eTSEC2" 386 387 /* Default mode is RGMII mode */ 388 #define TSEC1_PHY_ADDR 0 389 #define TSEC2_PHY_ADDR 2 390 391 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 392 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 393 394 #define CONFIG_ETHPRIME "eTSEC1" 395 #endif /* CONFIG_TSEC_ENET */ 396 397 /* 398 * Environment 399 */ 400 #if defined(CONFIG_SYS_RAMBOOT) 401 #if defined(CONFIG_RAMBOOT_SPIFLASH) 402 #define CONFIG_ENV_SPI_BUS 0 403 #define CONFIG_ENV_SPI_CS 0 404 #define CONFIG_ENV_SPI_MAX_HZ 10000000 405 #define CONFIG_ENV_SPI_MODE 0 406 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 407 #define CONFIG_ENV_SECT_SIZE 0x10000 408 #define CONFIG_ENV_SIZE 0x2000 409 #endif 410 #elif defined(CONFIG_NAND) 411 #ifdef CONFIG_TPL_BUILD 412 #define CONFIG_ENV_SIZE 0x2000 413 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 414 #else 415 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 416 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 417 #endif 418 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE 419 #else 420 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 421 #define CONFIG_ENV_SIZE 0x2000 422 #define CONFIG_ENV_SECT_SIZE 0x20000 423 #endif 424 425 #define CONFIG_LOADS_ECHO 426 #define CONFIG_SYS_LOADS_BAUD_CHANGE 427 428 /* 429 * Miscellaneous configurable options 430 */ 431 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 432 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 433 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 434 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 435 436 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 437 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 438 /* Print Buffer Size */ 439 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 440 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 441 442 /* 443 * For booting Linux, the board info and command line data 444 * have to be in the first 64 MB of memory, since this is 445 * the maximum mapped by the Linux kernel during initialization. 446 */ 447 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 448 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 449 450 /* 451 * Environment Configuration 452 */ 453 454 #ifdef CONFIG_TSEC_ENET 455 #define CONFIG_HAS_ETH0 456 #define CONFIG_HAS_ETH1 457 #endif 458 459 #define CONFIG_ROOTPATH "/opt/nfsroot" 460 #define CONFIG_BOOTFILE "uImage" 461 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 462 463 /* default location for tftp and bootm */ 464 #define CONFIG_LOADADDR 1000000 465 466 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 467 468 #define CONFIG_EXTRA_ENV_SETTINGS \ 469 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 470 "netdev=eth0\0" \ 471 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 472 "loadaddr=1000000\0" \ 473 "consoledev=ttyS0\0" \ 474 "ramdiskaddr=2000000\0" \ 475 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 476 "fdtaddr=1e00000\0" \ 477 "fdtfile=name/of/device-tree.dtb\0" \ 478 "othbootargs=ramdisk_size=600000\0" \ 479 480 #define CONFIG_RAMBOOTCOMMAND \ 481 "setenv bootargs root=/dev/ram rw " \ 482 "console=$consoledev,$baudrate $othbootargs; " \ 483 "tftp $ramdiskaddr $ramdiskfile;" \ 484 "tftp $loadaddr $bootfile;" \ 485 "tftp $fdtaddr $fdtfile;" \ 486 "bootm $loadaddr $ramdiskaddr $fdtaddr" 487 488 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 489 490 #include <asm/fsl_secure_boot.h> 491 492 #endif /* __CONFIG_H */ 493