1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_SPIFLASH 15 #define CONFIG_RAMBOOT_SPIFLASH 16 #define CONFIG_SYS_TEXT_BASE 0x11000000 17 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 18 #endif 19 20 #ifdef CONFIG_NAND 21 #ifdef CONFIG_TPL_BUILD 22 #define CONFIG_SPL_NAND_BOOT 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_NAND_INIT 25 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT 26 #define CONFIG_SPL_COMMON_INIT_DDR 27 #define CONFIG_SPL_MAX_SIZE (128 << 10) 28 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 30 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 31 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 32 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 33 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 34 #elif defined(CONFIG_SPL_BUILD) 35 #define CONFIG_SPL_INIT_MINIMAL 36 #define CONFIG_SPL_NAND_MINIMAL 37 #define CONFIG_SPL_FLUSH_IMAGE 38 #define CONFIG_SPL_TEXT_BASE 0xff800000 39 #define CONFIG_SPL_MAX_SIZE 8192 40 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 41 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 42 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 43 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 44 #endif 45 #define CONFIG_SPL_PAD_TO 0x20000 46 #define CONFIG_TPL_PAD_TO 0x20000 47 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 48 #define CONFIG_SYS_TEXT_BASE 0x11001000 49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 50 #endif 51 52 #ifndef CONFIG_SYS_TEXT_BASE 53 #define CONFIG_SYS_TEXT_BASE 0xeff40000 54 #endif 55 56 #ifndef CONFIG_RESET_VECTOR_ADDRESS 57 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 58 #endif 59 60 #ifdef CONFIG_SPL_BUILD 61 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 62 #else 63 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 64 #endif 65 66 #ifdef CONFIG_SPL_BUILD 67 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 68 #endif 69 70 /* High Level Configuration Options */ 71 #define CONFIG_BOOKE /* BOOKE */ 72 #define CONFIG_E500 /* BOOKE e500 family */ 73 #define CONFIG_FSL_IFC /* Enable IFC Support */ 74 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 75 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 76 77 #ifdef CONFIG_PCI 78 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 79 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 80 #define CONFIG_PCI_INDIRECT_BRIDGE 81 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 82 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 83 84 #define CONFIG_CMD_PCI 85 86 /* 87 * PCI Windows 88 * Memory space is mapped 1-1, but I/O space must start from 0. 89 */ 90 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 91 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 92 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 93 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 94 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 95 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 96 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 97 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 98 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 99 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 100 101 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 102 #define CONFIG_DOS_PARTITION 103 #endif 104 105 #define CONFIG_FSL_LAW /* Use common FSL init code */ 106 #define CONFIG_TSEC_ENET 107 #define CONFIG_ENV_OVERWRITE 108 109 #define CONFIG_DDR_CLK_FREQ 100000000 110 #define CONFIG_SYS_CLK_FREQ 66666666 111 112 #define CONFIG_HWCONFIG 113 114 /* 115 * These can be toggled for performance analysis, otherwise use default. 116 */ 117 #define CONFIG_L2_CACHE /* toggle L2 cache */ 118 #define CONFIG_BTB /* toggle branch predition */ 119 120 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 121 122 #define CONFIG_ENABLE_36BIT_PHYS 123 124 #define CONFIG_ADDR_MAP 1 125 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 126 127 #define CONFIG_SYS_MEMTEST_START 0x00200000 128 #define CONFIG_SYS_MEMTEST_END 0x00400000 129 #define CONFIG_PANIC_HANG 130 131 /* DDR Setup */ 132 #define CONFIG_SYS_FSL_DDR3 133 #define CONFIG_DDR_SPD 134 #define CONFIG_SYS_SPD_BUS_NUM 0 135 #define SPD_EEPROM_ADDRESS 0x50 136 #define CONFIG_SYS_DDR_RAW_TIMING 137 138 /* DDR ECC Setup*/ 139 #define CONFIG_DDR_ECC 140 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 141 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 142 143 #define CONFIG_SYS_SDRAM_SIZE 512 144 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 145 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 146 147 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 148 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 149 150 #define CONFIG_SYS_CCSRBAR 0xffe00000 151 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 152 153 /* Platform SRAM setting */ 154 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 155 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 156 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 157 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 158 159 #ifdef CONFIG_SPL_BUILD 160 #define CONFIG_SYS_NO_FLASH 161 #endif 162 163 /* 164 * IFC Definitions 165 */ 166 /* NOR Flash on IFC */ 167 #define CONFIG_SYS_FLASH_BASE 0xec000000 168 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 169 170 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 171 172 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 173 #define CONFIG_SYS_MAX_FLASH_BANKS 1 174 175 #define CONFIG_SYS_FLASH_QUIET_TEST 176 #define CONFIG_FLASH_SHOW_PROGRESS 45 177 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 178 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 179 180 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 181 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 182 CSPR_PORT_SIZE_16 | \ 183 CSPR_MSEL_NOR | \ 184 CSPR_V) 185 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 186 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 187 188 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 189 FTIM0_NOR_TEADC(0x5) | \ 190 FTIM0_NOR_TEAHC(0x5)) 191 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 192 FTIM1_NOR_TRAD_NOR(0x1A) |\ 193 FTIM1_NOR_TSEQRAD_NOR(0x13)) 194 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 195 FTIM2_NOR_TCH(0x4) | \ 196 FTIM2_NOR_TWPH(0x0E) | \ 197 FTIM2_NOR_TWP(0x1c)) 198 #define CONFIG_SYS_NOR_FTIM3 0x0 199 200 /* CFI for NOR Flash */ 201 #define CONFIG_FLASH_CFI_DRIVER 202 #define CONFIG_SYS_FLASH_CFI 203 #define CONFIG_SYS_FLASH_EMPTY_INFO 204 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 205 206 /* NAND Flash on IFC */ 207 #define CONFIG_NAND_FSL_IFC 208 #define CONFIG_SYS_NAND_BASE 0xff800000 209 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 210 211 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 212 213 #define CONFIG_SYS_MAX_NAND_DEVICE 1 214 #define CONFIG_CMD_NAND 215 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 216 217 /* 8Bit NAND Flash - K9F1G08U0B */ 218 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 219 | CSPR_PORT_SIZE_8 \ 220 | CSPR_MSEL_NAND \ 221 | CSPR_V) 222 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 223 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 224 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 225 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 226 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 227 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 228 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 229 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 230 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 231 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 232 FTIM0_NAND_TWP(0x0c) | \ 233 FTIM0_NAND_TWCHT(0x08) | \ 234 FTIM0_NAND_TWH(0x06)) 235 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 236 FTIM1_NAND_TWBE(0x1d) | \ 237 FTIM1_NAND_TRR(0x08) | \ 238 FTIM1_NAND_TRP(0x0c)) 239 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 240 FTIM2_NAND_TREH(0x0a) | \ 241 FTIM2_NAND_TWHRE(0x18)) 242 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 243 244 #define CONFIG_SYS_NAND_DDR_LAW 11 245 246 /* Set up IFC registers for boot location NOR/NAND */ 247 #ifdef CONFIG_NAND 248 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 249 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 250 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 251 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 252 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 253 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 254 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 255 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 256 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 257 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 258 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 259 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 260 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 261 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 262 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 263 #else 264 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 265 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 266 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 267 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 268 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 269 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 270 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 271 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 272 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 273 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 274 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 275 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 276 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 277 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 278 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 279 #endif 280 281 /* CPLD on IFC, selected by CS2 */ 282 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 283 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 284 | CONFIG_SYS_CPLD_BASE) 285 286 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 287 | CSPR_PORT_SIZE_8 \ 288 | CSPR_MSEL_GPCM \ 289 | CSPR_V) 290 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 291 #define CONFIG_SYS_CSOR2 0x0 292 /* CPLD Timing parameters for IFC CS2 */ 293 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 294 FTIM0_GPCM_TEADC(0x0e) | \ 295 FTIM0_GPCM_TEAHC(0x0e)) 296 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 297 FTIM1_GPCM_TRAD(0x1f)) 298 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 299 FTIM2_GPCM_TCH(0x8) | \ 300 FTIM2_GPCM_TWP(0x1f)) 301 #define CONFIG_SYS_CS2_FTIM3 0x0 302 303 #if defined(CONFIG_RAMBOOT_SPIFLASH) 304 #define CONFIG_SYS_RAMBOOT 305 #define CONFIG_SYS_EXTRA_ENV_RELOC 306 #endif 307 308 #define CONFIG_BOARD_EARLY_INIT_R 309 310 #define CONFIG_SYS_INIT_RAM_LOCK 311 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 312 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 313 314 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 315 - GENERATED_GBL_DATA_SIZE) 316 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 317 318 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 319 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 320 321 /* 322 * Config the L2 Cache as L2 SRAM 323 */ 324 #if defined(CONFIG_SPL_BUILD) 325 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 326 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 327 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 328 #define CONFIG_SYS_L2_SIZE (256 << 10) 329 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 330 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 331 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 332 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 333 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 334 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 335 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 336 #elif defined(CONFIG_NAND) 337 #ifdef CONFIG_TPL_BUILD 338 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 339 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 340 #define CONFIG_SYS_L2_SIZE (256 << 10) 341 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 342 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 343 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 344 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 345 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 346 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 347 #else 348 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 349 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 350 #define CONFIG_SYS_L2_SIZE (256 << 10) 351 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 352 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 353 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 354 #endif 355 #endif 356 #endif 357 358 /* Serial Port */ 359 #define CONFIG_CONS_INDEX 1 360 #define CONFIG_SYS_NS16550_SERIAL 361 #define CONFIG_SYS_NS16550_REG_SIZE 1 362 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 363 364 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 365 #define CONFIG_NS16550_MIN_FUNCTIONS 366 #endif 367 368 #define CONFIG_SYS_BAUDRATE_TABLE \ 369 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 370 371 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 372 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 373 374 #define CONFIG_SYS_I2C 375 #define CONFIG_SYS_I2C_FSL 376 #define CONFIG_SYS_FSL_I2C_SPEED 400000 377 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 378 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 379 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 380 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 381 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 382 383 /* I2C EEPROM */ 384 /* enable read and write access to EEPROM */ 385 #define CONFIG_CMD_EEPROM 386 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 387 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 388 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 389 390 /* eSPI - Enhanced SPI */ 391 #define CONFIG_SF_DEFAULT_SPEED 10000000 392 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 393 394 #ifdef CONFIG_TSEC_ENET 395 #define CONFIG_MII /* MII PHY management */ 396 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 397 #define CONFIG_TSEC1 1 398 #define CONFIG_TSEC1_NAME "eTSEC1" 399 #define CONFIG_TSEC2 1 400 #define CONFIG_TSEC2_NAME "eTSEC2" 401 402 /* Default mode is RGMII mode */ 403 #define TSEC1_PHY_ADDR 0 404 #define TSEC2_PHY_ADDR 2 405 406 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 407 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 408 409 #define CONFIG_ETHPRIME "eTSEC1" 410 411 #define CONFIG_PHY_GIGE 412 #endif /* CONFIG_TSEC_ENET */ 413 414 /* 415 * Environment 416 */ 417 #if defined(CONFIG_SYS_RAMBOOT) 418 #if defined(CONFIG_RAMBOOT_SPIFLASH) 419 #define CONFIG_ENV_IS_IN_SPI_FLASH 420 #define CONFIG_ENV_SPI_BUS 0 421 #define CONFIG_ENV_SPI_CS 0 422 #define CONFIG_ENV_SPI_MAX_HZ 10000000 423 #define CONFIG_ENV_SPI_MODE 0 424 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 425 #define CONFIG_ENV_SECT_SIZE 0x10000 426 #define CONFIG_ENV_SIZE 0x2000 427 #endif 428 #elif defined(CONFIG_NAND) 429 #define CONFIG_ENV_IS_IN_NAND 430 #ifdef CONFIG_TPL_BUILD 431 #define CONFIG_ENV_SIZE 0x2000 432 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 433 #else 434 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 435 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 436 #endif 437 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE 438 #else 439 #define CONFIG_ENV_IS_IN_FLASH 440 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 441 #define CONFIG_ENV_SIZE 0x2000 442 #define CONFIG_ENV_SECT_SIZE 0x20000 443 #endif 444 445 #define CONFIG_LOADS_ECHO 446 #define CONFIG_SYS_LOADS_BAUD_CHANGE 447 448 /* 449 * Command line configuration. 450 */ 451 #define CONFIG_CMD_ERRATA 452 #define CONFIG_CMD_IRQ 453 #define CONFIG_CMD_REGINFO 454 455 /* Hash command with SHA acceleration supported in hardware */ 456 #ifdef CONFIG_FSL_CAAM 457 #define CONFIG_CMD_HASH 458 #define CONFIG_SHA_HW_ACCEL 459 #endif 460 461 /* 462 * Miscellaneous configurable options 463 */ 464 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 465 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 466 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 467 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 468 469 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 470 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 471 /* Print Buffer Size */ 472 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 473 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 474 475 /* 476 * For booting Linux, the board info and command line data 477 * have to be in the first 64 MB of memory, since this is 478 * the maximum mapped by the Linux kernel during initialization. 479 */ 480 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 481 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 482 483 /* 484 * Environment Configuration 485 */ 486 487 #ifdef CONFIG_TSEC_ENET 488 #define CONFIG_HAS_ETH0 489 #define CONFIG_HAS_ETH1 490 #endif 491 492 #define CONFIG_ROOTPATH "/opt/nfsroot" 493 #define CONFIG_BOOTFILE "uImage" 494 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 495 496 /* default location for tftp and bootm */ 497 #define CONFIG_LOADADDR 1000000 498 499 500 #define CONFIG_BAUDRATE 115200 501 502 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 503 504 #define CONFIG_EXTRA_ENV_SETTINGS \ 505 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 506 "netdev=eth0\0" \ 507 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 508 "loadaddr=1000000\0" \ 509 "consoledev=ttyS0\0" \ 510 "ramdiskaddr=2000000\0" \ 511 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 512 "fdtaddr=1e00000\0" \ 513 "fdtfile=name/of/device-tree.dtb\0" \ 514 "othbootargs=ramdisk_size=600000\0" \ 515 516 #define CONFIG_RAMBOOTCOMMAND \ 517 "setenv bootargs root=/dev/ram rw " \ 518 "console=$consoledev,$baudrate $othbootargs; " \ 519 "tftp $ramdiskaddr $ramdiskfile;" \ 520 "tftp $loadaddr $bootfile;" \ 521 "tftp $fdtaddr $fdtfile;" \ 522 "bootm $loadaddr $ramdiskaddr $fdtaddr" 523 524 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 525 526 #include <asm/fsl_secure_boot.h> 527 528 #endif /* __CONFIG_H */ 529