1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_SPIFLASH 15 #define CONFIG_RAMBOOT_SPIFLASH 16 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 17 #endif 18 19 #ifdef CONFIG_NAND 20 #ifdef CONFIG_TPL_BUILD 21 #define CONFIG_SPL_NAND_BOOT 22 #define CONFIG_SPL_FLUSH_IMAGE 23 #define CONFIG_SPL_NAND_INIT 24 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT 25 #define CONFIG_SPL_COMMON_INIT_DDR 26 #define CONFIG_SPL_MAX_SIZE (128 << 10) 27 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 28 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 29 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 30 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 31 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 32 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 33 #elif defined(CONFIG_SPL_BUILD) 34 #define CONFIG_SPL_INIT_MINIMAL 35 #define CONFIG_SPL_NAND_MINIMAL 36 #define CONFIG_SPL_FLUSH_IMAGE 37 #define CONFIG_SPL_TEXT_BASE 0xff800000 38 #define CONFIG_SPL_MAX_SIZE 8192 39 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 40 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 41 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 42 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 43 #endif 44 #define CONFIG_SPL_PAD_TO 0x20000 45 #define CONFIG_TPL_PAD_TO 0x20000 46 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 47 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 48 #endif 49 50 #ifndef CONFIG_RESET_VECTOR_ADDRESS 51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 52 #endif 53 54 #ifdef CONFIG_SPL_BUILD 55 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 56 #else 57 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 58 #endif 59 60 #ifdef CONFIG_SPL_BUILD 61 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 62 #endif 63 64 /* High Level Configuration Options */ 65 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 66 67 #ifdef CONFIG_PCI 68 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 69 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 70 #define CONFIG_PCI_INDIRECT_BRIDGE 71 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 72 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 73 74 /* 75 * PCI Windows 76 * Memory space is mapped 1-1, but I/O space must start from 0. 77 */ 78 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 79 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 80 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 81 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 82 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 83 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 84 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 85 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 86 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 87 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 88 89 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 90 #endif 91 92 #define CONFIG_TSEC_ENET 93 #define CONFIG_ENV_OVERWRITE 94 95 #define CONFIG_DDR_CLK_FREQ 100000000 96 #define CONFIG_SYS_CLK_FREQ 66666666 97 98 #define CONFIG_HWCONFIG 99 100 /* 101 * These can be toggled for performance analysis, otherwise use default. 102 */ 103 #define CONFIG_L2_CACHE /* toggle L2 cache */ 104 #define CONFIG_BTB /* toggle branch predition */ 105 106 107 #define CONFIG_ENABLE_36BIT_PHYS 108 109 #define CONFIG_ADDR_MAP 1 110 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 111 112 #define CONFIG_SYS_MEMTEST_START 0x00200000 113 #define CONFIG_SYS_MEMTEST_END 0x00400000 114 115 /* DDR Setup */ 116 #define CONFIG_DDR_SPD 117 #define CONFIG_SYS_SPD_BUS_NUM 0 118 #define SPD_EEPROM_ADDRESS 0x50 119 #define CONFIG_SYS_DDR_RAW_TIMING 120 121 /* DDR ECC Setup*/ 122 #define CONFIG_DDR_ECC 123 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 124 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 125 126 #define CONFIG_SYS_SDRAM_SIZE 512 127 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 128 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 129 130 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 131 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 132 133 #define CONFIG_SYS_CCSRBAR 0xffe00000 134 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 135 136 /* Platform SRAM setting */ 137 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 138 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 139 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 140 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 141 142 /* 143 * IFC Definitions 144 */ 145 /* NOR Flash on IFC */ 146 #define CONFIG_SYS_FLASH_BASE 0xec000000 147 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 148 149 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 150 151 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 152 #define CONFIG_SYS_MAX_FLASH_BANKS 1 153 154 #define CONFIG_SYS_FLASH_QUIET_TEST 155 #define CONFIG_FLASH_SHOW_PROGRESS 45 156 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 157 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 158 159 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 160 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 161 CSPR_PORT_SIZE_16 | \ 162 CSPR_MSEL_NOR | \ 163 CSPR_V) 164 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 165 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 166 167 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 168 FTIM0_NOR_TEADC(0x5) | \ 169 FTIM0_NOR_TEAHC(0x5)) 170 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 171 FTIM1_NOR_TRAD_NOR(0x1A) |\ 172 FTIM1_NOR_TSEQRAD_NOR(0x13)) 173 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 174 FTIM2_NOR_TCH(0x4) | \ 175 FTIM2_NOR_TWPH(0x0E) | \ 176 FTIM2_NOR_TWP(0x1c)) 177 #define CONFIG_SYS_NOR_FTIM3 0x0 178 179 /* CFI for NOR Flash */ 180 #define CONFIG_FLASH_CFI_DRIVER 181 #define CONFIG_SYS_FLASH_CFI 182 #define CONFIG_SYS_FLASH_EMPTY_INFO 183 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 184 185 /* NAND Flash on IFC */ 186 #define CONFIG_NAND_FSL_IFC 187 #define CONFIG_SYS_NAND_BASE 0xff800000 188 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 189 190 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 191 192 #define CONFIG_SYS_MAX_NAND_DEVICE 1 193 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 194 195 /* 8Bit NAND Flash - K9F1G08U0B */ 196 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 197 | CSPR_PORT_SIZE_8 \ 198 | CSPR_MSEL_NAND \ 199 | CSPR_V) 200 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 201 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 202 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 203 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 204 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 205 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 206 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 207 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 208 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 209 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 210 FTIM0_NAND_TWP(0x0c) | \ 211 FTIM0_NAND_TWCHT(0x08) | \ 212 FTIM0_NAND_TWH(0x06)) 213 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 214 FTIM1_NAND_TWBE(0x1d) | \ 215 FTIM1_NAND_TRR(0x08) | \ 216 FTIM1_NAND_TRP(0x0c)) 217 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 218 FTIM2_NAND_TREH(0x0a) | \ 219 FTIM2_NAND_TWHRE(0x18)) 220 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 221 222 #define CONFIG_SYS_NAND_DDR_LAW 11 223 224 /* Set up IFC registers for boot location NOR/NAND */ 225 #ifdef CONFIG_NAND 226 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 227 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 228 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 229 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 230 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 231 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 232 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 233 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 234 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 235 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 236 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 237 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 238 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 239 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 240 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 241 #else 242 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 243 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 244 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 245 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 246 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 247 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 248 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 249 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 250 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 251 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 252 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 253 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 254 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 255 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 256 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 257 #endif 258 259 /* CPLD on IFC, selected by CS2 */ 260 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 261 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 262 | CONFIG_SYS_CPLD_BASE) 263 264 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 265 | CSPR_PORT_SIZE_8 \ 266 | CSPR_MSEL_GPCM \ 267 | CSPR_V) 268 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 269 #define CONFIG_SYS_CSOR2 0x0 270 /* CPLD Timing parameters for IFC CS2 */ 271 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 272 FTIM0_GPCM_TEADC(0x0e) | \ 273 FTIM0_GPCM_TEAHC(0x0e)) 274 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 275 FTIM1_GPCM_TRAD(0x1f)) 276 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 277 FTIM2_GPCM_TCH(0x8) | \ 278 FTIM2_GPCM_TWP(0x1f)) 279 #define CONFIG_SYS_CS2_FTIM3 0x0 280 281 #if defined(CONFIG_RAMBOOT_SPIFLASH) 282 #define CONFIG_SYS_RAMBOOT 283 #define CONFIG_SYS_EXTRA_ENV_RELOC 284 #endif 285 286 #define CONFIG_BOARD_EARLY_INIT_R 287 288 #define CONFIG_SYS_INIT_RAM_LOCK 289 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 290 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 291 292 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 293 - GENERATED_GBL_DATA_SIZE) 294 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 295 296 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 297 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 298 299 /* 300 * Config the L2 Cache as L2 SRAM 301 */ 302 #if defined(CONFIG_SPL_BUILD) 303 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 304 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 305 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 306 #define CONFIG_SYS_L2_SIZE (256 << 10) 307 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 308 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 309 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 310 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 311 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 312 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 313 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 314 #elif defined(CONFIG_NAND) 315 #ifdef CONFIG_TPL_BUILD 316 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 317 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 318 #define CONFIG_SYS_L2_SIZE (256 << 10) 319 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 320 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 321 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 322 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 323 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 324 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 325 #else 326 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 327 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 328 #define CONFIG_SYS_L2_SIZE (256 << 10) 329 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 330 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 331 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 332 #endif 333 #endif 334 #endif 335 336 /* Serial Port */ 337 #define CONFIG_SYS_NS16550_SERIAL 338 #define CONFIG_SYS_NS16550_REG_SIZE 1 339 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 340 341 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 342 #define CONFIG_NS16550_MIN_FUNCTIONS 343 #endif 344 345 #define CONFIG_SYS_BAUDRATE_TABLE \ 346 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 347 348 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 349 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 350 351 #define CONFIG_SYS_I2C 352 #define CONFIG_SYS_I2C_FSL 353 #define CONFIG_SYS_FSL_I2C_SPEED 400000 354 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 355 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 356 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 357 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 358 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 359 360 /* I2C EEPROM */ 361 /* enable read and write access to EEPROM */ 362 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 363 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 364 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 365 366 /* eSPI - Enhanced SPI */ 367 #define CONFIG_SF_DEFAULT_SPEED 10000000 368 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 369 370 #ifdef CONFIG_TSEC_ENET 371 #define CONFIG_MII /* MII PHY management */ 372 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 373 #define CONFIG_TSEC1 1 374 #define CONFIG_TSEC1_NAME "eTSEC1" 375 #define CONFIG_TSEC2 1 376 #define CONFIG_TSEC2_NAME "eTSEC2" 377 378 /* Default mode is RGMII mode */ 379 #define TSEC1_PHY_ADDR 0 380 #define TSEC2_PHY_ADDR 2 381 382 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 383 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 384 385 #define CONFIG_ETHPRIME "eTSEC1" 386 #endif /* CONFIG_TSEC_ENET */ 387 388 /* 389 * Environment 390 */ 391 #if defined(CONFIG_SYS_RAMBOOT) 392 #if defined(CONFIG_RAMBOOT_SPIFLASH) 393 #define CONFIG_ENV_SPI_BUS 0 394 #define CONFIG_ENV_SPI_CS 0 395 #define CONFIG_ENV_SPI_MAX_HZ 10000000 396 #define CONFIG_ENV_SPI_MODE 0 397 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 398 #define CONFIG_ENV_SECT_SIZE 0x10000 399 #define CONFIG_ENV_SIZE 0x2000 400 #endif 401 #elif defined(CONFIG_NAND) 402 #ifdef CONFIG_TPL_BUILD 403 #define CONFIG_ENV_SIZE 0x2000 404 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 405 #else 406 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 407 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 408 #endif 409 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE 410 #else 411 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 412 #define CONFIG_ENV_SIZE 0x2000 413 #define CONFIG_ENV_SECT_SIZE 0x20000 414 #endif 415 416 #define CONFIG_LOADS_ECHO 417 #define CONFIG_SYS_LOADS_BAUD_CHANGE 418 419 /* 420 * Miscellaneous configurable options 421 */ 422 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 423 424 /* 425 * For booting Linux, the board info and command line data 426 * have to be in the first 64 MB of memory, since this is 427 * the maximum mapped by the Linux kernel during initialization. 428 */ 429 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 430 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 431 432 /* 433 * Environment Configuration 434 */ 435 436 #ifdef CONFIG_TSEC_ENET 437 #define CONFIG_HAS_ETH0 438 #define CONFIG_HAS_ETH1 439 #endif 440 441 #define CONFIG_ROOTPATH "/opt/nfsroot" 442 #define CONFIG_BOOTFILE "uImage" 443 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 444 445 /* default location for tftp and bootm */ 446 #define CONFIG_LOADADDR 1000000 447 448 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 449 450 #define CONFIG_EXTRA_ENV_SETTINGS \ 451 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 452 "netdev=eth0\0" \ 453 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 454 "loadaddr=1000000\0" \ 455 "consoledev=ttyS0\0" \ 456 "ramdiskaddr=2000000\0" \ 457 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 458 "fdtaddr=1e00000\0" \ 459 "fdtfile=name/of/device-tree.dtb\0" \ 460 "othbootargs=ramdisk_size=600000\0" \ 461 462 #define CONFIG_RAMBOOTCOMMAND \ 463 "setenv bootargs root=/dev/ram rw " \ 464 "console=$consoledev,$baudrate $othbootargs; " \ 465 "tftp $ramdiskaddr $ramdiskfile;" \ 466 "tftp $loadaddr $bootfile;" \ 467 "tftp $fdtaddr $fdtfile;" \ 468 "bootm $loadaddr $ramdiskaddr $fdtaddr" 469 470 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 471 472 #include <asm/fsl_secure_boot.h> 473 474 #endif /* __CONFIG_H */ 475