1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_SPIFLASH 15 #define CONFIG_RAMBOOT_SPIFLASH 16 #define CONFIG_SYS_TEXT_BASE 0x11000000 17 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 18 #endif 19 20 #ifdef CONFIG_NAND 21 #ifdef CONFIG_TPL_BUILD 22 #define CONFIG_SPL_NAND_BOOT 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_NAND_INIT 25 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT 26 #define CONFIG_SPL_COMMON_INIT_DDR 27 #define CONFIG_SPL_MAX_SIZE (128 << 10) 28 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 30 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 31 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 32 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 33 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 34 #elif defined(CONFIG_SPL_BUILD) 35 #define CONFIG_SPL_INIT_MINIMAL 36 #define CONFIG_SPL_NAND_MINIMAL 37 #define CONFIG_SPL_FLUSH_IMAGE 38 #define CONFIG_SPL_TEXT_BASE 0xff800000 39 #define CONFIG_SPL_MAX_SIZE 8192 40 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 41 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 42 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 43 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 44 #endif 45 #define CONFIG_SPL_PAD_TO 0x20000 46 #define CONFIG_TPL_PAD_TO 0x20000 47 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 48 #define CONFIG_SYS_TEXT_BASE 0x11001000 49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 50 #endif 51 52 #ifndef CONFIG_SYS_TEXT_BASE 53 #define CONFIG_SYS_TEXT_BASE 0xeff40000 54 #endif 55 56 #ifndef CONFIG_RESET_VECTOR_ADDRESS 57 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 58 #endif 59 60 #ifdef CONFIG_SPL_BUILD 61 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 62 #else 63 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 64 #endif 65 66 #ifdef CONFIG_SPL_BUILD 67 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 68 #endif 69 70 /* High Level Configuration Options */ 71 #define CONFIG_FSL_IFC /* Enable IFC Support */ 72 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 73 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 74 75 #ifdef CONFIG_PCI 76 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 77 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 78 #define CONFIG_PCI_INDIRECT_BRIDGE 79 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 80 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 81 82 #define CONFIG_CMD_PCI 83 84 /* 85 * PCI Windows 86 * Memory space is mapped 1-1, but I/O space must start from 0. 87 */ 88 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 89 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 90 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 91 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 92 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 93 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 94 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 95 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 96 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 97 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 98 99 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 100 #endif 101 102 #define CONFIG_TSEC_ENET 103 #define CONFIG_ENV_OVERWRITE 104 105 #define CONFIG_DDR_CLK_FREQ 100000000 106 #define CONFIG_SYS_CLK_FREQ 66666666 107 108 #define CONFIG_HWCONFIG 109 110 /* 111 * These can be toggled for performance analysis, otherwise use default. 112 */ 113 #define CONFIG_L2_CACHE /* toggle L2 cache */ 114 #define CONFIG_BTB /* toggle branch predition */ 115 116 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 117 118 #define CONFIG_ENABLE_36BIT_PHYS 119 120 #define CONFIG_ADDR_MAP 1 121 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 122 123 #define CONFIG_SYS_MEMTEST_START 0x00200000 124 #define CONFIG_SYS_MEMTEST_END 0x00400000 125 #define CONFIG_PANIC_HANG 126 127 /* DDR Setup */ 128 #define CONFIG_DDR_SPD 129 #define CONFIG_SYS_SPD_BUS_NUM 0 130 #define SPD_EEPROM_ADDRESS 0x50 131 #define CONFIG_SYS_DDR_RAW_TIMING 132 133 /* DDR ECC Setup*/ 134 #define CONFIG_DDR_ECC 135 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 136 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 137 138 #define CONFIG_SYS_SDRAM_SIZE 512 139 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 140 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 141 142 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 143 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 144 145 #define CONFIG_SYS_CCSRBAR 0xffe00000 146 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 147 148 /* Platform SRAM setting */ 149 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 150 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 151 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 152 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 153 154 #ifdef CONFIG_SPL_BUILD 155 #define CONFIG_SYS_NO_FLASH 156 #endif 157 158 /* 159 * IFC Definitions 160 */ 161 /* NOR Flash on IFC */ 162 #define CONFIG_SYS_FLASH_BASE 0xec000000 163 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 164 165 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 166 167 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 168 #define CONFIG_SYS_MAX_FLASH_BANKS 1 169 170 #define CONFIG_SYS_FLASH_QUIET_TEST 171 #define CONFIG_FLASH_SHOW_PROGRESS 45 172 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 173 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 174 175 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 176 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 177 CSPR_PORT_SIZE_16 | \ 178 CSPR_MSEL_NOR | \ 179 CSPR_V) 180 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 181 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 182 183 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 184 FTIM0_NOR_TEADC(0x5) | \ 185 FTIM0_NOR_TEAHC(0x5)) 186 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 187 FTIM1_NOR_TRAD_NOR(0x1A) |\ 188 FTIM1_NOR_TSEQRAD_NOR(0x13)) 189 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 190 FTIM2_NOR_TCH(0x4) | \ 191 FTIM2_NOR_TWPH(0x0E) | \ 192 FTIM2_NOR_TWP(0x1c)) 193 #define CONFIG_SYS_NOR_FTIM3 0x0 194 195 /* CFI for NOR Flash */ 196 #define CONFIG_FLASH_CFI_DRIVER 197 #define CONFIG_SYS_FLASH_CFI 198 #define CONFIG_SYS_FLASH_EMPTY_INFO 199 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 200 201 /* NAND Flash on IFC */ 202 #define CONFIG_NAND_FSL_IFC 203 #define CONFIG_SYS_NAND_BASE 0xff800000 204 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 205 206 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 207 208 #define CONFIG_SYS_MAX_NAND_DEVICE 1 209 #define CONFIG_CMD_NAND 210 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 211 212 /* 8Bit NAND Flash - K9F1G08U0B */ 213 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 214 | CSPR_PORT_SIZE_8 \ 215 | CSPR_MSEL_NAND \ 216 | CSPR_V) 217 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 218 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 219 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 220 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 221 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 222 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 223 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 224 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 225 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 226 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 227 FTIM0_NAND_TWP(0x0c) | \ 228 FTIM0_NAND_TWCHT(0x08) | \ 229 FTIM0_NAND_TWH(0x06)) 230 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 231 FTIM1_NAND_TWBE(0x1d) | \ 232 FTIM1_NAND_TRR(0x08) | \ 233 FTIM1_NAND_TRP(0x0c)) 234 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 235 FTIM2_NAND_TREH(0x0a) | \ 236 FTIM2_NAND_TWHRE(0x18)) 237 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 238 239 #define CONFIG_SYS_NAND_DDR_LAW 11 240 241 /* Set up IFC registers for boot location NOR/NAND */ 242 #ifdef CONFIG_NAND 243 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 244 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 245 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 246 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 247 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 248 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 249 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 250 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 251 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 252 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 253 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 254 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 255 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 256 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 257 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 258 #else 259 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 260 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 261 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 262 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 263 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 264 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 265 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 266 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 267 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 268 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 269 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 270 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 271 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 272 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 273 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 274 #endif 275 276 /* CPLD on IFC, selected by CS2 */ 277 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 278 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 279 | CONFIG_SYS_CPLD_BASE) 280 281 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 282 | CSPR_PORT_SIZE_8 \ 283 | CSPR_MSEL_GPCM \ 284 | CSPR_V) 285 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 286 #define CONFIG_SYS_CSOR2 0x0 287 /* CPLD Timing parameters for IFC CS2 */ 288 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 289 FTIM0_GPCM_TEADC(0x0e) | \ 290 FTIM0_GPCM_TEAHC(0x0e)) 291 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 292 FTIM1_GPCM_TRAD(0x1f)) 293 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 294 FTIM2_GPCM_TCH(0x8) | \ 295 FTIM2_GPCM_TWP(0x1f)) 296 #define CONFIG_SYS_CS2_FTIM3 0x0 297 298 #if defined(CONFIG_RAMBOOT_SPIFLASH) 299 #define CONFIG_SYS_RAMBOOT 300 #define CONFIG_SYS_EXTRA_ENV_RELOC 301 #endif 302 303 #define CONFIG_BOARD_EARLY_INIT_R 304 305 #define CONFIG_SYS_INIT_RAM_LOCK 306 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 307 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 308 309 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 310 - GENERATED_GBL_DATA_SIZE) 311 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 312 313 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 314 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 315 316 /* 317 * Config the L2 Cache as L2 SRAM 318 */ 319 #if defined(CONFIG_SPL_BUILD) 320 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 321 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 322 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 323 #define CONFIG_SYS_L2_SIZE (256 << 10) 324 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 325 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 326 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 327 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 328 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 329 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 330 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 331 #elif defined(CONFIG_NAND) 332 #ifdef CONFIG_TPL_BUILD 333 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 334 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 335 #define CONFIG_SYS_L2_SIZE (256 << 10) 336 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 337 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 338 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 339 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 340 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 341 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 342 #else 343 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 344 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 345 #define CONFIG_SYS_L2_SIZE (256 << 10) 346 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 347 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 348 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 349 #endif 350 #endif 351 #endif 352 353 /* Serial Port */ 354 #define CONFIG_CONS_INDEX 1 355 #define CONFIG_SYS_NS16550_SERIAL 356 #define CONFIG_SYS_NS16550_REG_SIZE 1 357 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 358 359 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 360 #define CONFIG_NS16550_MIN_FUNCTIONS 361 #endif 362 363 #define CONFIG_SYS_BAUDRATE_TABLE \ 364 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 365 366 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 367 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 368 369 #define CONFIG_SYS_I2C 370 #define CONFIG_SYS_I2C_FSL 371 #define CONFIG_SYS_FSL_I2C_SPEED 400000 372 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 373 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 374 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 375 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 376 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 377 378 /* I2C EEPROM */ 379 /* enable read and write access to EEPROM */ 380 #define CONFIG_CMD_EEPROM 381 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 382 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 383 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 384 385 /* eSPI - Enhanced SPI */ 386 #define CONFIG_SF_DEFAULT_SPEED 10000000 387 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 388 389 #ifdef CONFIG_TSEC_ENET 390 #define CONFIG_MII /* MII PHY management */ 391 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 392 #define CONFIG_TSEC1 1 393 #define CONFIG_TSEC1_NAME "eTSEC1" 394 #define CONFIG_TSEC2 1 395 #define CONFIG_TSEC2_NAME "eTSEC2" 396 397 /* Default mode is RGMII mode */ 398 #define TSEC1_PHY_ADDR 0 399 #define TSEC2_PHY_ADDR 2 400 401 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 402 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 403 404 #define CONFIG_ETHPRIME "eTSEC1" 405 406 #define CONFIG_PHY_GIGE 407 #endif /* CONFIG_TSEC_ENET */ 408 409 /* 410 * Environment 411 */ 412 #if defined(CONFIG_SYS_RAMBOOT) 413 #if defined(CONFIG_RAMBOOT_SPIFLASH) 414 #define CONFIG_ENV_IS_IN_SPI_FLASH 415 #define CONFIG_ENV_SPI_BUS 0 416 #define CONFIG_ENV_SPI_CS 0 417 #define CONFIG_ENV_SPI_MAX_HZ 10000000 418 #define CONFIG_ENV_SPI_MODE 0 419 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 420 #define CONFIG_ENV_SECT_SIZE 0x10000 421 #define CONFIG_ENV_SIZE 0x2000 422 #endif 423 #elif defined(CONFIG_NAND) 424 #define CONFIG_ENV_IS_IN_NAND 425 #ifdef CONFIG_TPL_BUILD 426 #define CONFIG_ENV_SIZE 0x2000 427 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 428 #else 429 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 430 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 431 #endif 432 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE 433 #else 434 #define CONFIG_ENV_IS_IN_FLASH 435 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 436 #define CONFIG_ENV_SIZE 0x2000 437 #define CONFIG_ENV_SECT_SIZE 0x20000 438 #endif 439 440 #define CONFIG_LOADS_ECHO 441 #define CONFIG_SYS_LOADS_BAUD_CHANGE 442 443 /* 444 * Command line configuration. 445 */ 446 #define CONFIG_CMD_ERRATA 447 #define CONFIG_CMD_IRQ 448 #define CONFIG_CMD_REGINFO 449 450 /* Hash command with SHA acceleration supported in hardware */ 451 #ifdef CONFIG_FSL_CAAM 452 #define CONFIG_CMD_HASH 453 #define CONFIG_SHA_HW_ACCEL 454 #endif 455 456 /* 457 * Miscellaneous configurable options 458 */ 459 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 460 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 461 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 462 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 463 464 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 465 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 466 /* Print Buffer Size */ 467 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 468 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 469 470 /* 471 * For booting Linux, the board info and command line data 472 * have to be in the first 64 MB of memory, since this is 473 * the maximum mapped by the Linux kernel during initialization. 474 */ 475 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 476 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 477 478 /* 479 * Environment Configuration 480 */ 481 482 #ifdef CONFIG_TSEC_ENET 483 #define CONFIG_HAS_ETH0 484 #define CONFIG_HAS_ETH1 485 #endif 486 487 #define CONFIG_ROOTPATH "/opt/nfsroot" 488 #define CONFIG_BOOTFILE "uImage" 489 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 490 491 /* default location for tftp and bootm */ 492 #define CONFIG_LOADADDR 1000000 493 494 495 #define CONFIG_BAUDRATE 115200 496 497 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 498 499 #define CONFIG_EXTRA_ENV_SETTINGS \ 500 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 501 "netdev=eth0\0" \ 502 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 503 "loadaddr=1000000\0" \ 504 "consoledev=ttyS0\0" \ 505 "ramdiskaddr=2000000\0" \ 506 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 507 "fdtaddr=1e00000\0" \ 508 "fdtfile=name/of/device-tree.dtb\0" \ 509 "othbootargs=ramdisk_size=600000\0" \ 510 511 #define CONFIG_RAMBOOTCOMMAND \ 512 "setenv bootargs root=/dev/ram rw " \ 513 "console=$consoledev,$baudrate $othbootargs; " \ 514 "tftp $ramdiskaddr $ramdiskfile;" \ 515 "tftp $loadaddr $bootfile;" \ 516 "tftp $fdtaddr $fdtfile;" \ 517 "bootm $loadaddr $ramdiskaddr $fdtaddr" 518 519 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 520 521 #include <asm/fsl_secure_boot.h> 522 523 #endif /* __CONFIG_H */ 524