1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_C29XPCIE 17 #define CONFIG_PPC_C29X 18 #endif 19 20 #ifdef CONFIG_SPIFLASH 21 #define CONFIG_RAMBOOT_SPIFLASH 22 #define CONFIG_SYS_TEXT_BASE 0x11000000 23 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 24 #endif 25 26 #ifdef CONFIG_NAND 27 #ifdef CONFIG_TPL_BUILD 28 #define CONFIG_SPL_NAND_BOOT 29 #define CONFIG_SPL_FLUSH_IMAGE 30 #define CONFIG_SPL_ENV_SUPPORT 31 #define CONFIG_SPL_NAND_INIT 32 #define CONFIG_SPL_SERIAL_SUPPORT 33 #define CONFIG_SPL_LIBGENERIC_SUPPORT 34 #define CONFIG_SPL_LIBCOMMON_SUPPORT 35 #define CONFIG_SPL_I2C_SUPPORT 36 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 37 #define CONFIG_SPL_NAND_SUPPORT 38 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 39 #define CONFIG_SPL_COMMON_INIT_DDR 40 #define CONFIG_SPL_MAX_SIZE (128 << 10) 41 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 42 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 43 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 44 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 45 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 46 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 47 #elif defined(CONFIG_SPL_BUILD) 48 #define CONFIG_SPL_INIT_MINIMAL 49 #define CONFIG_SPL_SERIAL_SUPPORT 50 #define CONFIG_SPL_NAND_SUPPORT 51 #define CONFIG_SPL_NAND_MINIMAL 52 #define CONFIG_SPL_FLUSH_IMAGE 53 #define CONFIG_SPL_TEXT_BASE 0xff800000 54 #define CONFIG_SPL_MAX_SIZE 8192 55 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 56 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 57 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 58 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 59 #endif 60 #define CONFIG_SPL_PAD_TO 0x20000 61 #define CONFIG_TPL_PAD_TO 0x20000 62 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 63 #define CONFIG_SYS_TEXT_BASE 0x11001000 64 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 65 #endif 66 67 #ifndef CONFIG_SYS_TEXT_BASE 68 #define CONFIG_SYS_TEXT_BASE 0xeff40000 69 #endif 70 71 #ifndef CONFIG_RESET_VECTOR_ADDRESS 72 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 73 #endif 74 75 #ifdef CONFIG_SPL_BUILD 76 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 77 #else 78 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 79 #endif 80 81 #ifdef CONFIG_SPL_BUILD 82 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 83 #endif 84 85 /* High Level Configuration Options */ 86 #define CONFIG_BOOKE /* BOOKE */ 87 #define CONFIG_E500 /* BOOKE e500 family */ 88 #define CONFIG_FSL_IFC /* Enable IFC Support */ 89 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 90 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 91 92 #define CONFIG_PCI /* Enable PCI/PCIE */ 93 #ifdef CONFIG_PCI 94 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 95 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 96 #define CONFIG_PCI_INDIRECT_BRIDGE 97 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 98 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 99 100 #define CONFIG_CMD_PCI 101 102 /* 103 * PCI Windows 104 * Memory space is mapped 1-1, but I/O space must start from 0. 105 */ 106 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 107 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 108 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 109 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 110 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 111 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 112 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 113 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 114 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 115 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 116 117 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 118 119 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 120 #define CONFIG_DOS_PARTITION 121 #endif 122 123 #define CONFIG_FSL_LAW /* Use common FSL init code */ 124 #define CONFIG_TSEC_ENET 125 #define CONFIG_ENV_OVERWRITE 126 127 #define CONFIG_DDR_CLK_FREQ 100000000 128 #define CONFIG_SYS_CLK_FREQ 66666666 129 130 #define CONFIG_HWCONFIG 131 132 /* 133 * These can be toggled for performance analysis, otherwise use default. 134 */ 135 #define CONFIG_L2_CACHE /* toggle L2 cache */ 136 #define CONFIG_BTB /* toggle branch predition */ 137 138 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 139 140 #define CONFIG_ENABLE_36BIT_PHYS 141 142 #define CONFIG_ADDR_MAP 1 143 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 144 145 #define CONFIG_SYS_MEMTEST_START 0x00200000 146 #define CONFIG_SYS_MEMTEST_END 0x00400000 147 #define CONFIG_PANIC_HANG 148 149 /* DDR Setup */ 150 #define CONFIG_SYS_FSL_DDR3 151 #define CONFIG_DDR_SPD 152 #define CONFIG_SYS_SPD_BUS_NUM 0 153 #define SPD_EEPROM_ADDRESS 0x50 154 #define CONFIG_SYS_DDR_RAW_TIMING 155 156 /* DDR ECC Setup*/ 157 #define CONFIG_DDR_ECC 158 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 159 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 160 161 #define CONFIG_SYS_SDRAM_SIZE 512 162 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 163 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 164 165 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 166 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 167 168 #define CONFIG_SYS_CCSRBAR 0xffe00000 169 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 170 171 /* Platform SRAM setting */ 172 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 173 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 174 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 175 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 176 177 #ifdef CONFIG_SPL_BUILD 178 #define CONFIG_SYS_NO_FLASH 179 #endif 180 181 /* 182 * IFC Definitions 183 */ 184 /* NOR Flash on IFC */ 185 #define CONFIG_SYS_FLASH_BASE 0xec000000 186 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 187 188 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 189 190 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 191 #define CONFIG_SYS_MAX_FLASH_BANKS 1 192 193 #define CONFIG_SYS_FLASH_QUIET_TEST 194 #define CONFIG_FLASH_SHOW_PROGRESS 45 195 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 196 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 197 198 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 199 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 200 CSPR_PORT_SIZE_16 | \ 201 CSPR_MSEL_NOR | \ 202 CSPR_V) 203 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 204 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 205 206 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 207 FTIM0_NOR_TEADC(0x5) | \ 208 FTIM0_NOR_TEAHC(0x5)) 209 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 210 FTIM1_NOR_TRAD_NOR(0x1A) |\ 211 FTIM1_NOR_TSEQRAD_NOR(0x13)) 212 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 213 FTIM2_NOR_TCH(0x4) | \ 214 FTIM2_NOR_TWPH(0x0E) | \ 215 FTIM2_NOR_TWP(0x1c)) 216 #define CONFIG_SYS_NOR_FTIM3 0x0 217 218 /* CFI for NOR Flash */ 219 #define CONFIG_FLASH_CFI_DRIVER 220 #define CONFIG_SYS_FLASH_CFI 221 #define CONFIG_SYS_FLASH_EMPTY_INFO 222 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 223 224 /* NAND Flash on IFC */ 225 #define CONFIG_NAND_FSL_IFC 226 #define CONFIG_SYS_NAND_BASE 0xff800000 227 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 228 229 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 230 231 #define CONFIG_SYS_MAX_NAND_DEVICE 1 232 #define CONFIG_CMD_NAND 233 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 234 235 /* 8Bit NAND Flash - K9F1G08U0B */ 236 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 237 | CSPR_PORT_SIZE_8 \ 238 | CSPR_MSEL_NAND \ 239 | CSPR_V) 240 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 241 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 242 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 243 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 244 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 245 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 246 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 247 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 248 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 249 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 250 FTIM0_NAND_TWP(0x0c) | \ 251 FTIM0_NAND_TWCHT(0x08) | \ 252 FTIM0_NAND_TWH(0x06)) 253 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 254 FTIM1_NAND_TWBE(0x1d) | \ 255 FTIM1_NAND_TRR(0x08) | \ 256 FTIM1_NAND_TRP(0x0c)) 257 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 258 FTIM2_NAND_TREH(0x0a) | \ 259 FTIM2_NAND_TWHRE(0x18)) 260 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 261 262 #define CONFIG_SYS_NAND_DDR_LAW 11 263 264 /* Set up IFC registers for boot location NOR/NAND */ 265 #ifdef CONFIG_NAND 266 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 267 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 268 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 269 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 270 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 271 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 272 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 273 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 274 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 275 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 276 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 277 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 278 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 279 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 280 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 281 #else 282 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 283 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 284 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 285 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 286 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 287 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 288 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 289 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 290 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 291 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 292 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 293 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 294 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 295 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 296 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 297 #endif 298 299 /* CPLD on IFC, selected by CS2 */ 300 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 301 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 302 | CONFIG_SYS_CPLD_BASE) 303 304 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 305 | CSPR_PORT_SIZE_8 \ 306 | CSPR_MSEL_GPCM \ 307 | CSPR_V) 308 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 309 #define CONFIG_SYS_CSOR2 0x0 310 /* CPLD Timing parameters for IFC CS2 */ 311 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 312 FTIM0_GPCM_TEADC(0x0e) | \ 313 FTIM0_GPCM_TEAHC(0x0e)) 314 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 315 FTIM1_GPCM_TRAD(0x1f)) 316 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 317 FTIM2_GPCM_TCH(0x8) | \ 318 FTIM2_GPCM_TWP(0x1f)) 319 #define CONFIG_SYS_CS2_FTIM3 0x0 320 321 #if defined(CONFIG_RAMBOOT_SPIFLASH) 322 #define CONFIG_SYS_RAMBOOT 323 #define CONFIG_SYS_EXTRA_ENV_RELOC 324 #endif 325 326 #define CONFIG_BOARD_EARLY_INIT_R 327 328 #define CONFIG_SYS_INIT_RAM_LOCK 329 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 330 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 331 332 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 333 - GENERATED_GBL_DATA_SIZE) 334 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 335 336 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 337 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 338 339 /* 340 * Config the L2 Cache as L2 SRAM 341 */ 342 #if defined(CONFIG_SPL_BUILD) 343 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 344 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 345 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 346 #define CONFIG_SYS_L2_SIZE (256 << 10) 347 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 348 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 349 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 350 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 351 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 352 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 353 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 354 #elif defined(CONFIG_NAND) 355 #ifdef CONFIG_TPL_BUILD 356 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 357 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 358 #define CONFIG_SYS_L2_SIZE (256 << 10) 359 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 360 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 361 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 362 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 363 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 364 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 365 #else 366 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 367 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 368 #define CONFIG_SYS_L2_SIZE (256 << 10) 369 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 370 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 371 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 372 #endif 373 #endif 374 #endif 375 376 /* Serial Port */ 377 #define CONFIG_CONS_INDEX 1 378 #define CONFIG_SYS_NS16550_SERIAL 379 #define CONFIG_SYS_NS16550_REG_SIZE 1 380 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 381 382 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 383 #define CONFIG_NS16550_MIN_FUNCTIONS 384 #endif 385 386 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 387 388 #define CONFIG_SYS_BAUDRATE_TABLE \ 389 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 390 391 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 392 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 393 394 #define CONFIG_SYS_I2C 395 #define CONFIG_SYS_I2C_FSL 396 #define CONFIG_SYS_FSL_I2C_SPEED 400000 397 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 398 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 399 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 400 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 401 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 402 403 /* I2C EEPROM */ 404 /* enable read and write access to EEPROM */ 405 #define CONFIG_CMD_EEPROM 406 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 407 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 408 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 409 410 /* eSPI - Enhanced SPI */ 411 #define CONFIG_SF_DEFAULT_SPEED 10000000 412 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 413 414 #ifdef CONFIG_TSEC_ENET 415 #define CONFIG_MII /* MII PHY management */ 416 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 417 #define CONFIG_TSEC1 1 418 #define CONFIG_TSEC1_NAME "eTSEC1" 419 #define CONFIG_TSEC2 1 420 #define CONFIG_TSEC2_NAME "eTSEC2" 421 422 /* Default mode is RGMII mode */ 423 #define TSEC1_PHY_ADDR 0 424 #define TSEC2_PHY_ADDR 2 425 426 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 427 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 428 429 #define CONFIG_ETHPRIME "eTSEC1" 430 431 #define CONFIG_PHY_GIGE 432 #endif /* CONFIG_TSEC_ENET */ 433 434 /* 435 * Environment 436 */ 437 #if defined(CONFIG_SYS_RAMBOOT) 438 #if defined(CONFIG_RAMBOOT_SPIFLASH) 439 #define CONFIG_ENV_IS_IN_SPI_FLASH 440 #define CONFIG_ENV_SPI_BUS 0 441 #define CONFIG_ENV_SPI_CS 0 442 #define CONFIG_ENV_SPI_MAX_HZ 10000000 443 #define CONFIG_ENV_SPI_MODE 0 444 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 445 #define CONFIG_ENV_SECT_SIZE 0x10000 446 #define CONFIG_ENV_SIZE 0x2000 447 #endif 448 #elif defined(CONFIG_NAND) 449 #define CONFIG_ENV_IS_IN_NAND 450 #ifdef CONFIG_TPL_BUILD 451 #define CONFIG_ENV_SIZE 0x2000 452 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 453 #else 454 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 455 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 456 #endif 457 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE 458 #else 459 #define CONFIG_ENV_IS_IN_FLASH 460 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 461 #define CONFIG_ENV_SIZE 0x2000 462 #define CONFIG_ENV_SECT_SIZE 0x20000 463 #endif 464 465 #define CONFIG_LOADS_ECHO 466 #define CONFIG_SYS_LOADS_BAUD_CHANGE 467 468 /* 469 * Command line configuration. 470 */ 471 #define CONFIG_CMD_ERRATA 472 #define CONFIG_CMD_IRQ 473 #define CONFIG_CMD_REGINFO 474 475 /* Hash command with SHA acceleration supported in hardware */ 476 #ifdef CONFIG_FSL_CAAM 477 #define CONFIG_CMD_HASH 478 #define CONFIG_SHA_HW_ACCEL 479 #endif 480 481 /* 482 * Miscellaneous configurable options 483 */ 484 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 485 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 486 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 487 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 488 489 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 490 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 491 /* Print Buffer Size */ 492 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 493 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 494 495 /* 496 * For booting Linux, the board info and command line data 497 * have to be in the first 64 MB of memory, since this is 498 * the maximum mapped by the Linux kernel during initialization. 499 */ 500 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 501 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 502 503 /* 504 * Environment Configuration 505 */ 506 507 #ifdef CONFIG_TSEC_ENET 508 #define CONFIG_HAS_ETH0 509 #define CONFIG_HAS_ETH1 510 #endif 511 512 #define CONFIG_ROOTPATH "/opt/nfsroot" 513 #define CONFIG_BOOTFILE "uImage" 514 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 515 516 /* default location for tftp and bootm */ 517 #define CONFIG_LOADADDR 1000000 518 519 520 #define CONFIG_BAUDRATE 115200 521 522 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 523 524 #define CONFIG_EXTRA_ENV_SETTINGS \ 525 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 526 "netdev=eth0\0" \ 527 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 528 "loadaddr=1000000\0" \ 529 "consoledev=ttyS0\0" \ 530 "ramdiskaddr=2000000\0" \ 531 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 532 "fdtaddr=1e00000\0" \ 533 "fdtfile=name/of/device-tree.dtb\0" \ 534 "othbootargs=ramdisk_size=600000\0" \ 535 536 #define CONFIG_RAMBOOTCOMMAND \ 537 "setenv bootargs root=/dev/ram rw " \ 538 "console=$consoledev,$baudrate $othbootargs; " \ 539 "tftp $ramdiskaddr $ramdiskfile;" \ 540 "tftp $loadaddr $bootfile;" \ 541 "tftp $fdtaddr $fdtfile;" \ 542 "bootm $loadaddr $ramdiskaddr $fdtaddr" 543 544 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 545 546 #include <asm/fsl_secure_boot.h> 547 548 #endif /* __CONFIG_H */ 549