1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_PHYS_64BIT 15 #define CONFIG_SYS_GENERIC_BOARD 16 #define CONFIG_DISPLAY_BOARDINFO 17 18 #ifdef CONFIG_C29XPCIE 19 #define CONFIG_PPC_C29X 20 #endif 21 22 #ifdef CONFIG_SPIFLASH 23 #define CONFIG_RAMBOOT_SPIFLASH 24 #define CONFIG_SYS_TEXT_BASE 0x11000000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 26 #endif 27 28 #ifdef CONFIG_NAND 29 #ifdef CONFIG_TPL_BUILD 30 #define CONFIG_SPL_NAND_BOOT 31 #define CONFIG_SPL_FLUSH_IMAGE 32 #define CONFIG_SPL_ENV_SUPPORT 33 #define CONFIG_SPL_NAND_INIT 34 #define CONFIG_SPL_SERIAL_SUPPORT 35 #define CONFIG_SPL_LIBGENERIC_SUPPORT 36 #define CONFIG_SPL_LIBCOMMON_SUPPORT 37 #define CONFIG_SPL_I2C_SUPPORT 38 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 39 #define CONFIG_SPL_NAND_SUPPORT 40 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 41 #define CONFIG_SPL_COMMON_INIT_DDR 42 #define CONFIG_SPL_MAX_SIZE (128 << 10) 43 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 44 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 45 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 46 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 47 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 48 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 49 #elif defined(CONFIG_SPL_BUILD) 50 #define CONFIG_SPL_INIT_MINIMAL 51 #define CONFIG_SPL_SERIAL_SUPPORT 52 #define CONFIG_SPL_NAND_SUPPORT 53 #define CONFIG_SPL_NAND_MINIMAL 54 #define CONFIG_SPL_FLUSH_IMAGE 55 #define CONFIG_SPL_TEXT_BASE 0xff800000 56 #define CONFIG_SPL_MAX_SIZE 8192 57 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 58 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 59 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 60 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 61 #endif 62 #define CONFIG_SPL_PAD_TO 0x20000 63 #define CONFIG_TPL_PAD_TO 0x20000 64 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 65 #define CONFIG_SYS_TEXT_BASE 0x11001000 66 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 67 #endif 68 69 #ifndef CONFIG_SYS_TEXT_BASE 70 #define CONFIG_SYS_TEXT_BASE 0xeff40000 71 #endif 72 73 #ifndef CONFIG_RESET_VECTOR_ADDRESS 74 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 75 #endif 76 77 #ifdef CONFIG_SPL_BUILD 78 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 79 #else 80 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 81 #endif 82 83 #ifdef CONFIG_SPL_BUILD 84 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 85 #endif 86 87 /* High Level Configuration Options */ 88 #define CONFIG_BOOKE /* BOOKE */ 89 #define CONFIG_E500 /* BOOKE e500 family */ 90 #define CONFIG_FSL_IFC /* Enable IFC Support */ 91 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 92 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 93 94 #define CONFIG_PCI /* Enable PCI/PCIE */ 95 #ifdef CONFIG_PCI 96 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 97 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 98 #define CONFIG_PCI_INDIRECT_BRIDGE 99 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 100 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 101 102 #define CONFIG_CMD_PCI 103 104 105 /* 106 * PCI Windows 107 * Memory space is mapped 1-1, but I/O space must start from 0. 108 */ 109 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 110 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 111 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 112 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 113 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 114 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 115 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 116 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 117 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 118 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 119 120 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 121 122 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 123 #define CONFIG_DOS_PARTITION 124 #endif 125 126 #define CONFIG_FSL_LAW /* Use common FSL init code */ 127 #define CONFIG_TSEC_ENET 128 #define CONFIG_ENV_OVERWRITE 129 130 #define CONFIG_DDR_CLK_FREQ 100000000 131 #define CONFIG_SYS_CLK_FREQ 66666666 132 133 #define CONFIG_HWCONFIG 134 135 /* 136 * These can be toggled for performance analysis, otherwise use default. 137 */ 138 #define CONFIG_L2_CACHE /* toggle L2 cache */ 139 #define CONFIG_BTB /* toggle branch predition */ 140 141 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 142 143 #define CONFIG_ENABLE_36BIT_PHYS 144 145 #define CONFIG_ADDR_MAP 1 146 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 147 148 #define CONFIG_SYS_MEMTEST_START 0x00200000 149 #define CONFIG_SYS_MEMTEST_END 0x00400000 150 #define CONFIG_PANIC_HANG 151 152 /* DDR Setup */ 153 #define CONFIG_SYS_FSL_DDR3 154 #define CONFIG_DDR_SPD 155 #define CONFIG_SYS_SPD_BUS_NUM 0 156 #define SPD_EEPROM_ADDRESS 0x50 157 #define CONFIG_SYS_DDR_RAW_TIMING 158 159 /* DDR ECC Setup*/ 160 #define CONFIG_DDR_ECC 161 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 162 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 163 164 #define CONFIG_SYS_SDRAM_SIZE 512 165 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 166 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 167 168 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 169 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 170 171 #define CONFIG_SYS_CCSRBAR 0xffe00000 172 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 173 174 /* Platform SRAM setting */ 175 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 176 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 177 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 178 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 179 180 #ifdef CONFIG_SPL_BUILD 181 #define CONFIG_SYS_NO_FLASH 182 #endif 183 184 /* 185 * IFC Definitions 186 */ 187 /* NOR Flash on IFC */ 188 #define CONFIG_SYS_FLASH_BASE 0xec000000 189 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 190 191 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 192 193 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 194 #define CONFIG_SYS_MAX_FLASH_BANKS 1 195 196 #define CONFIG_SYS_FLASH_QUIET_TEST 197 #define CONFIG_FLASH_SHOW_PROGRESS 45 198 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 199 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 200 201 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 202 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 203 CSPR_PORT_SIZE_16 | \ 204 CSPR_MSEL_NOR | \ 205 CSPR_V) 206 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 207 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 208 209 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 210 FTIM0_NOR_TEADC(0x5) | \ 211 FTIM0_NOR_TEAHC(0x5)) 212 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 213 FTIM1_NOR_TRAD_NOR(0x1A) |\ 214 FTIM1_NOR_TSEQRAD_NOR(0x13)) 215 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 216 FTIM2_NOR_TCH(0x4) | \ 217 FTIM2_NOR_TWPH(0x0E) | \ 218 FTIM2_NOR_TWP(0x1c)) 219 #define CONFIG_SYS_NOR_FTIM3 0x0 220 221 /* CFI for NOR Flash */ 222 #define CONFIG_FLASH_CFI_DRIVER 223 #define CONFIG_SYS_FLASH_CFI 224 #define CONFIG_SYS_FLASH_EMPTY_INFO 225 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 226 227 /* NAND Flash on IFC */ 228 #define CONFIG_NAND_FSL_IFC 229 #define CONFIG_SYS_NAND_BASE 0xff800000 230 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 231 232 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 233 234 #define CONFIG_SYS_MAX_NAND_DEVICE 1 235 #define CONFIG_CMD_NAND 236 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 237 238 /* 8Bit NAND Flash - K9F1G08U0B */ 239 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 240 | CSPR_PORT_SIZE_8 \ 241 | CSPR_MSEL_NAND \ 242 | CSPR_V) 243 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 244 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 245 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 246 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 247 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 248 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 249 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 250 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 251 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 252 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 253 FTIM0_NAND_TWP(0x0c) | \ 254 FTIM0_NAND_TWCHT(0x08) | \ 255 FTIM0_NAND_TWH(0x06)) 256 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 257 FTIM1_NAND_TWBE(0x1d) | \ 258 FTIM1_NAND_TRR(0x08) | \ 259 FTIM1_NAND_TRP(0x0c)) 260 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 261 FTIM2_NAND_TREH(0x0a) | \ 262 FTIM2_NAND_TWHRE(0x18)) 263 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 264 265 #define CONFIG_SYS_NAND_DDR_LAW 11 266 267 /* Set up IFC registers for boot location NOR/NAND */ 268 #ifdef CONFIG_NAND 269 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 270 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 271 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 272 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 273 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 274 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 275 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 276 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 277 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 278 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 279 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 280 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 281 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 282 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 283 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 284 #else 285 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 286 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 287 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 288 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 289 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 290 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 291 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 292 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 293 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 294 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 295 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 296 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 297 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 298 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 299 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 300 #endif 301 302 /* CPLD on IFC, selected by CS2 */ 303 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 304 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 305 | CONFIG_SYS_CPLD_BASE) 306 307 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 308 | CSPR_PORT_SIZE_8 \ 309 | CSPR_MSEL_GPCM \ 310 | CSPR_V) 311 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 312 #define CONFIG_SYS_CSOR2 0x0 313 /* CPLD Timing parameters for IFC CS2 */ 314 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 315 FTIM0_GPCM_TEADC(0x0e) | \ 316 FTIM0_GPCM_TEAHC(0x0e)) 317 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 318 FTIM1_GPCM_TRAD(0x1f)) 319 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 320 FTIM2_GPCM_TCH(0x8) | \ 321 FTIM2_GPCM_TWP(0x1f)) 322 #define CONFIG_SYS_CS2_FTIM3 0x0 323 324 #if defined(CONFIG_RAMBOOT_SPIFLASH) 325 #define CONFIG_SYS_RAMBOOT 326 #define CONFIG_SYS_EXTRA_ENV_RELOC 327 #endif 328 329 #define CONFIG_BOARD_EARLY_INIT_R 330 331 #define CONFIG_SYS_INIT_RAM_LOCK 332 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 333 #define CONFIG_SYS_INIT_RAM_END 0x00004000 334 335 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 336 - GENERATED_GBL_DATA_SIZE) 337 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 338 339 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 340 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 341 342 /* 343 * Config the L2 Cache as L2 SRAM 344 */ 345 #if defined(CONFIG_SPL_BUILD) 346 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 347 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 348 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 349 #define CONFIG_SYS_L2_SIZE (256 << 10) 350 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 351 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 352 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 353 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 354 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 355 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 356 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 357 #elif defined(CONFIG_NAND) 358 #ifdef CONFIG_TPL_BUILD 359 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 360 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 361 #define CONFIG_SYS_L2_SIZE (256 << 10) 362 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 363 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 364 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 365 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 366 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 367 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 368 #else 369 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 370 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 371 #define CONFIG_SYS_L2_SIZE (256 << 10) 372 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 373 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 374 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 375 #endif 376 #endif 377 #endif 378 379 /* Serial Port */ 380 #define CONFIG_CONS_INDEX 1 381 #define CONFIG_SYS_NS16550 382 #define CONFIG_SYS_NS16550_SERIAL 383 #define CONFIG_SYS_NS16550_REG_SIZE 1 384 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 385 386 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 387 #define CONFIG_NS16550_MIN_FUNCTIONS 388 #endif 389 390 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 391 392 #define CONFIG_SYS_BAUDRATE_TABLE \ 393 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 394 395 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 396 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 397 398 /* Use the HUSH parser */ 399 #define CONFIG_SYS_HUSH_PARSER 400 401 /* 402 * Pass open firmware flat tree 403 */ 404 #define CONFIG_OF_LIBFDT 405 #define CONFIG_OF_BOARD_SETUP 406 #define CONFIG_OF_STDOUT_VIA_ALIAS 407 408 /* new uImage format support */ 409 #define CONFIG_FIT 410 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 411 412 #define CONFIG_SYS_I2C 413 #define CONFIG_SYS_I2C_FSL 414 #define CONFIG_SYS_FSL_I2C_SPEED 400000 415 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 416 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 417 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 418 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 419 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 420 421 /* I2C EEPROM */ 422 /* enable read and write access to EEPROM */ 423 #define CONFIG_CMD_EEPROM 424 #define CONFIG_SYS_I2C_MULTI_EEPROMS 425 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 426 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 427 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 428 429 #define CONFIG_CMD_I2C 430 431 /* eSPI - Enhanced SPI */ 432 #define CONFIG_FSL_ESPI 433 #define CONFIG_SPI_FLASH_SPANSION 434 #define CONFIG_SPI_FLASH_EON 435 #define CONFIG_CMD_SF 436 #define CONFIG_SF_DEFAULT_SPEED 10000000 437 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 438 439 #ifdef CONFIG_TSEC_ENET 440 #define CONFIG_MII /* MII PHY management */ 441 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 442 #define CONFIG_TSEC1 1 443 #define CONFIG_TSEC1_NAME "eTSEC1" 444 #define CONFIG_TSEC2 1 445 #define CONFIG_TSEC2_NAME "eTSEC2" 446 447 /* Default mode is RGMII mode */ 448 #define TSEC1_PHY_ADDR 0 449 #define TSEC2_PHY_ADDR 2 450 451 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 452 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 453 454 #define CONFIG_ETHPRIME "eTSEC1" 455 456 #define CONFIG_PHY_GIGE 457 #endif /* CONFIG_TSEC_ENET */ 458 459 /* 460 * Environment 461 */ 462 #if defined(CONFIG_SYS_RAMBOOT) 463 #if defined(CONFIG_RAMBOOT_SPIFLASH) 464 #define CONFIG_ENV_IS_IN_SPI_FLASH 465 #define CONFIG_ENV_SPI_BUS 0 466 #define CONFIG_ENV_SPI_CS 0 467 #define CONFIG_ENV_SPI_MAX_HZ 10000000 468 #define CONFIG_ENV_SPI_MODE 0 469 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 470 #define CONFIG_ENV_SECT_SIZE 0x10000 471 #define CONFIG_ENV_SIZE 0x2000 472 #endif 473 #elif defined(CONFIG_NAND) 474 #define CONFIG_ENV_IS_IN_NAND 475 #ifdef CONFIG_TPL_BUILD 476 #define CONFIG_ENV_SIZE 0x2000 477 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 478 #else 479 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 480 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 481 #endif 482 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE 483 #else 484 #define CONFIG_ENV_IS_IN_FLASH 485 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 486 #define CONFIG_ENV_SIZE 0x2000 487 #define CONFIG_ENV_SECT_SIZE 0x20000 488 #endif 489 490 #define CONFIG_LOADS_ECHO 491 #define CONFIG_SYS_LOADS_BAUD_CHANGE 492 493 /* 494 * Command line configuration. 495 */ 496 #define CONFIG_CMD_ERRATA 497 #define CONFIG_CMD_IRQ 498 #define CONFIG_CMD_MII 499 #define CONFIG_CMD_PING 500 #define CONFIG_CMD_REGINFO 501 502 /* Hash command with SHA acceleration supported in hardware */ 503 #ifdef CONFIG_FSL_CAAM 504 #define CONFIG_CMD_HASH 505 #define CONFIG_SHA_HW_ACCEL 506 #endif 507 508 /* 509 * Miscellaneous configurable options 510 */ 511 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 512 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 513 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 514 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 515 516 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 517 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 518 /* Print Buffer Size */ 519 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 520 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 521 522 /* 523 * For booting Linux, the board info and command line data 524 * have to be in the first 64 MB of memory, since this is 525 * the maximum mapped by the Linux kernel during initialization. 526 */ 527 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 528 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 529 530 /* 531 * Environment Configuration 532 */ 533 534 #ifdef CONFIG_TSEC_ENET 535 #define CONFIG_HAS_ETH0 536 #define CONFIG_HAS_ETH1 537 #endif 538 539 #define CONFIG_ROOTPATH "/opt/nfsroot" 540 #define CONFIG_BOOTFILE "uImage" 541 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 542 543 /* default location for tftp and bootm */ 544 #define CONFIG_LOADADDR 1000000 545 546 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 547 548 #define CONFIG_BAUDRATE 115200 549 550 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 551 552 #define CONFIG_EXTRA_ENV_SETTINGS \ 553 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 554 "netdev=eth0\0" \ 555 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 556 "loadaddr=1000000\0" \ 557 "consoledev=ttyS0\0" \ 558 "ramdiskaddr=2000000\0" \ 559 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 560 "fdtaddr=c00000\0" \ 561 "fdtfile=name/of/device-tree.dtb\0" \ 562 "othbootargs=ramdisk_size=600000\0" \ 563 564 #define CONFIG_RAMBOOTCOMMAND \ 565 "setenv bootargs root=/dev/ram rw " \ 566 "console=$consoledev,$baudrate $othbootargs; " \ 567 "tftp $ramdiskaddr $ramdiskfile;" \ 568 "tftp $loadaddr $bootfile;" \ 569 "tftp $fdtaddr $fdtfile;" \ 570 "bootm $loadaddr $ramdiskaddr $fdtaddr" 571 572 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 573 574 #include <asm/fsl_secure_boot.h> 575 576 #endif /* __CONFIG_H */ 577