1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_PHYS_64BIT 15 16 #ifdef CONFIG_C29XPCIE 17 #define CONFIG_PPC_C29X 18 #endif 19 20 #ifdef CONFIG_SPIFLASH 21 #define CONFIG_RAMBOOT_SPIFLASH 22 #define CONFIG_SYS_TEXT_BASE 0x11000000 23 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 24 #endif 25 26 #ifndef CONFIG_SYS_TEXT_BASE 27 #define CONFIG_SYS_TEXT_BASE 0xeff80000 28 #endif 29 30 #ifndef CONFIG_RESET_VECTOR_ADDRESS 31 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 32 #endif 33 34 #ifndef CONFIG_SYS_MONITOR_BASE 35 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 36 #endif 37 38 /* High Level Configuration Options */ 39 #define CONFIG_BOOKE /* BOOKE */ 40 #define CONFIG_E500 /* BOOKE e500 family */ 41 #define CONFIG_MPC85xx 42 #define CONFIG_FSL_IFC /* Enable IFC Support */ 43 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 44 45 #define CONFIG_PCI /* Enable PCI/PCIE */ 46 #ifdef CONFIG_PCI 47 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 48 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 49 #define CONFIG_PCI_INDIRECT_BRIDGE 50 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 51 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 52 53 #define CONFIG_CMD_NET 54 #define CONFIG_CMD_PCI 55 56 #define CONFIG_E1000 57 58 /* 59 * PCI Windows 60 * Memory space is mapped 1-1, but I/O space must start from 0. 61 */ 62 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 63 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 64 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 65 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 66 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 67 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 68 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 69 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 70 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 71 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 72 73 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 74 75 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 76 #define CONFIG_DOS_PARTITION 77 #endif 78 79 #define CONFIG_FSL_LAW /* Use common FSL init code */ 80 #define CONFIG_TSEC_ENET 81 #define CONFIG_ENV_OVERWRITE 82 83 #define CONFIG_DDR_CLK_FREQ 100000000 84 #define CONFIG_SYS_CLK_FREQ 66666666 85 86 #define CONFIG_HWCONFIG 87 88 /* 89 * These can be toggled for performance analysis, otherwise use default. 90 */ 91 #define CONFIG_L2_CACHE /* toggle L2 cache */ 92 #define CONFIG_BTB /* toggle branch predition */ 93 94 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 95 96 #define CONFIG_ENABLE_36BIT_PHYS 97 98 #define CONFIG_ADDR_MAP 1 99 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 100 101 #define CONFIG_SYS_MEMTEST_START 0x00200000 102 #define CONFIG_SYS_MEMTEST_END 0x00400000 103 #define CONFIG_PANIC_HANG 104 105 /* DDR Setup */ 106 #define CONFIG_FSL_DDR3 107 #define CONFIG_DDR_SPD 108 #define CONFIG_SYS_SPD_BUS_NUM 0 109 #define SPD_EEPROM_ADDRESS 0x50 110 #define CONFIG_SYS_DDR_RAW_TIMING 111 112 /* DDR ECC Setup*/ 113 #define CONFIG_DDR_ECC 114 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 115 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 116 117 #define CONFIG_SYS_SDRAM_SIZE 512 118 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 120 121 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 122 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 123 124 #define CONFIG_SYS_CCSRBAR 0xffe00000 125 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 126 127 /* Platform SRAM setting */ 128 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 129 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 130 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 131 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 132 133 /* 134 * IFC Definitions 135 */ 136 /* NOR Flash on IFC */ 137 #define CONFIG_SYS_FLASH_BASE 0xec000000 138 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 139 140 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 141 142 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 143 #define CONFIG_SYS_MAX_FLASH_BANKS 1 144 145 #define CONFIG_SYS_FLASH_QUIET_TEST 146 #define CONFIG_FLASH_SHOW_PROGRESS 45 147 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 148 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 149 150 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 151 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 152 CSPR_PORT_SIZE_16 | \ 153 CSPR_MSEL_NOR | \ 154 CSPR_V) 155 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 156 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 157 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 158 FTIM0_NOR_TEADC(0x5) | \ 159 FTIM0_NOR_TEAHC(0x5)) 160 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1e) | \ 161 FTIM1_NOR_TRAD_NOR(0x0f) | \ 162 FTIM1_NOR_TSEQRAD_NOR(0x0f)) 163 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 164 FTIM2_NOR_TCH(0x4) | \ 165 FTIM2_NOR_TWP(0x1c)) 166 #define CONFIG_SYS_NOR_FTIM3 0x0 167 168 /* CFI for NOR Flash */ 169 #define CONFIG_FLASH_CFI_DRIVER 170 #define CONFIG_SYS_FLASH_CFI 171 #define CONFIG_SYS_FLASH_EMPTY_INFO 172 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 173 174 /* NAND Flash on IFC */ 175 #define CONFIG_NAND_FSL_IFC 176 #define CONFIG_SYS_NAND_BASE 0xff800000 177 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 178 179 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 180 181 #define CONFIG_SYS_MAX_NAND_DEVICE 1 182 #define CONFIG_MTD_NAND_VERIFY_WRITE 183 #define CONFIG_CMD_NAND 184 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 185 186 /* 8Bit NAND Flash - K9F1G08U0B */ 187 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 188 | CSPR_PORT_SIZE_8 \ 189 | CSPR_MSEL_NAND \ 190 | CSPR_V) 191 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 192 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 193 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 194 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 195 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 196 | CSOR_NAND_PGS_2K /* Page Size = 2k */ \ 197 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 198 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 199 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 200 FTIM0_NAND_TWP(0x0c) | \ 201 FTIM0_NAND_TWCHT(0x08) | \ 202 FTIM0_NAND_TWH(0x06)) 203 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 204 FTIM1_NAND_TWBE(0x1d) | \ 205 FTIM1_NAND_TRR(0x08) | \ 206 FTIM1_NAND_TRP(0x0c)) 207 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 208 FTIM2_NAND_TREH(0x0a) | \ 209 FTIM2_NAND_TWHRE(0x18)) 210 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 211 212 #define CONFIG_SYS_NAND_DDR_LAW 11 213 214 /* Set up IFC registers for boot location NOR/NAND */ 215 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 216 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 217 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 218 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 219 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 220 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 221 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 222 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 223 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 224 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 225 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 226 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 227 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 228 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 229 230 /* CPLD on IFC, selected by CS2 */ 231 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 232 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 233 | CONFIG_SYS_CPLD_BASE) 234 235 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 236 | CSPR_PORT_SIZE_8 \ 237 | CSPR_MSEL_GPCM \ 238 | CSPR_V) 239 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 240 #define CONFIG_SYS_CSOR2 0x0 241 /* CPLD Timing parameters for IFC CS2 */ 242 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 243 FTIM0_GPCM_TEADC(0x0e) | \ 244 FTIM0_GPCM_TEAHC(0x0e)) 245 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 246 FTIM1_GPCM_TRAD(0x1f)) 247 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 248 FTIM2_GPCM_TCH(0x0) | \ 249 FTIM2_GPCM_TWP(0x1f)) 250 #define CONFIG_SYS_CS2_FTIM3 0x0 251 252 #if defined(CONFIG_RAMBOOT_SPIFLASH) 253 #define CONFIG_SYS_RAMBOOT 254 #define CONFIG_SYS_EXTRA_ENV_RELOC 255 #endif 256 257 #define CONFIG_BOARD_EARLY_INIT_R 258 259 #define CONFIG_SYS_INIT_RAM_LOCK 260 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 261 #define CONFIG_SYS_INIT_RAM_END 0x00004000 262 263 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 264 - GENERATED_GBL_DATA_SIZE) 265 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 266 267 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 268 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 269 270 /* Serial Port */ 271 #define CONFIG_CONS_INDEX 1 272 #define CONFIG_SYS_NS16550 273 #define CONFIG_SYS_NS16550_SERIAL 274 #define CONFIG_SYS_NS16550_REG_SIZE 1 275 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 276 277 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 278 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 279 280 #define CONFIG_SYS_BAUDRATE_TABLE \ 281 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 282 283 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 284 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 285 286 /* Use the HUSH parser */ 287 #define CONFIG_SYS_HUSH_PARSER 288 289 /* 290 * Pass open firmware flat tree 291 */ 292 #define CONFIG_OF_LIBFDT 293 #define CONFIG_OF_BOARD_SETUP 294 #define CONFIG_OF_STDOUT_VIA_ALIAS 295 296 /* new uImage format support */ 297 #define CONFIG_FIT 298 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 299 300 #define CONFIG_SYS_I2C 301 #define CONFIG_SYS_I2C_FSL 302 #define CONFIG_SYS_FSL_I2C_SPEED 400000 303 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 304 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 305 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 306 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 307 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 308 309 /* I2C EEPROM */ 310 /* enable read and write access to EEPROM */ 311 #define CONFIG_CMD_EEPROM 312 #define CONFIG_SYS_I2C_MULTI_EEPROMS 313 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 314 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 315 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 316 317 #define CONFIG_CMD_I2C 318 319 /* eSPI - Enhanced SPI */ 320 #define CONFIG_FSL_ESPI 321 #define CONFIG_SPI_FLASH 322 #define CONFIG_SPI_FLASH_SPANSION 323 #define CONFIG_SPI_FLASH_EON 324 #define CONFIG_CMD_SF 325 #define CONFIG_SF_DEFAULT_SPEED 10000000 326 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 327 328 #ifdef CONFIG_TSEC_ENET 329 #define CONFIG_NET_MULTI 330 #define CONFIG_MII /* MII PHY management */ 331 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 332 #define CONFIG_TSEC1 1 333 #define CONFIG_TSEC1_NAME "eTSEC1" 334 #define CONFIG_TSEC2 1 335 #define CONFIG_TSEC2_NAME "eTSEC2" 336 337 /* Default mode is RGMII mode */ 338 #define TSEC1_PHY_ADDR 0 339 #define TSEC2_PHY_ADDR 2 340 341 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 342 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 343 344 #define CONFIG_ETHPRIME "eTSEC1" 345 346 #define CONFIG_PHY_GIGE 347 #endif /* CONFIG_TSEC_ENET */ 348 349 /* 350 * Environment 351 */ 352 #if defined(CONFIG_SYS_RAMBOOT) 353 #if defined(CONFIG_RAMBOOT_SPIFLASH) 354 #define CONFIG_ENV_IS_IN_SPI_FLASH 355 #define CONFIG_ENV_SPI_BUS 0 356 #define CONFIG_ENV_SPI_CS 0 357 #define CONFIG_ENV_SPI_MAX_HZ 10000000 358 #define CONFIG_ENV_SPI_MODE 0 359 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 360 #define CONFIG_ENV_SECT_SIZE 0x10000 361 #define CONFIG_ENV_SIZE 0x2000 362 #endif 363 #else 364 #define CONFIG_ENV_IS_IN_FLASH 365 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 366 #define CONFIG_ENV_ADDR 0xfff80000 367 #else 368 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 369 #endif 370 #define CONFIG_ENV_SIZE 0x2000 371 #define CONFIG_ENV_SECT_SIZE 0x20000 372 #endif 373 374 #define CONFIG_LOADS_ECHO 375 #define CONFIG_SYS_LOADS_BAUD_CHANGE 376 377 /* 378 * Command line configuration. 379 */ 380 #include <config_cmd_default.h> 381 382 #define CONFIG_CMD_ERRATA 383 #define CONFIG_CMD_ELF 384 #define CONFIG_CMD_IRQ 385 #define CONFIG_CMD_MII 386 #define CONFIG_CMD_PING 387 #define CONFIG_CMD_SETEXPR 388 #define CONFIG_CMD_REGINFO 389 390 /* 391 * Miscellaneous configurable options 392 */ 393 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 394 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 395 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 396 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 397 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 398 399 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 400 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 401 /* Print Buffer Size */ 402 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 403 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 404 #define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */ 405 406 /* 407 * For booting Linux, the board info and command line data 408 * have to be in the first 64 MB of memory, since this is 409 * the maximum mapped by the Linux kernel during initialization. 410 */ 411 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 412 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 413 414 /* 415 * Environment Configuration 416 */ 417 418 #ifdef CONFIG_TSEC_ENET 419 #define CONFIG_HAS_ETH0 420 #define CONFIG_HAS_ETH1 421 #endif 422 423 #define CONFIG_ROOTPATH "/opt/nfsroot" 424 #define CONFIG_BOOTFILE "uImage" 425 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 426 427 /* default location for tftp and bootm */ 428 #define CONFIG_LOADADDR 1000000 429 430 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 431 432 #define CONFIG_BAUDRATE 115200 433 434 #define CONFIG_EXTRA_ENV_SETTINGS \ 435 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 436 "netdev=eth0\0" \ 437 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 438 "loadaddr=1000000\0" \ 439 "consoledev=ttyS0\0" \ 440 "ramdiskaddr=2000000\0" \ 441 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 442 "fdtaddr=c00000\0" \ 443 "fdtfile=name/of/device-tree.dtb\0" \ 444 "othbootargs=ramdisk_size=600000\0" \ 445 446 #define CONFIG_RAMBOOTCOMMAND \ 447 "setenv bootargs root=/dev/ram rw " \ 448 "console=$consoledev,$baudrate $othbootargs; " \ 449 "tftp $ramdiskaddr $ramdiskfile;" \ 450 "tftp $loadaddr $bootfile;" \ 451 "tftp $fdtaddr $fdtfile;" \ 452 "bootm $loadaddr $ramdiskaddr $fdtaddr" 453 454 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 455 456 #endif /* __CONFIG_H */ 457