1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_SPIFLASH 15 #define CONFIG_RAMBOOT_SPIFLASH 16 #define CONFIG_SYS_TEXT_BASE 0x11000000 17 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 18 #endif 19 20 #ifdef CONFIG_NAND 21 #ifdef CONFIG_TPL_BUILD 22 #define CONFIG_SPL_NAND_BOOT 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_NAND_INIT 25 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT 26 #define CONFIG_SPL_COMMON_INIT_DDR 27 #define CONFIG_SPL_MAX_SIZE (128 << 10) 28 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 30 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 31 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 32 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 33 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 34 #elif defined(CONFIG_SPL_BUILD) 35 #define CONFIG_SPL_INIT_MINIMAL 36 #define CONFIG_SPL_NAND_MINIMAL 37 #define CONFIG_SPL_FLUSH_IMAGE 38 #define CONFIG_SPL_TEXT_BASE 0xff800000 39 #define CONFIG_SPL_MAX_SIZE 8192 40 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 41 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 42 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 43 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 44 #endif 45 #define CONFIG_SPL_PAD_TO 0x20000 46 #define CONFIG_TPL_PAD_TO 0x20000 47 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 48 #define CONFIG_SYS_TEXT_BASE 0x11001000 49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 50 #endif 51 52 #ifndef CONFIG_SYS_TEXT_BASE 53 #define CONFIG_SYS_TEXT_BASE 0xeff40000 54 #endif 55 56 #ifndef CONFIG_RESET_VECTOR_ADDRESS 57 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 58 #endif 59 60 #ifdef CONFIG_SPL_BUILD 61 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 62 #else 63 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 64 #endif 65 66 #ifdef CONFIG_SPL_BUILD 67 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 68 #endif 69 70 /* High Level Configuration Options */ 71 #define CONFIG_BOOKE /* BOOKE */ 72 #define CONFIG_E500 /* BOOKE e500 family */ 73 #define CONFIG_FSL_IFC /* Enable IFC Support */ 74 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 75 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 76 77 #ifdef CONFIG_PCI 78 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 79 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 80 #define CONFIG_PCI_INDIRECT_BRIDGE 81 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 82 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 83 84 #define CONFIG_CMD_PCI 85 86 /* 87 * PCI Windows 88 * Memory space is mapped 1-1, but I/O space must start from 0. 89 */ 90 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 91 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 92 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 93 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 94 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 95 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 96 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 97 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 98 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 99 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 100 101 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 102 #define CONFIG_DOS_PARTITION 103 #endif 104 105 #define CONFIG_TSEC_ENET 106 #define CONFIG_ENV_OVERWRITE 107 108 #define CONFIG_DDR_CLK_FREQ 100000000 109 #define CONFIG_SYS_CLK_FREQ 66666666 110 111 #define CONFIG_HWCONFIG 112 113 /* 114 * These can be toggled for performance analysis, otherwise use default. 115 */ 116 #define CONFIG_L2_CACHE /* toggle L2 cache */ 117 #define CONFIG_BTB /* toggle branch predition */ 118 119 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 120 121 #define CONFIG_ENABLE_36BIT_PHYS 122 123 #define CONFIG_ADDR_MAP 1 124 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 125 126 #define CONFIG_SYS_MEMTEST_START 0x00200000 127 #define CONFIG_SYS_MEMTEST_END 0x00400000 128 #define CONFIG_PANIC_HANG 129 130 /* DDR Setup */ 131 #define CONFIG_SYS_FSL_DDR3 132 #define CONFIG_DDR_SPD 133 #define CONFIG_SYS_SPD_BUS_NUM 0 134 #define SPD_EEPROM_ADDRESS 0x50 135 #define CONFIG_SYS_DDR_RAW_TIMING 136 137 /* DDR ECC Setup*/ 138 #define CONFIG_DDR_ECC 139 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 140 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 141 142 #define CONFIG_SYS_SDRAM_SIZE 512 143 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 144 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 145 146 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 147 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 148 149 #define CONFIG_SYS_CCSRBAR 0xffe00000 150 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 151 152 /* Platform SRAM setting */ 153 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 154 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 155 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 156 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 157 158 #ifdef CONFIG_SPL_BUILD 159 #define CONFIG_SYS_NO_FLASH 160 #endif 161 162 /* 163 * IFC Definitions 164 */ 165 /* NOR Flash on IFC */ 166 #define CONFIG_SYS_FLASH_BASE 0xec000000 167 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 168 169 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 170 171 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 172 #define CONFIG_SYS_MAX_FLASH_BANKS 1 173 174 #define CONFIG_SYS_FLASH_QUIET_TEST 175 #define CONFIG_FLASH_SHOW_PROGRESS 45 176 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 177 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 178 179 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 180 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 181 CSPR_PORT_SIZE_16 | \ 182 CSPR_MSEL_NOR | \ 183 CSPR_V) 184 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 185 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 186 187 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 188 FTIM0_NOR_TEADC(0x5) | \ 189 FTIM0_NOR_TEAHC(0x5)) 190 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 191 FTIM1_NOR_TRAD_NOR(0x1A) |\ 192 FTIM1_NOR_TSEQRAD_NOR(0x13)) 193 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 194 FTIM2_NOR_TCH(0x4) | \ 195 FTIM2_NOR_TWPH(0x0E) | \ 196 FTIM2_NOR_TWP(0x1c)) 197 #define CONFIG_SYS_NOR_FTIM3 0x0 198 199 /* CFI for NOR Flash */ 200 #define CONFIG_FLASH_CFI_DRIVER 201 #define CONFIG_SYS_FLASH_CFI 202 #define CONFIG_SYS_FLASH_EMPTY_INFO 203 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 204 205 /* NAND Flash on IFC */ 206 #define CONFIG_NAND_FSL_IFC 207 #define CONFIG_SYS_NAND_BASE 0xff800000 208 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 209 210 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 211 212 #define CONFIG_SYS_MAX_NAND_DEVICE 1 213 #define CONFIG_CMD_NAND 214 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 215 216 /* 8Bit NAND Flash - K9F1G08U0B */ 217 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 218 | CSPR_PORT_SIZE_8 \ 219 | CSPR_MSEL_NAND \ 220 | CSPR_V) 221 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 222 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 223 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 224 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 225 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 226 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 227 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 228 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 229 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 230 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 231 FTIM0_NAND_TWP(0x0c) | \ 232 FTIM0_NAND_TWCHT(0x08) | \ 233 FTIM0_NAND_TWH(0x06)) 234 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 235 FTIM1_NAND_TWBE(0x1d) | \ 236 FTIM1_NAND_TRR(0x08) | \ 237 FTIM1_NAND_TRP(0x0c)) 238 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 239 FTIM2_NAND_TREH(0x0a) | \ 240 FTIM2_NAND_TWHRE(0x18)) 241 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 242 243 #define CONFIG_SYS_NAND_DDR_LAW 11 244 245 /* Set up IFC registers for boot location NOR/NAND */ 246 #ifdef CONFIG_NAND 247 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 248 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 249 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 250 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 251 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 252 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 253 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 254 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 255 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 256 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 257 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 258 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 259 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 260 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 261 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 262 #else 263 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 264 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 265 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 266 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 267 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 268 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 269 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 270 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 271 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 272 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 273 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 274 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 275 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 276 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 277 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 278 #endif 279 280 /* CPLD on IFC, selected by CS2 */ 281 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 282 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 283 | CONFIG_SYS_CPLD_BASE) 284 285 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 286 | CSPR_PORT_SIZE_8 \ 287 | CSPR_MSEL_GPCM \ 288 | CSPR_V) 289 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 290 #define CONFIG_SYS_CSOR2 0x0 291 /* CPLD Timing parameters for IFC CS2 */ 292 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 293 FTIM0_GPCM_TEADC(0x0e) | \ 294 FTIM0_GPCM_TEAHC(0x0e)) 295 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 296 FTIM1_GPCM_TRAD(0x1f)) 297 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 298 FTIM2_GPCM_TCH(0x8) | \ 299 FTIM2_GPCM_TWP(0x1f)) 300 #define CONFIG_SYS_CS2_FTIM3 0x0 301 302 #if defined(CONFIG_RAMBOOT_SPIFLASH) 303 #define CONFIG_SYS_RAMBOOT 304 #define CONFIG_SYS_EXTRA_ENV_RELOC 305 #endif 306 307 #define CONFIG_BOARD_EARLY_INIT_R 308 309 #define CONFIG_SYS_INIT_RAM_LOCK 310 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 311 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 312 313 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 314 - GENERATED_GBL_DATA_SIZE) 315 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 316 317 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 318 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 319 320 /* 321 * Config the L2 Cache as L2 SRAM 322 */ 323 #if defined(CONFIG_SPL_BUILD) 324 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 325 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 326 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 327 #define CONFIG_SYS_L2_SIZE (256 << 10) 328 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 329 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 330 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 331 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 332 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 333 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 334 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 335 #elif defined(CONFIG_NAND) 336 #ifdef CONFIG_TPL_BUILD 337 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 338 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 339 #define CONFIG_SYS_L2_SIZE (256 << 10) 340 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 341 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 342 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 343 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 344 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 345 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 346 #else 347 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 348 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 349 #define CONFIG_SYS_L2_SIZE (256 << 10) 350 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 351 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 352 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 353 #endif 354 #endif 355 #endif 356 357 /* Serial Port */ 358 #define CONFIG_CONS_INDEX 1 359 #define CONFIG_SYS_NS16550_SERIAL 360 #define CONFIG_SYS_NS16550_REG_SIZE 1 361 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 362 363 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 364 #define CONFIG_NS16550_MIN_FUNCTIONS 365 #endif 366 367 #define CONFIG_SYS_BAUDRATE_TABLE \ 368 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 369 370 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 371 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 372 373 #define CONFIG_SYS_I2C 374 #define CONFIG_SYS_I2C_FSL 375 #define CONFIG_SYS_FSL_I2C_SPEED 400000 376 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 377 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 378 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 379 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 380 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 381 382 /* I2C EEPROM */ 383 /* enable read and write access to EEPROM */ 384 #define CONFIG_CMD_EEPROM 385 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 386 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 387 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 388 389 /* eSPI - Enhanced SPI */ 390 #define CONFIG_SF_DEFAULT_SPEED 10000000 391 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 392 393 #ifdef CONFIG_TSEC_ENET 394 #define CONFIG_MII /* MII PHY management */ 395 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 396 #define CONFIG_TSEC1 1 397 #define CONFIG_TSEC1_NAME "eTSEC1" 398 #define CONFIG_TSEC2 1 399 #define CONFIG_TSEC2_NAME "eTSEC2" 400 401 /* Default mode is RGMII mode */ 402 #define TSEC1_PHY_ADDR 0 403 #define TSEC2_PHY_ADDR 2 404 405 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 406 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 407 408 #define CONFIG_ETHPRIME "eTSEC1" 409 410 #define CONFIG_PHY_GIGE 411 #endif /* CONFIG_TSEC_ENET */ 412 413 /* 414 * Environment 415 */ 416 #if defined(CONFIG_SYS_RAMBOOT) 417 #if defined(CONFIG_RAMBOOT_SPIFLASH) 418 #define CONFIG_ENV_IS_IN_SPI_FLASH 419 #define CONFIG_ENV_SPI_BUS 0 420 #define CONFIG_ENV_SPI_CS 0 421 #define CONFIG_ENV_SPI_MAX_HZ 10000000 422 #define CONFIG_ENV_SPI_MODE 0 423 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 424 #define CONFIG_ENV_SECT_SIZE 0x10000 425 #define CONFIG_ENV_SIZE 0x2000 426 #endif 427 #elif defined(CONFIG_NAND) 428 #define CONFIG_ENV_IS_IN_NAND 429 #ifdef CONFIG_TPL_BUILD 430 #define CONFIG_ENV_SIZE 0x2000 431 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 432 #else 433 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 434 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 435 #endif 436 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE 437 #else 438 #define CONFIG_ENV_IS_IN_FLASH 439 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 440 #define CONFIG_ENV_SIZE 0x2000 441 #define CONFIG_ENV_SECT_SIZE 0x20000 442 #endif 443 444 #define CONFIG_LOADS_ECHO 445 #define CONFIG_SYS_LOADS_BAUD_CHANGE 446 447 /* 448 * Command line configuration. 449 */ 450 #define CONFIG_CMD_ERRATA 451 #define CONFIG_CMD_IRQ 452 #define CONFIG_CMD_REGINFO 453 454 /* Hash command with SHA acceleration supported in hardware */ 455 #ifdef CONFIG_FSL_CAAM 456 #define CONFIG_CMD_HASH 457 #define CONFIG_SHA_HW_ACCEL 458 #endif 459 460 /* 461 * Miscellaneous configurable options 462 */ 463 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 464 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 465 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 466 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 467 468 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 469 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 470 /* Print Buffer Size */ 471 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 472 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 473 474 /* 475 * For booting Linux, the board info and command line data 476 * have to be in the first 64 MB of memory, since this is 477 * the maximum mapped by the Linux kernel during initialization. 478 */ 479 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 480 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 481 482 /* 483 * Environment Configuration 484 */ 485 486 #ifdef CONFIG_TSEC_ENET 487 #define CONFIG_HAS_ETH0 488 #define CONFIG_HAS_ETH1 489 #endif 490 491 #define CONFIG_ROOTPATH "/opt/nfsroot" 492 #define CONFIG_BOOTFILE "uImage" 493 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 494 495 /* default location for tftp and bootm */ 496 #define CONFIG_LOADADDR 1000000 497 498 499 #define CONFIG_BAUDRATE 115200 500 501 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 502 503 #define CONFIG_EXTRA_ENV_SETTINGS \ 504 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 505 "netdev=eth0\0" \ 506 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 507 "loadaddr=1000000\0" \ 508 "consoledev=ttyS0\0" \ 509 "ramdiskaddr=2000000\0" \ 510 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 511 "fdtaddr=1e00000\0" \ 512 "fdtfile=name/of/device-tree.dtb\0" \ 513 "othbootargs=ramdisk_size=600000\0" \ 514 515 #define CONFIG_RAMBOOTCOMMAND \ 516 "setenv bootargs root=/dev/ram rw " \ 517 "console=$consoledev,$baudrate $othbootargs; " \ 518 "tftp $ramdiskaddr $ramdiskfile;" \ 519 "tftp $loadaddr $bootfile;" \ 520 "tftp $fdtaddr $fdtfile;" \ 521 "bootm $loadaddr $ramdiskaddr $fdtaddr" 522 523 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 524 525 #include <asm/fsl_secure_boot.h> 526 527 #endif /* __CONFIG_H */ 528