1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_C29XPCIE 15 #define CONFIG_PPC_C29X 16 #endif 17 18 #ifdef CONFIG_SPIFLASH 19 #define CONFIG_RAMBOOT_SPIFLASH 20 #define CONFIG_SYS_TEXT_BASE 0x11000000 21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 22 #endif 23 24 #ifdef CONFIG_NAND 25 #ifdef CONFIG_TPL_BUILD 26 #define CONFIG_SPL_NAND_BOOT 27 #define CONFIG_SPL_FLUSH_IMAGE 28 #define CONFIG_SPL_NAND_INIT 29 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT 30 #define CONFIG_SPL_COMMON_INIT_DDR 31 #define CONFIG_SPL_MAX_SIZE (128 << 10) 32 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 33 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 34 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 35 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 36 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 37 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 38 #elif defined(CONFIG_SPL_BUILD) 39 #define CONFIG_SPL_INIT_MINIMAL 40 #define CONFIG_SPL_NAND_MINIMAL 41 #define CONFIG_SPL_FLUSH_IMAGE 42 #define CONFIG_SPL_TEXT_BASE 0xff800000 43 #define CONFIG_SPL_MAX_SIZE 8192 44 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 45 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 46 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 47 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 48 #endif 49 #define CONFIG_SPL_PAD_TO 0x20000 50 #define CONFIG_TPL_PAD_TO 0x20000 51 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 52 #define CONFIG_SYS_TEXT_BASE 0x11001000 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #endif 55 56 #ifndef CONFIG_SYS_TEXT_BASE 57 #define CONFIG_SYS_TEXT_BASE 0xeff40000 58 #endif 59 60 #ifndef CONFIG_RESET_VECTOR_ADDRESS 61 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 62 #endif 63 64 #ifdef CONFIG_SPL_BUILD 65 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 66 #else 67 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 68 #endif 69 70 #ifdef CONFIG_SPL_BUILD 71 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 72 #endif 73 74 /* High Level Configuration Options */ 75 #define CONFIG_BOOKE /* BOOKE */ 76 #define CONFIG_E500 /* BOOKE e500 family */ 77 #define CONFIG_FSL_IFC /* Enable IFC Support */ 78 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 79 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 80 81 #define CONFIG_PCI /* Enable PCI/PCIE */ 82 #ifdef CONFIG_PCI 83 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 84 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 85 #define CONFIG_PCI_INDIRECT_BRIDGE 86 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 87 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 88 89 #define CONFIG_CMD_PCI 90 91 /* 92 * PCI Windows 93 * Memory space is mapped 1-1, but I/O space must start from 0. 94 */ 95 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 96 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 97 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 98 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 99 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 100 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 101 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 102 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 103 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 104 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 105 106 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 107 108 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 109 #define CONFIG_DOS_PARTITION 110 #endif 111 112 #define CONFIG_FSL_LAW /* Use common FSL init code */ 113 #define CONFIG_TSEC_ENET 114 #define CONFIG_ENV_OVERWRITE 115 116 #define CONFIG_DDR_CLK_FREQ 100000000 117 #define CONFIG_SYS_CLK_FREQ 66666666 118 119 #define CONFIG_HWCONFIG 120 121 /* 122 * These can be toggled for performance analysis, otherwise use default. 123 */ 124 #define CONFIG_L2_CACHE /* toggle L2 cache */ 125 #define CONFIG_BTB /* toggle branch predition */ 126 127 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 128 129 #define CONFIG_ENABLE_36BIT_PHYS 130 131 #define CONFIG_ADDR_MAP 1 132 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 133 134 #define CONFIG_SYS_MEMTEST_START 0x00200000 135 #define CONFIG_SYS_MEMTEST_END 0x00400000 136 #define CONFIG_PANIC_HANG 137 138 /* DDR Setup */ 139 #define CONFIG_SYS_FSL_DDR3 140 #define CONFIG_DDR_SPD 141 #define CONFIG_SYS_SPD_BUS_NUM 0 142 #define SPD_EEPROM_ADDRESS 0x50 143 #define CONFIG_SYS_DDR_RAW_TIMING 144 145 /* DDR ECC Setup*/ 146 #define CONFIG_DDR_ECC 147 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 148 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 149 150 #define CONFIG_SYS_SDRAM_SIZE 512 151 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 152 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 153 154 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 155 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 156 157 #define CONFIG_SYS_CCSRBAR 0xffe00000 158 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 159 160 /* Platform SRAM setting */ 161 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 162 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 163 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 164 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 165 166 #ifdef CONFIG_SPL_BUILD 167 #define CONFIG_SYS_NO_FLASH 168 #endif 169 170 /* 171 * IFC Definitions 172 */ 173 /* NOR Flash on IFC */ 174 #define CONFIG_SYS_FLASH_BASE 0xec000000 175 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 176 177 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 178 179 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 180 #define CONFIG_SYS_MAX_FLASH_BANKS 1 181 182 #define CONFIG_SYS_FLASH_QUIET_TEST 183 #define CONFIG_FLASH_SHOW_PROGRESS 45 184 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 185 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 186 187 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 188 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 189 CSPR_PORT_SIZE_16 | \ 190 CSPR_MSEL_NOR | \ 191 CSPR_V) 192 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 193 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 194 195 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 196 FTIM0_NOR_TEADC(0x5) | \ 197 FTIM0_NOR_TEAHC(0x5)) 198 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 199 FTIM1_NOR_TRAD_NOR(0x1A) |\ 200 FTIM1_NOR_TSEQRAD_NOR(0x13)) 201 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 202 FTIM2_NOR_TCH(0x4) | \ 203 FTIM2_NOR_TWPH(0x0E) | \ 204 FTIM2_NOR_TWP(0x1c)) 205 #define CONFIG_SYS_NOR_FTIM3 0x0 206 207 /* CFI for NOR Flash */ 208 #define CONFIG_FLASH_CFI_DRIVER 209 #define CONFIG_SYS_FLASH_CFI 210 #define CONFIG_SYS_FLASH_EMPTY_INFO 211 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 212 213 /* NAND Flash on IFC */ 214 #define CONFIG_NAND_FSL_IFC 215 #define CONFIG_SYS_NAND_BASE 0xff800000 216 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 217 218 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 219 220 #define CONFIG_SYS_MAX_NAND_DEVICE 1 221 #define CONFIG_CMD_NAND 222 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 223 224 /* 8Bit NAND Flash - K9F1G08U0B */ 225 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 226 | CSPR_PORT_SIZE_8 \ 227 | CSPR_MSEL_NAND \ 228 | CSPR_V) 229 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 230 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 231 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 232 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 233 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 234 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 235 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 236 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 237 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 238 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 239 FTIM0_NAND_TWP(0x0c) | \ 240 FTIM0_NAND_TWCHT(0x08) | \ 241 FTIM0_NAND_TWH(0x06)) 242 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 243 FTIM1_NAND_TWBE(0x1d) | \ 244 FTIM1_NAND_TRR(0x08) | \ 245 FTIM1_NAND_TRP(0x0c)) 246 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 247 FTIM2_NAND_TREH(0x0a) | \ 248 FTIM2_NAND_TWHRE(0x18)) 249 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 250 251 #define CONFIG_SYS_NAND_DDR_LAW 11 252 253 /* Set up IFC registers for boot location NOR/NAND */ 254 #ifdef CONFIG_NAND 255 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 256 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 257 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 258 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 259 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 260 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 261 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 262 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 263 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 264 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 265 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 266 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 267 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 268 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 269 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 270 #else 271 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 272 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 273 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 274 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 275 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 276 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 277 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 278 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 279 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 280 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 281 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 282 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 283 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 284 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 285 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 286 #endif 287 288 /* CPLD on IFC, selected by CS2 */ 289 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 290 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 291 | CONFIG_SYS_CPLD_BASE) 292 293 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 294 | CSPR_PORT_SIZE_8 \ 295 | CSPR_MSEL_GPCM \ 296 | CSPR_V) 297 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 298 #define CONFIG_SYS_CSOR2 0x0 299 /* CPLD Timing parameters for IFC CS2 */ 300 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 301 FTIM0_GPCM_TEADC(0x0e) | \ 302 FTIM0_GPCM_TEAHC(0x0e)) 303 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 304 FTIM1_GPCM_TRAD(0x1f)) 305 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 306 FTIM2_GPCM_TCH(0x8) | \ 307 FTIM2_GPCM_TWP(0x1f)) 308 #define CONFIG_SYS_CS2_FTIM3 0x0 309 310 #if defined(CONFIG_RAMBOOT_SPIFLASH) 311 #define CONFIG_SYS_RAMBOOT 312 #define CONFIG_SYS_EXTRA_ENV_RELOC 313 #endif 314 315 #define CONFIG_BOARD_EARLY_INIT_R 316 317 #define CONFIG_SYS_INIT_RAM_LOCK 318 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 319 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 320 321 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 322 - GENERATED_GBL_DATA_SIZE) 323 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 324 325 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 326 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 327 328 /* 329 * Config the L2 Cache as L2 SRAM 330 */ 331 #if defined(CONFIG_SPL_BUILD) 332 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 333 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 334 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 335 #define CONFIG_SYS_L2_SIZE (256 << 10) 336 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 337 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 338 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 339 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 340 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 341 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 342 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 343 #elif defined(CONFIG_NAND) 344 #ifdef CONFIG_TPL_BUILD 345 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 346 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 347 #define CONFIG_SYS_L2_SIZE (256 << 10) 348 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 349 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 350 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 351 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 352 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 353 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 354 #else 355 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 356 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 357 #define CONFIG_SYS_L2_SIZE (256 << 10) 358 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 359 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 360 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 361 #endif 362 #endif 363 #endif 364 365 /* Serial Port */ 366 #define CONFIG_CONS_INDEX 1 367 #define CONFIG_SYS_NS16550_SERIAL 368 #define CONFIG_SYS_NS16550_REG_SIZE 1 369 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 370 371 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 372 #define CONFIG_NS16550_MIN_FUNCTIONS 373 #endif 374 375 #define CONFIG_SYS_BAUDRATE_TABLE \ 376 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 377 378 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 379 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 380 381 #define CONFIG_SYS_I2C 382 #define CONFIG_SYS_I2C_FSL 383 #define CONFIG_SYS_FSL_I2C_SPEED 400000 384 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 385 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 386 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 387 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 388 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 389 390 /* I2C EEPROM */ 391 /* enable read and write access to EEPROM */ 392 #define CONFIG_CMD_EEPROM 393 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 394 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 395 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 396 397 /* eSPI - Enhanced SPI */ 398 #define CONFIG_SF_DEFAULT_SPEED 10000000 399 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 400 401 #ifdef CONFIG_TSEC_ENET 402 #define CONFIG_MII /* MII PHY management */ 403 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 404 #define CONFIG_TSEC1 1 405 #define CONFIG_TSEC1_NAME "eTSEC1" 406 #define CONFIG_TSEC2 1 407 #define CONFIG_TSEC2_NAME "eTSEC2" 408 409 /* Default mode is RGMII mode */ 410 #define TSEC1_PHY_ADDR 0 411 #define TSEC2_PHY_ADDR 2 412 413 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 414 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 415 416 #define CONFIG_ETHPRIME "eTSEC1" 417 418 #define CONFIG_PHY_GIGE 419 #endif /* CONFIG_TSEC_ENET */ 420 421 /* 422 * Environment 423 */ 424 #if defined(CONFIG_SYS_RAMBOOT) 425 #if defined(CONFIG_RAMBOOT_SPIFLASH) 426 #define CONFIG_ENV_IS_IN_SPI_FLASH 427 #define CONFIG_ENV_SPI_BUS 0 428 #define CONFIG_ENV_SPI_CS 0 429 #define CONFIG_ENV_SPI_MAX_HZ 10000000 430 #define CONFIG_ENV_SPI_MODE 0 431 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 432 #define CONFIG_ENV_SECT_SIZE 0x10000 433 #define CONFIG_ENV_SIZE 0x2000 434 #endif 435 #elif defined(CONFIG_NAND) 436 #define CONFIG_ENV_IS_IN_NAND 437 #ifdef CONFIG_TPL_BUILD 438 #define CONFIG_ENV_SIZE 0x2000 439 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 440 #else 441 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 442 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 443 #endif 444 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE 445 #else 446 #define CONFIG_ENV_IS_IN_FLASH 447 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 448 #define CONFIG_ENV_SIZE 0x2000 449 #define CONFIG_ENV_SECT_SIZE 0x20000 450 #endif 451 452 #define CONFIG_LOADS_ECHO 453 #define CONFIG_SYS_LOADS_BAUD_CHANGE 454 455 /* 456 * Command line configuration. 457 */ 458 #define CONFIG_CMD_ERRATA 459 #define CONFIG_CMD_IRQ 460 #define CONFIG_CMD_REGINFO 461 462 /* Hash command with SHA acceleration supported in hardware */ 463 #ifdef CONFIG_FSL_CAAM 464 #define CONFIG_CMD_HASH 465 #define CONFIG_SHA_HW_ACCEL 466 #endif 467 468 /* 469 * Miscellaneous configurable options 470 */ 471 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 472 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 473 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 474 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 475 476 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 477 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 478 /* Print Buffer Size */ 479 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 480 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 481 482 /* 483 * For booting Linux, the board info and command line data 484 * have to be in the first 64 MB of memory, since this is 485 * the maximum mapped by the Linux kernel during initialization. 486 */ 487 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 488 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 489 490 /* 491 * Environment Configuration 492 */ 493 494 #ifdef CONFIG_TSEC_ENET 495 #define CONFIG_HAS_ETH0 496 #define CONFIG_HAS_ETH1 497 #endif 498 499 #define CONFIG_ROOTPATH "/opt/nfsroot" 500 #define CONFIG_BOOTFILE "uImage" 501 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 502 503 /* default location for tftp and bootm */ 504 #define CONFIG_LOADADDR 1000000 505 506 507 #define CONFIG_BAUDRATE 115200 508 509 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 510 511 #define CONFIG_EXTRA_ENV_SETTINGS \ 512 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 513 "netdev=eth0\0" \ 514 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 515 "loadaddr=1000000\0" \ 516 "consoledev=ttyS0\0" \ 517 "ramdiskaddr=2000000\0" \ 518 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 519 "fdtaddr=1e00000\0" \ 520 "fdtfile=name/of/device-tree.dtb\0" \ 521 "othbootargs=ramdisk_size=600000\0" \ 522 523 #define CONFIG_RAMBOOTCOMMAND \ 524 "setenv bootargs root=/dev/ram rw " \ 525 "console=$consoledev,$baudrate $othbootargs; " \ 526 "tftp $ramdiskaddr $ramdiskfile;" \ 527 "tftp $loadaddr $bootfile;" \ 528 "tftp $fdtaddr $fdtfile;" \ 529 "bootm $loadaddr $ramdiskaddr $fdtaddr" 530 531 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 532 533 #include <asm/fsl_secure_boot.h> 534 535 #endif /* __CONFIG_H */ 536