1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_PHYS_64BIT 15 #define CONFIG_SYS_GENERIC_BOARD 16 #define CONFIG_DISPLAY_BOARDINFO 17 18 #ifdef CONFIG_C29XPCIE 19 #define CONFIG_PPC_C29X 20 #endif 21 22 #ifdef CONFIG_SPIFLASH 23 #define CONFIG_RAMBOOT_SPIFLASH 24 #define CONFIG_SYS_TEXT_BASE 0x11000000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 26 #endif 27 28 #ifdef CONFIG_NAND 29 #ifdef CONFIG_TPL_BUILD 30 #define CONFIG_SPL_NAND_BOOT 31 #define CONFIG_SPL_FLUSH_IMAGE 32 #define CONFIG_SPL_ENV_SUPPORT 33 #define CONFIG_SPL_NAND_INIT 34 #define CONFIG_SPL_SERIAL_SUPPORT 35 #define CONFIG_SPL_LIBGENERIC_SUPPORT 36 #define CONFIG_SPL_LIBCOMMON_SUPPORT 37 #define CONFIG_SPL_I2C_SUPPORT 38 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 39 #define CONFIG_SPL_NAND_SUPPORT 40 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 41 #define CONFIG_SPL_COMMON_INIT_DDR 42 #define CONFIG_SPL_MAX_SIZE (128 << 10) 43 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 44 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 45 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 46 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 47 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 48 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 49 #elif defined(CONFIG_SPL_BUILD) 50 #define CONFIG_SPL_INIT_MINIMAL 51 #define CONFIG_SPL_SERIAL_SUPPORT 52 #define CONFIG_SPL_NAND_SUPPORT 53 #define CONFIG_SPL_NAND_MINIMAL 54 #define CONFIG_SPL_FLUSH_IMAGE 55 #define CONFIG_SPL_TEXT_BASE 0xff800000 56 #define CONFIG_SPL_MAX_SIZE 8192 57 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 58 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 59 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 60 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 61 #endif 62 #define CONFIG_SPL_PAD_TO 0x20000 63 #define CONFIG_TPL_PAD_TO 0x20000 64 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 65 #define CONFIG_SYS_TEXT_BASE 0x11001000 66 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 67 #endif 68 69 #ifndef CONFIG_SYS_TEXT_BASE 70 #define CONFIG_SYS_TEXT_BASE 0xeff40000 71 #endif 72 73 #ifndef CONFIG_RESET_VECTOR_ADDRESS 74 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 75 #endif 76 77 #ifdef CONFIG_SPL_BUILD 78 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 79 #else 80 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 81 #endif 82 83 #ifdef CONFIG_SPL_BUILD 84 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 85 #endif 86 87 /* High Level Configuration Options */ 88 #define CONFIG_BOOKE /* BOOKE */ 89 #define CONFIG_E500 /* BOOKE e500 family */ 90 #define CONFIG_FSL_IFC /* Enable IFC Support */ 91 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 92 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 93 94 #define CONFIG_PCI /* Enable PCI/PCIE */ 95 #ifdef CONFIG_PCI 96 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 97 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 98 #define CONFIG_PCI_INDIRECT_BRIDGE 99 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 100 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 101 102 #define CONFIG_CMD_PCI 103 104 #define CONFIG_E1000 105 106 /* 107 * PCI Windows 108 * Memory space is mapped 1-1, but I/O space must start from 0. 109 */ 110 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 111 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 112 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 113 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 114 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 115 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 116 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 117 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 118 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 119 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 120 121 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 122 123 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 124 #define CONFIG_DOS_PARTITION 125 #endif 126 127 #define CONFIG_FSL_LAW /* Use common FSL init code */ 128 #define CONFIG_TSEC_ENET 129 #define CONFIG_ENV_OVERWRITE 130 131 #define CONFIG_DDR_CLK_FREQ 100000000 132 #define CONFIG_SYS_CLK_FREQ 66666666 133 134 #define CONFIG_HWCONFIG 135 136 /* 137 * These can be toggled for performance analysis, otherwise use default. 138 */ 139 #define CONFIG_L2_CACHE /* toggle L2 cache */ 140 #define CONFIG_BTB /* toggle branch predition */ 141 142 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 143 144 #define CONFIG_ENABLE_36BIT_PHYS 145 146 #define CONFIG_ADDR_MAP 1 147 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 148 149 #define CONFIG_SYS_MEMTEST_START 0x00200000 150 #define CONFIG_SYS_MEMTEST_END 0x00400000 151 #define CONFIG_PANIC_HANG 152 153 /* DDR Setup */ 154 #define CONFIG_SYS_FSL_DDR3 155 #define CONFIG_DDR_SPD 156 #define CONFIG_SYS_SPD_BUS_NUM 0 157 #define SPD_EEPROM_ADDRESS 0x50 158 #define CONFIG_SYS_DDR_RAW_TIMING 159 160 /* DDR ECC Setup*/ 161 #define CONFIG_DDR_ECC 162 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 163 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 164 165 #define CONFIG_SYS_SDRAM_SIZE 512 166 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 167 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 168 169 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 170 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 171 172 #define CONFIG_SYS_CCSRBAR 0xffe00000 173 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 174 175 /* Platform SRAM setting */ 176 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 177 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 178 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 179 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 180 181 #ifdef CONFIG_SPL_BUILD 182 #define CONFIG_SYS_NO_FLASH 183 #endif 184 185 /* 186 * IFC Definitions 187 */ 188 /* NOR Flash on IFC */ 189 #define CONFIG_SYS_FLASH_BASE 0xec000000 190 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 191 192 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 193 194 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 195 #define CONFIG_SYS_MAX_FLASH_BANKS 1 196 197 #define CONFIG_SYS_FLASH_QUIET_TEST 198 #define CONFIG_FLASH_SHOW_PROGRESS 45 199 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 200 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 201 202 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 203 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 204 CSPR_PORT_SIZE_16 | \ 205 CSPR_MSEL_NOR | \ 206 CSPR_V) 207 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 208 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 209 210 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 211 FTIM0_NOR_TEADC(0x5) | \ 212 FTIM0_NOR_TEAHC(0x5)) 213 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 214 FTIM1_NOR_TRAD_NOR(0x1A) |\ 215 FTIM1_NOR_TSEQRAD_NOR(0x13)) 216 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 217 FTIM2_NOR_TCH(0x4) | \ 218 FTIM2_NOR_TWPH(0x0E) | \ 219 FTIM2_NOR_TWP(0x1c)) 220 #define CONFIG_SYS_NOR_FTIM3 0x0 221 222 /* CFI for NOR Flash */ 223 #define CONFIG_FLASH_CFI_DRIVER 224 #define CONFIG_SYS_FLASH_CFI 225 #define CONFIG_SYS_FLASH_EMPTY_INFO 226 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 227 228 /* NAND Flash on IFC */ 229 #define CONFIG_NAND_FSL_IFC 230 #define CONFIG_SYS_NAND_BASE 0xff800000 231 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 232 233 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 234 235 #define CONFIG_SYS_MAX_NAND_DEVICE 1 236 #define CONFIG_CMD_NAND 237 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 238 239 /* 8Bit NAND Flash - K9F1G08U0B */ 240 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 241 | CSPR_PORT_SIZE_8 \ 242 | CSPR_MSEL_NAND \ 243 | CSPR_V) 244 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 245 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 246 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 247 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 248 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 249 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 250 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 251 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 252 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 253 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 254 FTIM0_NAND_TWP(0x0c) | \ 255 FTIM0_NAND_TWCHT(0x08) | \ 256 FTIM0_NAND_TWH(0x06)) 257 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 258 FTIM1_NAND_TWBE(0x1d) | \ 259 FTIM1_NAND_TRR(0x08) | \ 260 FTIM1_NAND_TRP(0x0c)) 261 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 262 FTIM2_NAND_TREH(0x0a) | \ 263 FTIM2_NAND_TWHRE(0x18)) 264 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 265 266 #define CONFIG_SYS_NAND_DDR_LAW 11 267 268 /* Set up IFC registers for boot location NOR/NAND */ 269 #ifdef CONFIG_NAND 270 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 271 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 272 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 273 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 274 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 275 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 276 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 277 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 278 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 279 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 280 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 281 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 282 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 283 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 284 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 285 #else 286 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 287 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 288 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 289 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 290 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 291 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 292 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 293 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 294 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 295 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 296 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 297 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 298 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 299 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 300 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 301 #endif 302 303 /* CPLD on IFC, selected by CS2 */ 304 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 305 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 306 | CONFIG_SYS_CPLD_BASE) 307 308 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 309 | CSPR_PORT_SIZE_8 \ 310 | CSPR_MSEL_GPCM \ 311 | CSPR_V) 312 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 313 #define CONFIG_SYS_CSOR2 0x0 314 /* CPLD Timing parameters for IFC CS2 */ 315 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 316 FTIM0_GPCM_TEADC(0x0e) | \ 317 FTIM0_GPCM_TEAHC(0x0e)) 318 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 319 FTIM1_GPCM_TRAD(0x1f)) 320 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 321 FTIM2_GPCM_TCH(0x8) | \ 322 FTIM2_GPCM_TWP(0x1f)) 323 #define CONFIG_SYS_CS2_FTIM3 0x0 324 325 #if defined(CONFIG_RAMBOOT_SPIFLASH) 326 #define CONFIG_SYS_RAMBOOT 327 #define CONFIG_SYS_EXTRA_ENV_RELOC 328 #endif 329 330 #define CONFIG_BOARD_EARLY_INIT_R 331 332 #define CONFIG_SYS_INIT_RAM_LOCK 333 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 334 #define CONFIG_SYS_INIT_RAM_END 0x00004000 335 336 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 337 - GENERATED_GBL_DATA_SIZE) 338 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 339 340 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 341 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 342 343 /* 344 * Config the L2 Cache as L2 SRAM 345 */ 346 #if defined(CONFIG_SPL_BUILD) 347 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 348 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 349 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 350 #define CONFIG_SYS_L2_SIZE (256 << 10) 351 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 352 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 353 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 354 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 355 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 356 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 357 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 358 #elif defined(CONFIG_NAND) 359 #ifdef CONFIG_TPL_BUILD 360 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 361 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 362 #define CONFIG_SYS_L2_SIZE (256 << 10) 363 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 364 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 365 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 366 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 367 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 368 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 369 #else 370 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 371 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 372 #define CONFIG_SYS_L2_SIZE (256 << 10) 373 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 374 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 375 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 376 #endif 377 #endif 378 #endif 379 380 /* Serial Port */ 381 #define CONFIG_CONS_INDEX 1 382 #define CONFIG_SYS_NS16550 383 #define CONFIG_SYS_NS16550_SERIAL 384 #define CONFIG_SYS_NS16550_REG_SIZE 1 385 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 386 387 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 388 #define CONFIG_NS16550_MIN_FUNCTIONS 389 #endif 390 391 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 392 393 #define CONFIG_SYS_BAUDRATE_TABLE \ 394 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 395 396 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 397 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 398 399 /* Use the HUSH parser */ 400 #define CONFIG_SYS_HUSH_PARSER 401 402 /* 403 * Pass open firmware flat tree 404 */ 405 #define CONFIG_OF_LIBFDT 406 #define CONFIG_OF_BOARD_SETUP 407 #define CONFIG_OF_STDOUT_VIA_ALIAS 408 409 /* new uImage format support */ 410 #define CONFIG_FIT 411 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 412 413 #define CONFIG_SYS_I2C 414 #define CONFIG_SYS_I2C_FSL 415 #define CONFIG_SYS_FSL_I2C_SPEED 400000 416 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 417 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 418 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 419 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 420 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 421 422 /* I2C EEPROM */ 423 /* enable read and write access to EEPROM */ 424 #define CONFIG_CMD_EEPROM 425 #define CONFIG_SYS_I2C_MULTI_EEPROMS 426 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 427 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 428 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 429 430 #define CONFIG_CMD_I2C 431 432 /* eSPI - Enhanced SPI */ 433 #define CONFIG_FSL_ESPI 434 #define CONFIG_SPI_FLASH_SPANSION 435 #define CONFIG_SPI_FLASH_EON 436 #define CONFIG_CMD_SF 437 #define CONFIG_SF_DEFAULT_SPEED 10000000 438 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 439 440 #ifdef CONFIG_TSEC_ENET 441 #define CONFIG_MII /* MII PHY management */ 442 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 443 #define CONFIG_TSEC1 1 444 #define CONFIG_TSEC1_NAME "eTSEC1" 445 #define CONFIG_TSEC2 1 446 #define CONFIG_TSEC2_NAME "eTSEC2" 447 448 /* Default mode is RGMII mode */ 449 #define TSEC1_PHY_ADDR 0 450 #define TSEC2_PHY_ADDR 2 451 452 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 453 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 454 455 #define CONFIG_ETHPRIME "eTSEC1" 456 457 #define CONFIG_PHY_GIGE 458 #endif /* CONFIG_TSEC_ENET */ 459 460 /* 461 * Environment 462 */ 463 #if defined(CONFIG_SYS_RAMBOOT) 464 #if defined(CONFIG_RAMBOOT_SPIFLASH) 465 #define CONFIG_ENV_IS_IN_SPI_FLASH 466 #define CONFIG_ENV_SPI_BUS 0 467 #define CONFIG_ENV_SPI_CS 0 468 #define CONFIG_ENV_SPI_MAX_HZ 10000000 469 #define CONFIG_ENV_SPI_MODE 0 470 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 471 #define CONFIG_ENV_SECT_SIZE 0x10000 472 #define CONFIG_ENV_SIZE 0x2000 473 #endif 474 #elif defined(CONFIG_NAND) 475 #define CONFIG_ENV_IS_IN_NAND 476 #ifdef CONFIG_TPL_BUILD 477 #define CONFIG_ENV_SIZE 0x2000 478 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 479 #else 480 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 481 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 482 #endif 483 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE 484 #else 485 #define CONFIG_ENV_IS_IN_FLASH 486 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 487 #define CONFIG_ENV_SIZE 0x2000 488 #define CONFIG_ENV_SECT_SIZE 0x20000 489 #endif 490 491 #define CONFIG_LOADS_ECHO 492 #define CONFIG_SYS_LOADS_BAUD_CHANGE 493 494 /* 495 * Command line configuration. 496 */ 497 #define CONFIG_CMD_ERRATA 498 #define CONFIG_CMD_ELF 499 #define CONFIG_CMD_IRQ 500 #define CONFIG_CMD_MII 501 #define CONFIG_CMD_PING 502 #define CONFIG_CMD_REGINFO 503 504 /* Hash command with SHA acceleration supported in hardware */ 505 #ifdef CONFIG_FSL_CAAM 506 #define CONFIG_CMD_HASH 507 #define CONFIG_SHA_HW_ACCEL 508 #endif 509 510 /* 511 * Miscellaneous configurable options 512 */ 513 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 514 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 515 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 516 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 517 518 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 519 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 520 /* Print Buffer Size */ 521 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 522 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 523 524 /* 525 * For booting Linux, the board info and command line data 526 * have to be in the first 64 MB of memory, since this is 527 * the maximum mapped by the Linux kernel during initialization. 528 */ 529 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 530 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 531 532 /* 533 * Environment Configuration 534 */ 535 536 #ifdef CONFIG_TSEC_ENET 537 #define CONFIG_HAS_ETH0 538 #define CONFIG_HAS_ETH1 539 #endif 540 541 #define CONFIG_ROOTPATH "/opt/nfsroot" 542 #define CONFIG_BOOTFILE "uImage" 543 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 544 545 /* default location for tftp and bootm */ 546 #define CONFIG_LOADADDR 1000000 547 548 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 549 550 #define CONFIG_BAUDRATE 115200 551 552 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 553 554 #define CONFIG_EXTRA_ENV_SETTINGS \ 555 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 556 "netdev=eth0\0" \ 557 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 558 "loadaddr=1000000\0" \ 559 "consoledev=ttyS0\0" \ 560 "ramdiskaddr=2000000\0" \ 561 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 562 "fdtaddr=c00000\0" \ 563 "fdtfile=name/of/device-tree.dtb\0" \ 564 "othbootargs=ramdisk_size=600000\0" \ 565 566 #define CONFIG_RAMBOOTCOMMAND \ 567 "setenv bootargs root=/dev/ram rw " \ 568 "console=$consoledev,$baudrate $othbootargs; " \ 569 "tftp $ramdiskaddr $ramdiskfile;" \ 570 "tftp $loadaddr $bootfile;" \ 571 "tftp $fdtaddr $fdtfile;" \ 572 "bootm $loadaddr $ramdiskaddr $fdtaddr" 573 574 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 575 576 #include <asm/fsl_secure_boot.h> 577 578 #endif /* __CONFIG_H */ 579