1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_SPIFLASH 15 #define CONFIG_RAMBOOT_SPIFLASH 16 #define CONFIG_SYS_TEXT_BASE 0x11000000 17 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 18 #endif 19 20 #ifdef CONFIG_NAND 21 #ifdef CONFIG_TPL_BUILD 22 #define CONFIG_SPL_NAND_BOOT 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_NAND_INIT 25 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT 26 #define CONFIG_SPL_COMMON_INIT_DDR 27 #define CONFIG_SPL_MAX_SIZE (128 << 10) 28 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 30 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 31 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 32 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 33 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 34 #elif defined(CONFIG_SPL_BUILD) 35 #define CONFIG_SPL_INIT_MINIMAL 36 #define CONFIG_SPL_NAND_MINIMAL 37 #define CONFIG_SPL_FLUSH_IMAGE 38 #define CONFIG_SPL_TEXT_BASE 0xff800000 39 #define CONFIG_SPL_MAX_SIZE 8192 40 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 41 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 42 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 43 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 44 #endif 45 #define CONFIG_SPL_PAD_TO 0x20000 46 #define CONFIG_TPL_PAD_TO 0x20000 47 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 48 #define CONFIG_SYS_TEXT_BASE 0x11001000 49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 50 #endif 51 52 #ifndef CONFIG_SYS_TEXT_BASE 53 #define CONFIG_SYS_TEXT_BASE 0xeff40000 54 #endif 55 56 #ifndef CONFIG_RESET_VECTOR_ADDRESS 57 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 58 #endif 59 60 #ifdef CONFIG_SPL_BUILD 61 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 62 #else 63 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 64 #endif 65 66 #ifdef CONFIG_SPL_BUILD 67 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 68 #endif 69 70 /* High Level Configuration Options */ 71 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 72 73 #ifdef CONFIG_PCI 74 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 75 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 76 #define CONFIG_PCI_INDIRECT_BRIDGE 77 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 78 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 79 80 /* 81 * PCI Windows 82 * Memory space is mapped 1-1, but I/O space must start from 0. 83 */ 84 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 85 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 86 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 87 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 88 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 89 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 90 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 91 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 92 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 93 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 94 95 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 96 #endif 97 98 #define CONFIG_TSEC_ENET 99 #define CONFIG_ENV_OVERWRITE 100 101 #define CONFIG_DDR_CLK_FREQ 100000000 102 #define CONFIG_SYS_CLK_FREQ 66666666 103 104 #define CONFIG_HWCONFIG 105 106 /* 107 * These can be toggled for performance analysis, otherwise use default. 108 */ 109 #define CONFIG_L2_CACHE /* toggle L2 cache */ 110 #define CONFIG_BTB /* toggle branch predition */ 111 112 113 #define CONFIG_ENABLE_36BIT_PHYS 114 115 #define CONFIG_ADDR_MAP 1 116 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 117 118 #define CONFIG_SYS_MEMTEST_START 0x00200000 119 #define CONFIG_SYS_MEMTEST_END 0x00400000 120 #define CONFIG_PANIC_HANG 121 122 /* DDR Setup */ 123 #define CONFIG_DDR_SPD 124 #define CONFIG_SYS_SPD_BUS_NUM 0 125 #define SPD_EEPROM_ADDRESS 0x50 126 #define CONFIG_SYS_DDR_RAW_TIMING 127 128 /* DDR ECC Setup*/ 129 #define CONFIG_DDR_ECC 130 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 131 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 132 133 #define CONFIG_SYS_SDRAM_SIZE 512 134 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 135 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 136 137 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 138 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 139 140 #define CONFIG_SYS_CCSRBAR 0xffe00000 141 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 142 143 /* Platform SRAM setting */ 144 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 145 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 146 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 147 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 148 149 /* 150 * IFC Definitions 151 */ 152 /* NOR Flash on IFC */ 153 #define CONFIG_SYS_FLASH_BASE 0xec000000 154 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 155 156 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 157 158 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 159 #define CONFIG_SYS_MAX_FLASH_BANKS 1 160 161 #define CONFIG_SYS_FLASH_QUIET_TEST 162 #define CONFIG_FLASH_SHOW_PROGRESS 45 163 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 164 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 165 166 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 167 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 168 CSPR_PORT_SIZE_16 | \ 169 CSPR_MSEL_NOR | \ 170 CSPR_V) 171 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 172 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 173 174 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 175 FTIM0_NOR_TEADC(0x5) | \ 176 FTIM0_NOR_TEAHC(0x5)) 177 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 178 FTIM1_NOR_TRAD_NOR(0x1A) |\ 179 FTIM1_NOR_TSEQRAD_NOR(0x13)) 180 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 181 FTIM2_NOR_TCH(0x4) | \ 182 FTIM2_NOR_TWPH(0x0E) | \ 183 FTIM2_NOR_TWP(0x1c)) 184 #define CONFIG_SYS_NOR_FTIM3 0x0 185 186 /* CFI for NOR Flash */ 187 #define CONFIG_FLASH_CFI_DRIVER 188 #define CONFIG_SYS_FLASH_CFI 189 #define CONFIG_SYS_FLASH_EMPTY_INFO 190 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 191 192 /* NAND Flash on IFC */ 193 #define CONFIG_NAND_FSL_IFC 194 #define CONFIG_SYS_NAND_BASE 0xff800000 195 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 196 197 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 198 199 #define CONFIG_SYS_MAX_NAND_DEVICE 1 200 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 201 202 /* 8Bit NAND Flash - K9F1G08U0B */ 203 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 204 | CSPR_PORT_SIZE_8 \ 205 | CSPR_MSEL_NAND \ 206 | CSPR_V) 207 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 208 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 209 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 210 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 211 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 212 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 213 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 214 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 215 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 216 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 217 FTIM0_NAND_TWP(0x0c) | \ 218 FTIM0_NAND_TWCHT(0x08) | \ 219 FTIM0_NAND_TWH(0x06)) 220 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 221 FTIM1_NAND_TWBE(0x1d) | \ 222 FTIM1_NAND_TRR(0x08) | \ 223 FTIM1_NAND_TRP(0x0c)) 224 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 225 FTIM2_NAND_TREH(0x0a) | \ 226 FTIM2_NAND_TWHRE(0x18)) 227 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 228 229 #define CONFIG_SYS_NAND_DDR_LAW 11 230 231 /* Set up IFC registers for boot location NOR/NAND */ 232 #ifdef CONFIG_NAND 233 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 234 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 235 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 236 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 237 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 238 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 239 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 240 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 241 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 242 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 243 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 244 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 245 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 246 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 247 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 248 #else 249 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 250 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 251 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 252 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 253 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 254 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 255 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 256 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 257 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 258 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 259 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 260 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 261 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 262 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 263 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 264 #endif 265 266 /* CPLD on IFC, selected by CS2 */ 267 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 268 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 269 | CONFIG_SYS_CPLD_BASE) 270 271 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 272 | CSPR_PORT_SIZE_8 \ 273 | CSPR_MSEL_GPCM \ 274 | CSPR_V) 275 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 276 #define CONFIG_SYS_CSOR2 0x0 277 /* CPLD Timing parameters for IFC CS2 */ 278 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 279 FTIM0_GPCM_TEADC(0x0e) | \ 280 FTIM0_GPCM_TEAHC(0x0e)) 281 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 282 FTIM1_GPCM_TRAD(0x1f)) 283 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 284 FTIM2_GPCM_TCH(0x8) | \ 285 FTIM2_GPCM_TWP(0x1f)) 286 #define CONFIG_SYS_CS2_FTIM3 0x0 287 288 #if defined(CONFIG_RAMBOOT_SPIFLASH) 289 #define CONFIG_SYS_RAMBOOT 290 #define CONFIG_SYS_EXTRA_ENV_RELOC 291 #endif 292 293 #define CONFIG_BOARD_EARLY_INIT_R 294 295 #define CONFIG_SYS_INIT_RAM_LOCK 296 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 297 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 298 299 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 300 - GENERATED_GBL_DATA_SIZE) 301 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 302 303 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 304 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 305 306 /* 307 * Config the L2 Cache as L2 SRAM 308 */ 309 #if defined(CONFIG_SPL_BUILD) 310 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 311 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 312 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 313 #define CONFIG_SYS_L2_SIZE (256 << 10) 314 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 315 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 316 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 317 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 318 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 319 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 320 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 321 #elif defined(CONFIG_NAND) 322 #ifdef CONFIG_TPL_BUILD 323 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 324 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 325 #define CONFIG_SYS_L2_SIZE (256 << 10) 326 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 327 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 328 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 329 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 330 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 331 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 332 #else 333 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 334 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 335 #define CONFIG_SYS_L2_SIZE (256 << 10) 336 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 337 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 338 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 339 #endif 340 #endif 341 #endif 342 343 /* Serial Port */ 344 #define CONFIG_CONS_INDEX 1 345 #define CONFIG_SYS_NS16550_SERIAL 346 #define CONFIG_SYS_NS16550_REG_SIZE 1 347 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 348 349 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 350 #define CONFIG_NS16550_MIN_FUNCTIONS 351 #endif 352 353 #define CONFIG_SYS_BAUDRATE_TABLE \ 354 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 355 356 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 357 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 358 359 #define CONFIG_SYS_I2C 360 #define CONFIG_SYS_I2C_FSL 361 #define CONFIG_SYS_FSL_I2C_SPEED 400000 362 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 363 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 364 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 365 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 366 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 367 368 /* I2C EEPROM */ 369 /* enable read and write access to EEPROM */ 370 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 371 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 372 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 373 374 /* eSPI - Enhanced SPI */ 375 #define CONFIG_SF_DEFAULT_SPEED 10000000 376 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 377 378 #ifdef CONFIG_TSEC_ENET 379 #define CONFIG_MII /* MII PHY management */ 380 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 381 #define CONFIG_TSEC1 1 382 #define CONFIG_TSEC1_NAME "eTSEC1" 383 #define CONFIG_TSEC2 1 384 #define CONFIG_TSEC2_NAME "eTSEC2" 385 386 /* Default mode is RGMII mode */ 387 #define TSEC1_PHY_ADDR 0 388 #define TSEC2_PHY_ADDR 2 389 390 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 391 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 392 393 #define CONFIG_ETHPRIME "eTSEC1" 394 #endif /* CONFIG_TSEC_ENET */ 395 396 /* 397 * Environment 398 */ 399 #if defined(CONFIG_SYS_RAMBOOT) 400 #if defined(CONFIG_RAMBOOT_SPIFLASH) 401 #define CONFIG_ENV_SPI_BUS 0 402 #define CONFIG_ENV_SPI_CS 0 403 #define CONFIG_ENV_SPI_MAX_HZ 10000000 404 #define CONFIG_ENV_SPI_MODE 0 405 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 406 #define CONFIG_ENV_SECT_SIZE 0x10000 407 #define CONFIG_ENV_SIZE 0x2000 408 #endif 409 #elif defined(CONFIG_NAND) 410 #ifdef CONFIG_TPL_BUILD 411 #define CONFIG_ENV_SIZE 0x2000 412 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 413 #else 414 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 415 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 416 #endif 417 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE 418 #else 419 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 420 #define CONFIG_ENV_SIZE 0x2000 421 #define CONFIG_ENV_SECT_SIZE 0x20000 422 #endif 423 424 #define CONFIG_LOADS_ECHO 425 #define CONFIG_SYS_LOADS_BAUD_CHANGE 426 427 /* 428 * Miscellaneous configurable options 429 */ 430 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 431 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 432 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 433 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 434 435 /* 436 * For booting Linux, the board info and command line data 437 * have to be in the first 64 MB of memory, since this is 438 * the maximum mapped by the Linux kernel during initialization. 439 */ 440 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 441 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 442 443 /* 444 * Environment Configuration 445 */ 446 447 #ifdef CONFIG_TSEC_ENET 448 #define CONFIG_HAS_ETH0 449 #define CONFIG_HAS_ETH1 450 #endif 451 452 #define CONFIG_ROOTPATH "/opt/nfsroot" 453 #define CONFIG_BOOTFILE "uImage" 454 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 455 456 /* default location for tftp and bootm */ 457 #define CONFIG_LOADADDR 1000000 458 459 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 460 461 #define CONFIG_EXTRA_ENV_SETTINGS \ 462 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 463 "netdev=eth0\0" \ 464 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 465 "loadaddr=1000000\0" \ 466 "consoledev=ttyS0\0" \ 467 "ramdiskaddr=2000000\0" \ 468 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 469 "fdtaddr=1e00000\0" \ 470 "fdtfile=name/of/device-tree.dtb\0" \ 471 "othbootargs=ramdisk_size=600000\0" \ 472 473 #define CONFIG_RAMBOOTCOMMAND \ 474 "setenv bootargs root=/dev/ram rw " \ 475 "console=$consoledev,$baudrate $othbootargs; " \ 476 "tftp $ramdiskaddr $ramdiskfile;" \ 477 "tftp $loadaddr $bootfile;" \ 478 "tftp $fdtaddr $fdtfile;" \ 479 "bootm $loadaddr $ramdiskaddr $fdtaddr" 480 481 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 482 483 #include <asm/fsl_secure_boot.h> 484 485 #endif /* __CONFIG_H */ 486