1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9132 QDS board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_MISC_INIT_R 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 18 #define CONFIG_SYS_RAMBOOT 19 #define CONFIG_SYS_EXTRA_ENV_RELOC 20 #define CONFIG_SYS_TEXT_BASE 0x11000000 21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 22 #endif 23 #ifdef CONFIG_SPIFLASH 24 #define CONFIG_RAMBOOT_SPIFLASH 25 #define CONFIG_SYS_RAMBOOT 26 #define CONFIG_SYS_EXTRA_ENV_RELOC 27 #define CONFIG_SYS_TEXT_BASE 0x11000000 28 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 29 #endif 30 #ifdef CONFIG_NAND_SECBOOT 31 #define CONFIG_RAMBOOT_NAND 32 #define CONFIG_SYS_RAMBOOT 33 #define CONFIG_SYS_EXTRA_ENV_RELOC 34 #define CONFIG_SYS_TEXT_BASE 0x11000000 35 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 36 #endif 37 38 #ifdef CONFIG_NAND 39 #define CONFIG_SPL_INIT_MINIMAL 40 #define CONFIG_SPL_NAND_BOOT 41 #define CONFIG_SPL_FLUSH_IMAGE 42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 43 44 #define CONFIG_SYS_TEXT_BASE 0x00201000 45 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 46 #define CONFIG_SPL_MAX_SIZE 8192 47 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 48 #define CONFIG_SPL_RELOC_STACK 0x00100000 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 50 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 51 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 52 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #endif 55 56 #ifndef CONFIG_SYS_TEXT_BASE 57 #define CONFIG_SYS_TEXT_BASE 0x8ff40000 58 #endif 59 60 #ifndef CONFIG_RESET_VECTOR_ADDRESS 61 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 62 #endif 63 64 #ifdef CONFIG_SPL_BUILD 65 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 66 #else 67 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 68 #endif 69 70 /* High Level Configuration Options */ 71 #define CONFIG_FSL_IFC /* Enable IFC Support */ 72 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 73 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 74 75 #if defined(CONFIG_PCI) 76 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 77 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 78 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 79 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 80 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 81 82 #define CONFIG_CMD_PCI 83 84 /* 85 * PCI Windows 86 * Memory space is mapped 1-1, but I/O space must start from 0. 87 */ 88 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 89 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 90 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 91 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 92 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 93 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 94 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 95 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 96 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 97 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 98 99 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 100 #endif 101 102 #define CONFIG_ENV_OVERWRITE 103 #define CONFIG_TSEC_ENET /* ethernet */ 104 105 #if defined(CONFIG_SYS_CLK_100_DDR_100) 106 #define CONFIG_SYS_CLK_FREQ 100000000 107 #define CONFIG_DDR_CLK_FREQ 100000000 108 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 109 #define CONFIG_SYS_CLK_FREQ 100000000 110 #define CONFIG_DDR_CLK_FREQ 133000000 111 #endif 112 113 #define CONFIG_MP 114 115 #define CONFIG_HWCONFIG 116 /* 117 * These can be toggled for performance analysis, otherwise use default. 118 */ 119 #define CONFIG_L2_CACHE /* toggle L2 cache */ 120 #define CONFIG_BTB /* enable branch predition */ 121 122 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 123 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 124 125 /* DDR Setup */ 126 #define CONFIG_SYS_SPD_BUS_NUM 0 127 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 128 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 129 #define CONFIG_FSL_DDR_INTERACTIVE 130 131 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 132 133 #define CONFIG_SYS_SDRAM_SIZE (1024) 134 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 135 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 136 137 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 138 139 /* DDR3 Controller Settings */ 140 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 141 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 142 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 143 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 144 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 145 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 146 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 147 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 148 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 149 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 150 151 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 152 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 153 #define CONFIG_SYS_DDR_RCW_1 0x00000000 154 #define CONFIG_SYS_DDR_RCW_2 0x00000000 155 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 156 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 157 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 158 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 159 160 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 161 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 162 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 163 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 164 165 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 166 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 167 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 168 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 169 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 170 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 171 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 172 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 173 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 174 175 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 176 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 177 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 178 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 179 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 180 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 181 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 182 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 183 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 184 185 /*FIXME: the following params are constant w.r.t diff freq 186 combinations. this should be removed later 187 */ 188 #if CONFIG_DDR_CLK_FREQ == 100000000 189 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 190 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 191 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 192 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 193 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 194 #elif CONFIG_DDR_CLK_FREQ == 133000000 195 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 196 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 197 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 198 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 199 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 200 #else 201 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 202 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 203 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 204 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 205 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 206 #endif 207 208 /* relocated CCSRBAR */ 209 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 210 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 211 212 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 213 214 /* DSP CCSRBAR */ 215 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 216 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 217 218 /* 219 * IFC Definitions 220 */ 221 /* NOR Flash on IFC */ 222 223 #ifdef CONFIG_SPL_BUILD 224 #define CONFIG_SYS_NO_FLASH 225 #endif 226 #define CONFIG_SYS_FLASH_BASE 0x88000000 227 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 228 229 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 230 231 #define CONFIG_SYS_NOR_CSPR 0x88000101 232 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 233 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 234 /* NOR Flash Timing Params */ 235 236 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 237 | FTIM0_NOR_TEADC(0x03) \ 238 | FTIM0_NOR_TAVDS(0x00) \ 239 | FTIM0_NOR_TEAHC(0x0f)) 240 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 241 | FTIM1_NOR_TRAD_NOR(0x09) \ 242 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 243 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 244 | FTIM2_NOR_TCH(0x4) \ 245 | FTIM2_NOR_TWPH(0x7) \ 246 | FTIM2_NOR_TWP(0x1e)) 247 #define CONFIG_SYS_NOR_FTIM3 0x0 248 249 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 250 #define CONFIG_SYS_FLASH_QUIET_TEST 251 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 252 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 253 254 #undef CONFIG_SYS_FLASH_CHECKSUM 255 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 256 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 257 258 /* CFI for NOR Flash */ 259 #define CONFIG_FLASH_CFI_DRIVER 260 #define CONFIG_SYS_FLASH_CFI 261 #define CONFIG_SYS_FLASH_EMPTY_INFO 262 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 263 264 /* NAND Flash on IFC */ 265 #define CONFIG_SYS_NAND_BASE 0xff800000 266 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 267 268 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 269 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 270 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 271 | CSPR_V) 272 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 273 274 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 275 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 276 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 277 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 278 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 279 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 280 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 281 282 /* NAND Flash Timing Params */ 283 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 284 | FTIM0_NAND_TWP(0x05) \ 285 | FTIM0_NAND_TWCHT(0x02) \ 286 | FTIM0_NAND_TWH(0x04)) 287 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 288 | FTIM1_NAND_TWBE(0x1e) \ 289 | FTIM1_NAND_TRR(0x07) \ 290 | FTIM1_NAND_TRP(0x05)) 291 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 292 | FTIM2_NAND_TREH(0x04) \ 293 | FTIM2_NAND_TWHRE(0x11)) 294 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 295 296 #define CONFIG_SYS_NAND_DDR_LAW 11 297 298 /* NAND */ 299 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 300 #define CONFIG_SYS_MAX_NAND_DEVICE 1 301 #define CONFIG_CMD_NAND 302 303 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 304 305 #ifndef CONFIG_SPL_BUILD 306 #define CONFIG_FSL_QIXIS 307 #endif 308 #ifdef CONFIG_FSL_QIXIS 309 #define CONFIG_SYS_FPGA_BASE 0xffb00000 310 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 311 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 312 #define QIXIS_LBMAP_SWITCH 9 313 #define QIXIS_LBMAP_MASK 0x07 314 #define QIXIS_LBMAP_SHIFT 0 315 #define QIXIS_LBMAP_DFLTBANK 0x00 316 #define QIXIS_LBMAP_ALTBANK 0x04 317 #define QIXIS_RST_CTL_RESET 0x83 318 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 319 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 320 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 321 322 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 323 324 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 325 | CSPR_PORT_SIZE_8 \ 326 | CSPR_MSEL_GPCM \ 327 | CSPR_V) 328 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 329 #define CONFIG_SYS_CSOR2 0x0 330 /* CPLD Timing parameters for IFC CS3 */ 331 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 332 FTIM0_GPCM_TEADC(0x0e) | \ 333 FTIM0_GPCM_TEAHC(0x0e)) 334 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 335 FTIM1_GPCM_TRAD(0x1f)) 336 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 337 FTIM2_GPCM_TCH(0x8) | \ 338 FTIM2_GPCM_TWP(0x1f)) 339 #define CONFIG_SYS_CS2_FTIM3 0x0 340 #endif 341 342 /* Set up IFC registers for boot location NOR/NAND */ 343 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 344 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 345 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 346 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 347 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 348 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 349 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 350 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 351 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 352 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 353 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 354 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 355 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 356 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 357 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 358 #else 359 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 360 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 361 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 362 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 363 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 364 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 365 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 366 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 367 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 368 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 369 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 370 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 371 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 372 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 373 #endif 374 375 #define CONFIG_BOARD_EARLY_INIT_R 376 377 #define CONFIG_SYS_INIT_RAM_LOCK 378 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 379 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 380 381 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 382 - GENERATED_GBL_DATA_SIZE) 383 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 384 385 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 386 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 387 388 /* Serial Port */ 389 #define CONFIG_CONS_INDEX 1 390 #undef CONFIG_SERIAL_SOFTWARE_FIFO 391 #define CONFIG_SYS_NS16550_SERIAL 392 #define CONFIG_SYS_NS16550_REG_SIZE 1 393 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 394 #ifdef CONFIG_SPL_BUILD 395 #define CONFIG_NS16550_MIN_FUNCTIONS 396 #endif 397 398 #define CONFIG_SYS_BAUDRATE_TABLE \ 399 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 400 401 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 402 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 403 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 404 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 405 406 #define CONFIG_SYS_I2C 407 #define CONFIG_SYS_I2C_FSL 408 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 409 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 410 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 411 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 412 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 413 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 414 415 /* I2C EEPROM */ 416 #define CONFIG_ID_EEPROM 417 #ifdef CONFIG_ID_EEPROM 418 #define CONFIG_SYS_I2C_EEPROM_NXID 419 #endif 420 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 421 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 422 #define CONFIG_SYS_EEPROM_BUS_NUM 0 423 424 /* enable read and write access to EEPROM */ 425 #define CONFIG_CMD_EEPROM 426 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 427 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 428 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 429 430 /* I2C FPGA */ 431 #define CONFIG_I2C_FPGA 432 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 433 434 #define CONFIG_RTC_DS3231 435 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 436 437 /* 438 * SPI interface will not be available in case of NAND boot SPI CS0 will be 439 * used for SLIC 440 */ 441 /* eSPI - Enhanced SPI */ 442 #ifdef CONFIG_FSL_ESPI 443 #define CONFIG_SF_DEFAULT_SPEED 10000000 444 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 445 #endif 446 447 #if defined(CONFIG_TSEC_ENET) 448 449 #define CONFIG_MII /* MII PHY management */ 450 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 451 #define CONFIG_TSEC1 1 452 #define CONFIG_TSEC1_NAME "eTSEC1" 453 #define CONFIG_TSEC2 1 454 #define CONFIG_TSEC2_NAME "eTSEC2" 455 456 #define TSEC1_PHY_ADDR 0 457 #define TSEC2_PHY_ADDR 1 458 459 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 460 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 461 462 #define TSEC1_PHYIDX 0 463 #define TSEC2_PHYIDX 0 464 465 #define CONFIG_ETHPRIME "eTSEC1" 466 467 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 468 469 /* TBI PHY configuration for SGMII mode */ 470 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 471 TBICR_PHY_RESET \ 472 | TBICR_ANEG_ENABLE \ 473 | TBICR_FULL_DUPLEX \ 474 | TBICR_SPEED1_SET \ 475 ) 476 477 #endif /* CONFIG_TSEC_ENET */ 478 479 #ifdef CONFIG_MMC 480 #define CONFIG_FSL_ESDHC 481 #define CONFIG_GENERIC_MMC 482 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 483 #endif 484 485 #define CONFIG_USB_EHCI /* USB */ 486 #ifdef CONFIG_USB_EHCI 487 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 488 #define CONFIG_USB_EHCI_FSL 489 #define CONFIG_HAS_FSL_DR_USB 490 #endif 491 492 /* 493 * Environment 494 */ 495 #if defined(CONFIG_RAMBOOT_SDCARD) 496 #define CONFIG_ENV_IS_IN_MMC 497 #define CONFIG_FSL_FIXED_MMC_LOCATION 498 #define CONFIG_SYS_MMC_ENV_DEV 0 499 #define CONFIG_ENV_SIZE 0x2000 500 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 501 #define CONFIG_ENV_IS_IN_SPI_FLASH 502 #define CONFIG_ENV_SPI_BUS 0 503 #define CONFIG_ENV_SPI_CS 0 504 #define CONFIG_ENV_SPI_MAX_HZ 10000000 505 #define CONFIG_ENV_SPI_MODE 0 506 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 507 #define CONFIG_ENV_SECT_SIZE 0x10000 508 #define CONFIG_ENV_SIZE 0x2000 509 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 510 #define CONFIG_ENV_IS_IN_NAND 511 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 512 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 513 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 514 #elif defined(CONFIG_SYS_RAMBOOT) 515 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 516 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 517 #define CONFIG_ENV_SIZE 0x2000 518 #else 519 #define CONFIG_ENV_IS_IN_FLASH 520 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 521 #define CONFIG_ENV_SIZE 0x2000 522 #define CONFIG_ENV_SECT_SIZE 0x20000 523 #endif 524 525 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 526 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 527 528 /* 529 * Command line configuration. 530 */ 531 #define CONFIG_CMD_DATE 532 #define CONFIG_CMD_ERRATA 533 #define CONFIG_CMD_IRQ 534 #define CONFIG_CMD_REGINFO 535 536 /* Hash command with SHA acceleration supported in hardware */ 537 #ifdef CONFIG_FSL_CAAM 538 #define CONFIG_CMD_HASH 539 #define CONFIG_SHA_HW_ACCEL 540 #endif 541 542 /* 543 * Miscellaneous configurable options 544 */ 545 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 546 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 547 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 548 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 549 550 #if defined(CONFIG_CMD_KGDB) 551 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 552 #else 553 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 554 #endif 555 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 556 /* Print Buffer Size */ 557 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 558 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 559 560 /* 561 * For booting Linux, the board info and command line data 562 * have to be in the first 64 MB of memory, since this is 563 * the maximum mapped by the Linux kernel during initialization. 564 */ 565 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 566 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 567 568 #if defined(CONFIG_CMD_KGDB) 569 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 570 #endif 571 572 /* 573 * Dynamic MTD Partition support with mtdparts 574 */ 575 #ifndef CONFIG_SYS_NO_FLASH 576 #define CONFIG_MTD_DEVICE 577 #define CONFIG_MTD_PARTITIONS 578 #define CONFIG_CMD_MTDPARTS 579 #define CONFIG_FLASH_CFI_MTD 580 #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," 581 #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ 582 "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ 583 "8m(kernel),512k(dtb),-(fs)" 584 #endif 585 /* 586 * Environment Configuration 587 */ 588 589 #if defined(CONFIG_TSEC_ENET) 590 #define CONFIG_HAS_ETH0 591 #define CONFIG_HAS_ETH1 592 #endif 593 594 #define CONFIG_HOSTNAME BSC9132qds 595 #define CONFIG_ROOTPATH "/opt/nfsroot" 596 #define CONFIG_BOOTFILE "uImage" 597 #define CONFIG_UBOOTPATH "u-boot.bin" 598 599 #define CONFIG_BAUDRATE 115200 600 601 #ifdef CONFIG_SDCARD 602 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 603 #else 604 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 605 #endif 606 607 #define CONFIG_EXTRA_ENV_SETTINGS \ 608 "netdev=eth0\0" \ 609 "uboot=" CONFIG_UBOOTPATH "\0" \ 610 "loadaddr=1000000\0" \ 611 "bootfile=uImage\0" \ 612 "consoledev=ttyS0\0" \ 613 "ramdiskaddr=2000000\0" \ 614 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 615 "fdtaddr=1e00000\0" \ 616 "fdtfile=bsc9132qds.dtb\0" \ 617 "bdev=sda1\0" \ 618 CONFIG_DEF_HWCONFIG\ 619 "othbootargs=mem=880M ramdisk_size=600000 " \ 620 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 621 "isolcpus=0\0" \ 622 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 623 "console=$consoledev,$baudrate $othbootargs; " \ 624 "usb start;" \ 625 "ext2load usb 0:4 $loadaddr $bootfile;" \ 626 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 627 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 628 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 629 "debug_halt_off=mw ff7e0e30 0xf0000000;" 630 631 #define CONFIG_NFSBOOTCOMMAND \ 632 "setenv bootargs root=/dev/nfs rw " \ 633 "nfsroot=$serverip:$rootpath " \ 634 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 635 "console=$consoledev,$baudrate $othbootargs;" \ 636 "tftp $loadaddr $bootfile;" \ 637 "tftp $fdtaddr $fdtfile;" \ 638 "bootm $loadaddr - $fdtaddr" 639 640 #define CONFIG_HDBOOT \ 641 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 642 "console=$consoledev,$baudrate $othbootargs;" \ 643 "usb start;" \ 644 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 645 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 646 "bootm $loadaddr - $fdtaddr" 647 648 #define CONFIG_RAMBOOTCOMMAND \ 649 "setenv bootargs root=/dev/ram rw " \ 650 "console=$consoledev,$baudrate $othbootargs; " \ 651 "tftp $ramdiskaddr $ramdiskfile;" \ 652 "tftp $loadaddr $bootfile;" \ 653 "tftp $fdtaddr $fdtfile;" \ 654 "bootm $loadaddr $ramdiskaddr $fdtaddr" 655 656 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 657 658 #include <asm/fsl_secure_boot.h> 659 660 #endif /* __CONFIG_H */ 661