1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9132 QDS board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_MISC_INIT_R 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 18 #define CONFIG_SYS_RAMBOOT 19 #define CONFIG_SYS_EXTRA_ENV_RELOC 20 #define CONFIG_SYS_TEXT_BASE 0x11000000 21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 22 #endif 23 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 24 #ifdef CONFIG_SPIFLASH 25 #define CONFIG_RAMBOOT_SPIFLASH 26 #define CONFIG_SYS_RAMBOOT 27 #define CONFIG_SYS_EXTRA_ENV_RELOC 28 #define CONFIG_SYS_TEXT_BASE 0x11000000 29 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 30 #endif 31 #ifdef CONFIG_NAND_SECBOOT 32 #define CONFIG_RAMBOOT_NAND 33 #define CONFIG_SYS_RAMBOOT 34 #define CONFIG_SYS_EXTRA_ENV_RELOC 35 #define CONFIG_SYS_TEXT_BASE 0x11000000 36 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 37 #endif 38 39 #ifdef CONFIG_NAND 40 #define CONFIG_SPL_INIT_MINIMAL 41 #define CONFIG_SPL_NAND_BOOT 42 #define CONFIG_SPL_FLUSH_IMAGE 43 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 44 45 #define CONFIG_SYS_TEXT_BASE 0x00201000 46 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 47 #define CONFIG_SPL_MAX_SIZE 8192 48 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 49 #define CONFIG_SPL_RELOC_STACK 0x00100000 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 51 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 55 #endif 56 57 #ifndef CONFIG_SYS_TEXT_BASE 58 #define CONFIG_SYS_TEXT_BASE 0x8ff40000 59 #endif 60 61 #ifndef CONFIG_RESET_VECTOR_ADDRESS 62 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 63 #endif 64 65 #ifdef CONFIG_SPL_BUILD 66 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 67 #else 68 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 69 #endif 70 71 /* High Level Configuration Options */ 72 #define CONFIG_FSL_IFC /* Enable IFC Support */ 73 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 74 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 75 76 #if defined(CONFIG_PCI) 77 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 78 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 79 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 80 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 81 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 82 83 #define CONFIG_CMD_PCI 84 85 /* 86 * PCI Windows 87 * Memory space is mapped 1-1, but I/O space must start from 0. 88 */ 89 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 90 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 91 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 92 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 93 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 94 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 95 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 96 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 97 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 98 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 99 100 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 101 #define CONFIG_DOS_PARTITION 102 #endif 103 104 #define CONFIG_ENV_OVERWRITE 105 #define CONFIG_TSEC_ENET /* ethernet */ 106 107 #if defined(CONFIG_SYS_CLK_100_DDR_100) 108 #define CONFIG_SYS_CLK_FREQ 100000000 109 #define CONFIG_DDR_CLK_FREQ 100000000 110 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 111 #define CONFIG_SYS_CLK_FREQ 100000000 112 #define CONFIG_DDR_CLK_FREQ 133000000 113 #endif 114 115 #define CONFIG_MP 116 117 #define CONFIG_HWCONFIG 118 /* 119 * These can be toggled for performance analysis, otherwise use default. 120 */ 121 #define CONFIG_L2_CACHE /* toggle L2 cache */ 122 #define CONFIG_BTB /* enable branch predition */ 123 124 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 125 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 126 127 /* DDR Setup */ 128 #define CONFIG_SYS_SPD_BUS_NUM 0 129 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 130 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 131 #define CONFIG_FSL_DDR_INTERACTIVE 132 133 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 134 135 #define CONFIG_SYS_SDRAM_SIZE (1024) 136 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 137 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 138 139 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 140 141 /* DDR3 Controller Settings */ 142 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 143 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 144 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 145 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 146 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 147 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 148 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 149 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 150 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 151 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 152 153 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 154 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 155 #define CONFIG_SYS_DDR_RCW_1 0x00000000 156 #define CONFIG_SYS_DDR_RCW_2 0x00000000 157 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 158 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 159 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 160 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 161 162 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 163 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 164 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 165 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 166 167 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 168 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 169 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 170 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 171 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 172 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 173 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 174 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 175 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 176 177 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 178 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 179 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 180 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 181 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 182 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 183 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 184 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 185 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 186 187 /*FIXME: the following params are constant w.r.t diff freq 188 combinations. this should be removed later 189 */ 190 #if CONFIG_DDR_CLK_FREQ == 100000000 191 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 192 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 193 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 194 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 195 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 196 #elif CONFIG_DDR_CLK_FREQ == 133000000 197 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 198 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 199 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 200 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 201 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 202 #else 203 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 204 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 205 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 206 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 207 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 208 #endif 209 210 /* relocated CCSRBAR */ 211 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 212 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 213 214 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 215 216 /* DSP CCSRBAR */ 217 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 218 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 219 220 /* 221 * IFC Definitions 222 */ 223 /* NOR Flash on IFC */ 224 225 #ifdef CONFIG_SPL_BUILD 226 #define CONFIG_SYS_NO_FLASH 227 #endif 228 #define CONFIG_SYS_FLASH_BASE 0x88000000 229 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 230 231 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 232 233 #define CONFIG_SYS_NOR_CSPR 0x88000101 234 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 235 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 236 /* NOR Flash Timing Params */ 237 238 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 239 | FTIM0_NOR_TEADC(0x03) \ 240 | FTIM0_NOR_TAVDS(0x00) \ 241 | FTIM0_NOR_TEAHC(0x0f)) 242 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 243 | FTIM1_NOR_TRAD_NOR(0x09) \ 244 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 245 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 246 | FTIM2_NOR_TCH(0x4) \ 247 | FTIM2_NOR_TWPH(0x7) \ 248 | FTIM2_NOR_TWP(0x1e)) 249 #define CONFIG_SYS_NOR_FTIM3 0x0 250 251 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 252 #define CONFIG_SYS_FLASH_QUIET_TEST 253 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 254 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 255 256 #undef CONFIG_SYS_FLASH_CHECKSUM 257 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 258 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 259 260 /* CFI for NOR Flash */ 261 #define CONFIG_FLASH_CFI_DRIVER 262 #define CONFIG_SYS_FLASH_CFI 263 #define CONFIG_SYS_FLASH_EMPTY_INFO 264 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 265 266 /* NAND Flash on IFC */ 267 #define CONFIG_SYS_NAND_BASE 0xff800000 268 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 269 270 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 271 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 272 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 273 | CSPR_V) 274 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 275 276 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 277 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 278 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 279 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 280 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 281 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 282 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 283 284 /* NAND Flash Timing Params */ 285 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 286 | FTIM0_NAND_TWP(0x05) \ 287 | FTIM0_NAND_TWCHT(0x02) \ 288 | FTIM0_NAND_TWH(0x04)) 289 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 290 | FTIM1_NAND_TWBE(0x1e) \ 291 | FTIM1_NAND_TRR(0x07) \ 292 | FTIM1_NAND_TRP(0x05)) 293 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 294 | FTIM2_NAND_TREH(0x04) \ 295 | FTIM2_NAND_TWHRE(0x11)) 296 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 297 298 #define CONFIG_SYS_NAND_DDR_LAW 11 299 300 /* NAND */ 301 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 302 #define CONFIG_SYS_MAX_NAND_DEVICE 1 303 #define CONFIG_CMD_NAND 304 305 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 306 307 #ifndef CONFIG_SPL_BUILD 308 #define CONFIG_FSL_QIXIS 309 #endif 310 #ifdef CONFIG_FSL_QIXIS 311 #define CONFIG_SYS_FPGA_BASE 0xffb00000 312 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 313 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 314 #define QIXIS_LBMAP_SWITCH 9 315 #define QIXIS_LBMAP_MASK 0x07 316 #define QIXIS_LBMAP_SHIFT 0 317 #define QIXIS_LBMAP_DFLTBANK 0x00 318 #define QIXIS_LBMAP_ALTBANK 0x04 319 #define QIXIS_RST_CTL_RESET 0x83 320 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 321 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 322 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 323 324 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 325 326 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 327 | CSPR_PORT_SIZE_8 \ 328 | CSPR_MSEL_GPCM \ 329 | CSPR_V) 330 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 331 #define CONFIG_SYS_CSOR2 0x0 332 /* CPLD Timing parameters for IFC CS3 */ 333 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 334 FTIM0_GPCM_TEADC(0x0e) | \ 335 FTIM0_GPCM_TEAHC(0x0e)) 336 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 337 FTIM1_GPCM_TRAD(0x1f)) 338 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 339 FTIM2_GPCM_TCH(0x8) | \ 340 FTIM2_GPCM_TWP(0x1f)) 341 #define CONFIG_SYS_CS2_FTIM3 0x0 342 #endif 343 344 /* Set up IFC registers for boot location NOR/NAND */ 345 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 346 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 347 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 348 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 349 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 350 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 351 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 352 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 353 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 354 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 355 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 356 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 357 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 358 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 359 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 360 #else 361 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 362 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 363 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 364 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 365 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 366 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 367 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 368 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 369 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 370 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 371 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 372 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 373 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 374 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 375 #endif 376 377 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 378 #define CONFIG_BOARD_EARLY_INIT_R 379 380 #define CONFIG_SYS_INIT_RAM_LOCK 381 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 382 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 383 384 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 385 - GENERATED_GBL_DATA_SIZE) 386 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 387 388 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 389 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 390 391 /* Serial Port */ 392 #define CONFIG_CONS_INDEX 1 393 #undef CONFIG_SERIAL_SOFTWARE_FIFO 394 #define CONFIG_SYS_NS16550_SERIAL 395 #define CONFIG_SYS_NS16550_REG_SIZE 1 396 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 397 #ifdef CONFIG_SPL_BUILD 398 #define CONFIG_NS16550_MIN_FUNCTIONS 399 #endif 400 401 #define CONFIG_SYS_BAUDRATE_TABLE \ 402 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 403 404 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 405 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 406 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 407 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 408 409 #define CONFIG_SYS_I2C 410 #define CONFIG_SYS_I2C_FSL 411 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 412 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 413 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 414 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 415 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 416 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 417 418 /* I2C EEPROM */ 419 #define CONFIG_ID_EEPROM 420 #ifdef CONFIG_ID_EEPROM 421 #define CONFIG_SYS_I2C_EEPROM_NXID 422 #endif 423 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 424 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 425 #define CONFIG_SYS_EEPROM_BUS_NUM 0 426 427 /* enable read and write access to EEPROM */ 428 #define CONFIG_CMD_EEPROM 429 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 430 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 431 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 432 433 /* I2C FPGA */ 434 #define CONFIG_I2C_FPGA 435 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 436 437 #define CONFIG_RTC_DS3231 438 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 439 440 /* 441 * SPI interface will not be available in case of NAND boot SPI CS0 will be 442 * used for SLIC 443 */ 444 /* eSPI - Enhanced SPI */ 445 #ifdef CONFIG_FSL_ESPI 446 #define CONFIG_SF_DEFAULT_SPEED 10000000 447 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 448 #endif 449 450 #if defined(CONFIG_TSEC_ENET) 451 452 #define CONFIG_MII /* MII PHY management */ 453 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 454 #define CONFIG_TSEC1 1 455 #define CONFIG_TSEC1_NAME "eTSEC1" 456 #define CONFIG_TSEC2 1 457 #define CONFIG_TSEC2_NAME "eTSEC2" 458 459 #define TSEC1_PHY_ADDR 0 460 #define TSEC2_PHY_ADDR 1 461 462 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 463 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 464 465 #define TSEC1_PHYIDX 0 466 #define TSEC2_PHYIDX 0 467 468 #define CONFIG_ETHPRIME "eTSEC1" 469 470 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 471 472 /* TBI PHY configuration for SGMII mode */ 473 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 474 TBICR_PHY_RESET \ 475 | TBICR_ANEG_ENABLE \ 476 | TBICR_FULL_DUPLEX \ 477 | TBICR_SPEED1_SET \ 478 ) 479 480 #endif /* CONFIG_TSEC_ENET */ 481 482 #ifdef CONFIG_MMC 483 #define CONFIG_DOS_PARTITION 484 #define CONFIG_FSL_ESDHC 485 #define CONFIG_GENERIC_MMC 486 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 487 #endif 488 489 #define CONFIG_USB_EHCI /* USB */ 490 #ifdef CONFIG_USB_EHCI 491 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 492 #define CONFIG_USB_EHCI_FSL 493 #define CONFIG_HAS_FSL_DR_USB 494 #endif 495 496 /* 497 * Environment 498 */ 499 #if defined(CONFIG_RAMBOOT_SDCARD) 500 #define CONFIG_ENV_IS_IN_MMC 501 #define CONFIG_FSL_FIXED_MMC_LOCATION 502 #define CONFIG_SYS_MMC_ENV_DEV 0 503 #define CONFIG_ENV_SIZE 0x2000 504 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 505 #define CONFIG_ENV_IS_IN_SPI_FLASH 506 #define CONFIG_ENV_SPI_BUS 0 507 #define CONFIG_ENV_SPI_CS 0 508 #define CONFIG_ENV_SPI_MAX_HZ 10000000 509 #define CONFIG_ENV_SPI_MODE 0 510 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 511 #define CONFIG_ENV_SECT_SIZE 0x10000 512 #define CONFIG_ENV_SIZE 0x2000 513 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 514 #define CONFIG_ENV_IS_IN_NAND 515 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 516 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 517 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 518 #elif defined(CONFIG_SYS_RAMBOOT) 519 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 520 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 521 #define CONFIG_ENV_SIZE 0x2000 522 #else 523 #define CONFIG_ENV_IS_IN_FLASH 524 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 525 #define CONFIG_ENV_SIZE 0x2000 526 #define CONFIG_ENV_SECT_SIZE 0x20000 527 #endif 528 529 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 530 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 531 532 /* 533 * Command line configuration. 534 */ 535 #define CONFIG_CMD_DATE 536 #define CONFIG_CMD_ERRATA 537 #define CONFIG_CMD_IRQ 538 #define CONFIG_CMD_REGINFO 539 540 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 541 #define CONFIG_DOS_PARTITION 542 #endif 543 544 /* Hash command with SHA acceleration supported in hardware */ 545 #ifdef CONFIG_FSL_CAAM 546 #define CONFIG_CMD_HASH 547 #define CONFIG_SHA_HW_ACCEL 548 #endif 549 550 /* 551 * Miscellaneous configurable options 552 */ 553 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 554 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 555 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 556 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 557 558 #if defined(CONFIG_CMD_KGDB) 559 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 560 #else 561 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 562 #endif 563 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 564 /* Print Buffer Size */ 565 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 566 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 567 568 /* 569 * For booting Linux, the board info and command line data 570 * have to be in the first 64 MB of memory, since this is 571 * the maximum mapped by the Linux kernel during initialization. 572 */ 573 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 574 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 575 576 #if defined(CONFIG_CMD_KGDB) 577 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 578 #endif 579 580 /* 581 * Dynamic MTD Partition support with mtdparts 582 */ 583 #ifndef CONFIG_SYS_NO_FLASH 584 #define CONFIG_MTD_DEVICE 585 #define CONFIG_MTD_PARTITIONS 586 #define CONFIG_CMD_MTDPARTS 587 #define CONFIG_FLASH_CFI_MTD 588 #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," 589 #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ 590 "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ 591 "8m(kernel),512k(dtb),-(fs)" 592 #endif 593 /* 594 * Environment Configuration 595 */ 596 597 #if defined(CONFIG_TSEC_ENET) 598 #define CONFIG_HAS_ETH0 599 #define CONFIG_HAS_ETH1 600 #endif 601 602 #define CONFIG_HOSTNAME BSC9132qds 603 #define CONFIG_ROOTPATH "/opt/nfsroot" 604 #define CONFIG_BOOTFILE "uImage" 605 #define CONFIG_UBOOTPATH "u-boot.bin" 606 607 #define CONFIG_BAUDRATE 115200 608 609 #ifdef CONFIG_SDCARD 610 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 611 #else 612 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 613 #endif 614 615 #define CONFIG_EXTRA_ENV_SETTINGS \ 616 "netdev=eth0\0" \ 617 "uboot=" CONFIG_UBOOTPATH "\0" \ 618 "loadaddr=1000000\0" \ 619 "bootfile=uImage\0" \ 620 "consoledev=ttyS0\0" \ 621 "ramdiskaddr=2000000\0" \ 622 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 623 "fdtaddr=1e00000\0" \ 624 "fdtfile=bsc9132qds.dtb\0" \ 625 "bdev=sda1\0" \ 626 CONFIG_DEF_HWCONFIG\ 627 "othbootargs=mem=880M ramdisk_size=600000 " \ 628 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 629 "isolcpus=0\0" \ 630 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 631 "console=$consoledev,$baudrate $othbootargs; " \ 632 "usb start;" \ 633 "ext2load usb 0:4 $loadaddr $bootfile;" \ 634 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 635 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 636 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 637 "debug_halt_off=mw ff7e0e30 0xf0000000;" 638 639 #define CONFIG_NFSBOOTCOMMAND \ 640 "setenv bootargs root=/dev/nfs rw " \ 641 "nfsroot=$serverip:$rootpath " \ 642 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 643 "console=$consoledev,$baudrate $othbootargs;" \ 644 "tftp $loadaddr $bootfile;" \ 645 "tftp $fdtaddr $fdtfile;" \ 646 "bootm $loadaddr - $fdtaddr" 647 648 #define CONFIG_HDBOOT \ 649 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 650 "console=$consoledev,$baudrate $othbootargs;" \ 651 "usb start;" \ 652 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 653 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 654 "bootm $loadaddr - $fdtaddr" 655 656 #define CONFIG_RAMBOOTCOMMAND \ 657 "setenv bootargs root=/dev/ram rw " \ 658 "console=$consoledev,$baudrate $othbootargs; " \ 659 "tftp $ramdiskaddr $ramdiskfile;" \ 660 "tftp $loadaddr $bootfile;" \ 661 "tftp $fdtaddr $fdtfile;" \ 662 "bootm $loadaddr $ramdiskaddr $fdtaddr" 663 664 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 665 666 #include <asm/fsl_secure_boot.h> 667 668 #endif /* __CONFIG_H */ 669