1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9132 QDS board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_MISC_INIT_R 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 18 #define CONFIG_SYS_RAMBOOT 19 #define CONFIG_SYS_EXTRA_ENV_RELOC 20 #define CONFIG_SYS_TEXT_BASE 0x11000000 21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 22 #endif 23 #ifdef CONFIG_SPIFLASH 24 #define CONFIG_RAMBOOT_SPIFLASH 25 #define CONFIG_SYS_RAMBOOT 26 #define CONFIG_SYS_EXTRA_ENV_RELOC 27 #define CONFIG_SYS_TEXT_BASE 0x11000000 28 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 29 #endif 30 #ifdef CONFIG_NAND_SECBOOT 31 #define CONFIG_RAMBOOT_NAND 32 #define CONFIG_SYS_RAMBOOT 33 #define CONFIG_SYS_EXTRA_ENV_RELOC 34 #define CONFIG_SYS_TEXT_BASE 0x11000000 35 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 36 #endif 37 38 #ifdef CONFIG_NAND 39 #define CONFIG_SPL_INIT_MINIMAL 40 #define CONFIG_SPL_NAND_BOOT 41 #define CONFIG_SPL_FLUSH_IMAGE 42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 43 44 #define CONFIG_SYS_TEXT_BASE 0x00201000 45 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 46 #define CONFIG_SPL_MAX_SIZE 8192 47 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 48 #define CONFIG_SPL_RELOC_STACK 0x00100000 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 50 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 51 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 52 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #endif 55 56 #ifndef CONFIG_SYS_TEXT_BASE 57 #define CONFIG_SYS_TEXT_BASE 0x8ff40000 58 #endif 59 60 #ifndef CONFIG_RESET_VECTOR_ADDRESS 61 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 62 #endif 63 64 #ifdef CONFIG_SPL_BUILD 65 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 66 #else 67 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 68 #endif 69 70 /* High Level Configuration Options */ 71 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 72 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 73 74 #if defined(CONFIG_PCI) 75 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 76 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 77 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 78 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 79 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 80 81 #define CONFIG_CMD_PCI 82 83 /* 84 * PCI Windows 85 * Memory space is mapped 1-1, but I/O space must start from 0. 86 */ 87 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 88 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 89 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 90 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 91 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 92 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 93 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 94 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 95 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 96 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 97 98 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 99 #endif 100 101 #define CONFIG_ENV_OVERWRITE 102 #define CONFIG_TSEC_ENET /* ethernet */ 103 104 #if defined(CONFIG_SYS_CLK_100_DDR_100) 105 #define CONFIG_SYS_CLK_FREQ 100000000 106 #define CONFIG_DDR_CLK_FREQ 100000000 107 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 108 #define CONFIG_SYS_CLK_FREQ 100000000 109 #define CONFIG_DDR_CLK_FREQ 133000000 110 #endif 111 112 #define CONFIG_MP 113 114 #define CONFIG_HWCONFIG 115 /* 116 * These can be toggled for performance analysis, otherwise use default. 117 */ 118 #define CONFIG_L2_CACHE /* toggle L2 cache */ 119 #define CONFIG_BTB /* enable branch predition */ 120 121 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 122 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 123 124 /* DDR Setup */ 125 #define CONFIG_SYS_SPD_BUS_NUM 0 126 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 127 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 128 #define CONFIG_FSL_DDR_INTERACTIVE 129 130 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 131 132 #define CONFIG_SYS_SDRAM_SIZE (1024) 133 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 134 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 135 136 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 137 138 /* DDR3 Controller Settings */ 139 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 140 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 141 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 142 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 143 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 144 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 145 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 146 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 147 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 148 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 149 150 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 151 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 152 #define CONFIG_SYS_DDR_RCW_1 0x00000000 153 #define CONFIG_SYS_DDR_RCW_2 0x00000000 154 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 155 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 156 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 157 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 158 159 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 160 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 161 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 162 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 163 164 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 165 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 166 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 167 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 168 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 169 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 170 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 171 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 172 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 173 174 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 175 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 176 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 177 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 178 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 179 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 180 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 181 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 182 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 183 184 /*FIXME: the following params are constant w.r.t diff freq 185 combinations. this should be removed later 186 */ 187 #if CONFIG_DDR_CLK_FREQ == 100000000 188 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 189 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 190 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 191 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 192 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 193 #elif CONFIG_DDR_CLK_FREQ == 133000000 194 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 195 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 196 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 197 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 198 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 199 #else 200 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 201 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 202 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 203 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 204 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 205 #endif 206 207 /* relocated CCSRBAR */ 208 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 209 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 210 211 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 212 213 /* DSP CCSRBAR */ 214 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 215 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 216 217 /* 218 * IFC Definitions 219 */ 220 /* NOR Flash on IFC */ 221 222 #ifdef CONFIG_SPL_BUILD 223 #define CONFIG_SYS_NO_FLASH 224 #endif 225 #define CONFIG_SYS_FLASH_BASE 0x88000000 226 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 227 228 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 229 230 #define CONFIG_SYS_NOR_CSPR 0x88000101 231 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 232 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 233 /* NOR Flash Timing Params */ 234 235 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 236 | FTIM0_NOR_TEADC(0x03) \ 237 | FTIM0_NOR_TAVDS(0x00) \ 238 | FTIM0_NOR_TEAHC(0x0f)) 239 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 240 | FTIM1_NOR_TRAD_NOR(0x09) \ 241 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 242 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 243 | FTIM2_NOR_TCH(0x4) \ 244 | FTIM2_NOR_TWPH(0x7) \ 245 | FTIM2_NOR_TWP(0x1e)) 246 #define CONFIG_SYS_NOR_FTIM3 0x0 247 248 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 249 #define CONFIG_SYS_FLASH_QUIET_TEST 250 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 251 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 252 253 #undef CONFIG_SYS_FLASH_CHECKSUM 254 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 255 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 256 257 /* CFI for NOR Flash */ 258 #define CONFIG_FLASH_CFI_DRIVER 259 #define CONFIG_SYS_FLASH_CFI 260 #define CONFIG_SYS_FLASH_EMPTY_INFO 261 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 262 263 /* NAND Flash on IFC */ 264 #define CONFIG_SYS_NAND_BASE 0xff800000 265 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 266 267 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 268 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 269 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 270 | CSPR_V) 271 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 272 273 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 274 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 275 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 276 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 277 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 278 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 279 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 280 281 /* NAND Flash Timing Params */ 282 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 283 | FTIM0_NAND_TWP(0x05) \ 284 | FTIM0_NAND_TWCHT(0x02) \ 285 | FTIM0_NAND_TWH(0x04)) 286 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 287 | FTIM1_NAND_TWBE(0x1e) \ 288 | FTIM1_NAND_TRR(0x07) \ 289 | FTIM1_NAND_TRP(0x05)) 290 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 291 | FTIM2_NAND_TREH(0x04) \ 292 | FTIM2_NAND_TWHRE(0x11)) 293 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 294 295 #define CONFIG_SYS_NAND_DDR_LAW 11 296 297 /* NAND */ 298 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 299 #define CONFIG_SYS_MAX_NAND_DEVICE 1 300 #define CONFIG_CMD_NAND 301 302 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 303 304 #ifndef CONFIG_SPL_BUILD 305 #define CONFIG_FSL_QIXIS 306 #endif 307 #ifdef CONFIG_FSL_QIXIS 308 #define CONFIG_SYS_FPGA_BASE 0xffb00000 309 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 310 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 311 #define QIXIS_LBMAP_SWITCH 9 312 #define QIXIS_LBMAP_MASK 0x07 313 #define QIXIS_LBMAP_SHIFT 0 314 #define QIXIS_LBMAP_DFLTBANK 0x00 315 #define QIXIS_LBMAP_ALTBANK 0x04 316 #define QIXIS_RST_CTL_RESET 0x83 317 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 318 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 319 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 320 321 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 322 323 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 324 | CSPR_PORT_SIZE_8 \ 325 | CSPR_MSEL_GPCM \ 326 | CSPR_V) 327 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 328 #define CONFIG_SYS_CSOR2 0x0 329 /* CPLD Timing parameters for IFC CS3 */ 330 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 331 FTIM0_GPCM_TEADC(0x0e) | \ 332 FTIM0_GPCM_TEAHC(0x0e)) 333 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 334 FTIM1_GPCM_TRAD(0x1f)) 335 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 336 FTIM2_GPCM_TCH(0x8) | \ 337 FTIM2_GPCM_TWP(0x1f)) 338 #define CONFIG_SYS_CS2_FTIM3 0x0 339 #endif 340 341 /* Set up IFC registers for boot location NOR/NAND */ 342 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 343 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 344 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 345 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 346 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 347 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 348 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 349 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 350 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 351 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 352 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 353 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 354 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 355 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 356 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 357 #else 358 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 359 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 360 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 361 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 362 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 363 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 364 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 365 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 366 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 367 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 368 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 369 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 370 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 371 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 372 #endif 373 374 #define CONFIG_BOARD_EARLY_INIT_R 375 376 #define CONFIG_SYS_INIT_RAM_LOCK 377 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 378 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 379 380 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 381 - GENERATED_GBL_DATA_SIZE) 382 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 383 384 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 385 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 386 387 /* Serial Port */ 388 #define CONFIG_CONS_INDEX 1 389 #undef CONFIG_SERIAL_SOFTWARE_FIFO 390 #define CONFIG_SYS_NS16550_SERIAL 391 #define CONFIG_SYS_NS16550_REG_SIZE 1 392 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 393 #ifdef CONFIG_SPL_BUILD 394 #define CONFIG_NS16550_MIN_FUNCTIONS 395 #endif 396 397 #define CONFIG_SYS_BAUDRATE_TABLE \ 398 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 399 400 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 401 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 402 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 403 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 404 405 #define CONFIG_SYS_I2C 406 #define CONFIG_SYS_I2C_FSL 407 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 408 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 409 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 410 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 411 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 412 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 413 414 /* I2C EEPROM */ 415 #define CONFIG_ID_EEPROM 416 #ifdef CONFIG_ID_EEPROM 417 #define CONFIG_SYS_I2C_EEPROM_NXID 418 #endif 419 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 420 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 421 #define CONFIG_SYS_EEPROM_BUS_NUM 0 422 423 /* enable read and write access to EEPROM */ 424 #define CONFIG_CMD_EEPROM 425 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 426 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 427 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 428 429 /* I2C FPGA */ 430 #define CONFIG_I2C_FPGA 431 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 432 433 #define CONFIG_RTC_DS3231 434 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 435 436 /* 437 * SPI interface will not be available in case of NAND boot SPI CS0 will be 438 * used for SLIC 439 */ 440 /* eSPI - Enhanced SPI */ 441 #ifdef CONFIG_FSL_ESPI 442 #define CONFIG_SF_DEFAULT_SPEED 10000000 443 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 444 #endif 445 446 #if defined(CONFIG_TSEC_ENET) 447 448 #define CONFIG_MII /* MII PHY management */ 449 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 450 #define CONFIG_TSEC1 1 451 #define CONFIG_TSEC1_NAME "eTSEC1" 452 #define CONFIG_TSEC2 1 453 #define CONFIG_TSEC2_NAME "eTSEC2" 454 455 #define TSEC1_PHY_ADDR 0 456 #define TSEC2_PHY_ADDR 1 457 458 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 459 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 460 461 #define TSEC1_PHYIDX 0 462 #define TSEC2_PHYIDX 0 463 464 #define CONFIG_ETHPRIME "eTSEC1" 465 466 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 467 468 /* TBI PHY configuration for SGMII mode */ 469 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 470 TBICR_PHY_RESET \ 471 | TBICR_ANEG_ENABLE \ 472 | TBICR_FULL_DUPLEX \ 473 | TBICR_SPEED1_SET \ 474 ) 475 476 #endif /* CONFIG_TSEC_ENET */ 477 478 #ifdef CONFIG_MMC 479 #define CONFIG_FSL_ESDHC 480 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 481 #endif 482 483 #define CONFIG_USB_EHCI /* USB */ 484 #ifdef CONFIG_USB_EHCI 485 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 486 #define CONFIG_USB_EHCI_FSL 487 #define CONFIG_HAS_FSL_DR_USB 488 #endif 489 490 /* 491 * Environment 492 */ 493 #if defined(CONFIG_RAMBOOT_SDCARD) 494 #define CONFIG_ENV_IS_IN_MMC 495 #define CONFIG_FSL_FIXED_MMC_LOCATION 496 #define CONFIG_SYS_MMC_ENV_DEV 0 497 #define CONFIG_ENV_SIZE 0x2000 498 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 499 #define CONFIG_ENV_IS_IN_SPI_FLASH 500 #define CONFIG_ENV_SPI_BUS 0 501 #define CONFIG_ENV_SPI_CS 0 502 #define CONFIG_ENV_SPI_MAX_HZ 10000000 503 #define CONFIG_ENV_SPI_MODE 0 504 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 505 #define CONFIG_ENV_SECT_SIZE 0x10000 506 #define CONFIG_ENV_SIZE 0x2000 507 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 508 #define CONFIG_ENV_IS_IN_NAND 509 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 510 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 511 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 512 #elif defined(CONFIG_SYS_RAMBOOT) 513 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 514 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 515 #define CONFIG_ENV_SIZE 0x2000 516 #else 517 #define CONFIG_ENV_IS_IN_FLASH 518 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 519 #define CONFIG_ENV_SIZE 0x2000 520 #define CONFIG_ENV_SECT_SIZE 0x20000 521 #endif 522 523 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 524 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 525 526 /* 527 * Command line configuration. 528 */ 529 #define CONFIG_CMD_DATE 530 #define CONFIG_CMD_ERRATA 531 #define CONFIG_CMD_IRQ 532 #define CONFIG_CMD_REGINFO 533 534 /* Hash command with SHA acceleration supported in hardware */ 535 #ifdef CONFIG_FSL_CAAM 536 #define CONFIG_CMD_HASH 537 #define CONFIG_SHA_HW_ACCEL 538 #endif 539 540 /* 541 * Miscellaneous configurable options 542 */ 543 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 544 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 545 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 546 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 547 548 #if defined(CONFIG_CMD_KGDB) 549 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 550 #else 551 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 552 #endif 553 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 554 /* Print Buffer Size */ 555 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 556 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 557 558 /* 559 * For booting Linux, the board info and command line data 560 * have to be in the first 64 MB of memory, since this is 561 * the maximum mapped by the Linux kernel during initialization. 562 */ 563 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 564 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 565 566 #if defined(CONFIG_CMD_KGDB) 567 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 568 #endif 569 570 /* 571 * Dynamic MTD Partition support with mtdparts 572 */ 573 #ifndef CONFIG_SYS_NO_FLASH 574 #define CONFIG_MTD_DEVICE 575 #define CONFIG_MTD_PARTITIONS 576 #define CONFIG_CMD_MTDPARTS 577 #define CONFIG_FLASH_CFI_MTD 578 #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," 579 #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ 580 "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ 581 "8m(kernel),512k(dtb),-(fs)" 582 #endif 583 /* 584 * Environment Configuration 585 */ 586 587 #if defined(CONFIG_TSEC_ENET) 588 #define CONFIG_HAS_ETH0 589 #define CONFIG_HAS_ETH1 590 #endif 591 592 #define CONFIG_HOSTNAME BSC9132qds 593 #define CONFIG_ROOTPATH "/opt/nfsroot" 594 #define CONFIG_BOOTFILE "uImage" 595 #define CONFIG_UBOOTPATH "u-boot.bin" 596 597 #define CONFIG_BAUDRATE 115200 598 599 #ifdef CONFIG_SDCARD 600 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 601 #else 602 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 603 #endif 604 605 #define CONFIG_EXTRA_ENV_SETTINGS \ 606 "netdev=eth0\0" \ 607 "uboot=" CONFIG_UBOOTPATH "\0" \ 608 "loadaddr=1000000\0" \ 609 "bootfile=uImage\0" \ 610 "consoledev=ttyS0\0" \ 611 "ramdiskaddr=2000000\0" \ 612 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 613 "fdtaddr=1e00000\0" \ 614 "fdtfile=bsc9132qds.dtb\0" \ 615 "bdev=sda1\0" \ 616 CONFIG_DEF_HWCONFIG\ 617 "othbootargs=mem=880M ramdisk_size=600000 " \ 618 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 619 "isolcpus=0\0" \ 620 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 621 "console=$consoledev,$baudrate $othbootargs; " \ 622 "usb start;" \ 623 "ext2load usb 0:4 $loadaddr $bootfile;" \ 624 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 625 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 626 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 627 "debug_halt_off=mw ff7e0e30 0xf0000000;" 628 629 #define CONFIG_NFSBOOTCOMMAND \ 630 "setenv bootargs root=/dev/nfs rw " \ 631 "nfsroot=$serverip:$rootpath " \ 632 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 633 "console=$consoledev,$baudrate $othbootargs;" \ 634 "tftp $loadaddr $bootfile;" \ 635 "tftp $fdtaddr $fdtfile;" \ 636 "bootm $loadaddr - $fdtaddr" 637 638 #define CONFIG_HDBOOT \ 639 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 640 "console=$consoledev,$baudrate $othbootargs;" \ 641 "usb start;" \ 642 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 643 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 644 "bootm $loadaddr - $fdtaddr" 645 646 #define CONFIG_RAMBOOTCOMMAND \ 647 "setenv bootargs root=/dev/ram rw " \ 648 "console=$consoledev,$baudrate $othbootargs; " \ 649 "tftp $ramdiskaddr $ramdiskfile;" \ 650 "tftp $loadaddr $bootfile;" \ 651 "tftp $fdtaddr $fdtfile;" \ 652 "bootm $loadaddr $ramdiskaddr $fdtaddr" 653 654 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 655 656 #include <asm/fsl_secure_boot.h> 657 658 #endif /* __CONFIG_H */ 659