1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9132 QDS board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_MISC_INIT_R 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 18 #define CONFIG_SYS_RAMBOOT 19 #define CONFIG_SYS_EXTRA_ENV_RELOC 20 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 21 #endif 22 #ifdef CONFIG_SPIFLASH 23 #define CONFIG_RAMBOOT_SPIFLASH 24 #define CONFIG_SYS_RAMBOOT 25 #define CONFIG_SYS_EXTRA_ENV_RELOC 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 27 #endif 28 #ifdef CONFIG_NAND_SECBOOT 29 #define CONFIG_RAMBOOT_NAND 30 #define CONFIG_SYS_RAMBOOT 31 #define CONFIG_SYS_EXTRA_ENV_RELOC 32 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 33 #endif 34 35 #ifdef CONFIG_NAND 36 #define CONFIG_SPL_INIT_MINIMAL 37 #define CONFIG_SPL_NAND_BOOT 38 #define CONFIG_SPL_FLUSH_IMAGE 39 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 40 41 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 42 #define CONFIG_SPL_MAX_SIZE 8192 43 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 44 #define CONFIG_SPL_RELOC_STACK 0x00100000 45 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 46 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 47 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 48 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 50 #endif 51 52 #ifndef CONFIG_RESET_VECTOR_ADDRESS 53 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 54 #endif 55 56 #ifdef CONFIG_SPL_BUILD 57 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 58 #else 59 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 60 #endif 61 62 /* High Level Configuration Options */ 63 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 64 65 #if defined(CONFIG_PCI) 66 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 67 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 68 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 69 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 70 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 71 72 /* 73 * PCI Windows 74 * Memory space is mapped 1-1, but I/O space must start from 0. 75 */ 76 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 77 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 78 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 79 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 80 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 81 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 82 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 83 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 84 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 85 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 86 87 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 88 #endif 89 90 #define CONFIG_ENV_OVERWRITE 91 #define CONFIG_TSEC_ENET /* ethernet */ 92 93 #if defined(CONFIG_SYS_CLK_100_DDR_100) 94 #define CONFIG_SYS_CLK_FREQ 100000000 95 #define CONFIG_DDR_CLK_FREQ 100000000 96 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 97 #define CONFIG_SYS_CLK_FREQ 100000000 98 #define CONFIG_DDR_CLK_FREQ 133000000 99 #endif 100 101 #define CONFIG_MP 102 103 #define CONFIG_HWCONFIG 104 /* 105 * These can be toggled for performance analysis, otherwise use default. 106 */ 107 #define CONFIG_L2_CACHE /* toggle L2 cache */ 108 #define CONFIG_BTB /* enable branch predition */ 109 110 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 111 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 112 113 /* DDR Setup */ 114 #define CONFIG_SYS_SPD_BUS_NUM 0 115 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 116 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 117 #define CONFIG_FSL_DDR_INTERACTIVE 118 119 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 120 121 #define CONFIG_SYS_SDRAM_SIZE (1024) 122 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 123 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 124 125 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 126 127 /* DDR3 Controller Settings */ 128 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 129 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 130 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 131 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 132 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 133 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 134 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 135 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 136 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 137 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 138 139 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 140 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 141 #define CONFIG_SYS_DDR_RCW_1 0x00000000 142 #define CONFIG_SYS_DDR_RCW_2 0x00000000 143 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 144 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 145 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 146 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 147 148 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 149 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 150 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 151 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 152 153 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 154 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 155 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 156 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 157 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 158 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 159 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 160 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 161 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 162 163 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 164 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 165 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 166 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 167 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 168 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 169 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 170 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 171 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 172 173 /*FIXME: the following params are constant w.r.t diff freq 174 combinations. this should be removed later 175 */ 176 #if CONFIG_DDR_CLK_FREQ == 100000000 177 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 178 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 179 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 180 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 181 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 182 #elif CONFIG_DDR_CLK_FREQ == 133000000 183 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 184 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 185 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 186 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 187 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 188 #else 189 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 190 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 191 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 192 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 193 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 194 #endif 195 196 /* relocated CCSRBAR */ 197 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 198 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 199 200 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 201 202 /* DSP CCSRBAR */ 203 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 204 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 205 206 /* 207 * IFC Definitions 208 */ 209 /* NOR Flash on IFC */ 210 211 #define CONFIG_SYS_FLASH_BASE 0x88000000 212 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 213 214 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 215 216 #define CONFIG_SYS_NOR_CSPR 0x88000101 217 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 218 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 219 /* NOR Flash Timing Params */ 220 221 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 222 | FTIM0_NOR_TEADC(0x03) \ 223 | FTIM0_NOR_TAVDS(0x00) \ 224 | FTIM0_NOR_TEAHC(0x0f)) 225 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 226 | FTIM1_NOR_TRAD_NOR(0x09) \ 227 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 228 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 229 | FTIM2_NOR_TCH(0x4) \ 230 | FTIM2_NOR_TWPH(0x7) \ 231 | FTIM2_NOR_TWP(0x1e)) 232 #define CONFIG_SYS_NOR_FTIM3 0x0 233 234 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 235 #define CONFIG_SYS_FLASH_QUIET_TEST 236 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 237 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 238 239 #undef CONFIG_SYS_FLASH_CHECKSUM 240 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 241 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 242 243 /* CFI for NOR Flash */ 244 #define CONFIG_FLASH_CFI_DRIVER 245 #define CONFIG_SYS_FLASH_CFI 246 #define CONFIG_SYS_FLASH_EMPTY_INFO 247 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 248 249 /* NAND Flash on IFC */ 250 #define CONFIG_SYS_NAND_BASE 0xff800000 251 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 252 253 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 254 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 255 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 256 | CSPR_V) 257 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 258 259 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 260 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 261 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 262 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 263 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 264 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 265 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 266 267 /* NAND Flash Timing Params */ 268 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 269 | FTIM0_NAND_TWP(0x05) \ 270 | FTIM0_NAND_TWCHT(0x02) \ 271 | FTIM0_NAND_TWH(0x04)) 272 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 273 | FTIM1_NAND_TWBE(0x1e) \ 274 | FTIM1_NAND_TRR(0x07) \ 275 | FTIM1_NAND_TRP(0x05)) 276 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 277 | FTIM2_NAND_TREH(0x04) \ 278 | FTIM2_NAND_TWHRE(0x11)) 279 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 280 281 #define CONFIG_SYS_NAND_DDR_LAW 11 282 283 /* NAND */ 284 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 285 #define CONFIG_SYS_MAX_NAND_DEVICE 1 286 287 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 288 289 #ifndef CONFIG_SPL_BUILD 290 #define CONFIG_FSL_QIXIS 291 #endif 292 #ifdef CONFIG_FSL_QIXIS 293 #define CONFIG_SYS_FPGA_BASE 0xffb00000 294 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 295 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 296 #define QIXIS_LBMAP_SWITCH 9 297 #define QIXIS_LBMAP_MASK 0x07 298 #define QIXIS_LBMAP_SHIFT 0 299 #define QIXIS_LBMAP_DFLTBANK 0x00 300 #define QIXIS_LBMAP_ALTBANK 0x04 301 #define QIXIS_RST_CTL_RESET 0x83 302 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 303 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 304 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 305 306 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 307 308 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 309 | CSPR_PORT_SIZE_8 \ 310 | CSPR_MSEL_GPCM \ 311 | CSPR_V) 312 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 313 #define CONFIG_SYS_CSOR2 0x0 314 /* CPLD Timing parameters for IFC CS3 */ 315 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 316 FTIM0_GPCM_TEADC(0x0e) | \ 317 FTIM0_GPCM_TEAHC(0x0e)) 318 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 319 FTIM1_GPCM_TRAD(0x1f)) 320 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 321 FTIM2_GPCM_TCH(0x8) | \ 322 FTIM2_GPCM_TWP(0x1f)) 323 #define CONFIG_SYS_CS2_FTIM3 0x0 324 #endif 325 326 /* Set up IFC registers for boot location NOR/NAND */ 327 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 328 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 329 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 330 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 331 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 332 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 333 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 334 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 335 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 336 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 337 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 338 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 339 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 340 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 341 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 342 #else 343 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 344 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 345 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 346 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 347 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 348 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 349 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 350 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 351 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 352 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 353 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 354 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 355 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 356 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 357 #endif 358 359 #define CONFIG_BOARD_EARLY_INIT_R 360 361 #define CONFIG_SYS_INIT_RAM_LOCK 362 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 363 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 364 365 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 366 - GENERATED_GBL_DATA_SIZE) 367 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 368 369 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 370 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 371 372 /* Serial Port */ 373 #define CONFIG_CONS_INDEX 1 374 #undef CONFIG_SERIAL_SOFTWARE_FIFO 375 #define CONFIG_SYS_NS16550_SERIAL 376 #define CONFIG_SYS_NS16550_REG_SIZE 1 377 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 378 #ifdef CONFIG_SPL_BUILD 379 #define CONFIG_NS16550_MIN_FUNCTIONS 380 #endif 381 382 #define CONFIG_SYS_BAUDRATE_TABLE \ 383 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 384 385 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 386 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 387 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 388 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 389 390 #define CONFIG_SYS_I2C 391 #define CONFIG_SYS_I2C_FSL 392 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 393 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 394 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 395 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 396 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 397 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 398 399 /* I2C EEPROM */ 400 #define CONFIG_ID_EEPROM 401 #ifdef CONFIG_ID_EEPROM 402 #define CONFIG_SYS_I2C_EEPROM_NXID 403 #endif 404 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 405 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 406 #define CONFIG_SYS_EEPROM_BUS_NUM 0 407 408 /* enable read and write access to EEPROM */ 409 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 410 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 411 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 412 413 /* I2C FPGA */ 414 #define CONFIG_I2C_FPGA 415 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 416 417 #define CONFIG_RTC_DS3231 418 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 419 420 /* 421 * SPI interface will not be available in case of NAND boot SPI CS0 will be 422 * used for SLIC 423 */ 424 /* eSPI - Enhanced SPI */ 425 #ifdef CONFIG_FSL_ESPI 426 #define CONFIG_SF_DEFAULT_SPEED 10000000 427 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 428 #endif 429 430 #if defined(CONFIG_TSEC_ENET) 431 432 #define CONFIG_MII /* MII PHY management */ 433 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 434 #define CONFIG_TSEC1 1 435 #define CONFIG_TSEC1_NAME "eTSEC1" 436 #define CONFIG_TSEC2 1 437 #define CONFIG_TSEC2_NAME "eTSEC2" 438 439 #define TSEC1_PHY_ADDR 0 440 #define TSEC2_PHY_ADDR 1 441 442 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 443 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 444 445 #define TSEC1_PHYIDX 0 446 #define TSEC2_PHYIDX 0 447 448 #define CONFIG_ETHPRIME "eTSEC1" 449 450 /* TBI PHY configuration for SGMII mode */ 451 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 452 TBICR_PHY_RESET \ 453 | TBICR_ANEG_ENABLE \ 454 | TBICR_FULL_DUPLEX \ 455 | TBICR_SPEED1_SET \ 456 ) 457 458 #endif /* CONFIG_TSEC_ENET */ 459 460 #ifdef CONFIG_MMC 461 #define CONFIG_FSL_ESDHC 462 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 463 #endif 464 465 #ifdef CONFIG_USB_EHCI_HCD 466 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 467 #define CONFIG_USB_EHCI_FSL 468 #define CONFIG_HAS_FSL_DR_USB 469 #endif 470 471 /* 472 * Environment 473 */ 474 #if defined(CONFIG_RAMBOOT_SDCARD) 475 #define CONFIG_FSL_FIXED_MMC_LOCATION 476 #define CONFIG_SYS_MMC_ENV_DEV 0 477 #define CONFIG_ENV_SIZE 0x2000 478 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 479 #define CONFIG_ENV_SPI_BUS 0 480 #define CONFIG_ENV_SPI_CS 0 481 #define CONFIG_ENV_SPI_MAX_HZ 10000000 482 #define CONFIG_ENV_SPI_MODE 0 483 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 484 #define CONFIG_ENV_SECT_SIZE 0x10000 485 #define CONFIG_ENV_SIZE 0x2000 486 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 487 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 488 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 489 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 490 #elif defined(CONFIG_SYS_RAMBOOT) 491 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 492 #define CONFIG_ENV_SIZE 0x2000 493 #else 494 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 495 #define CONFIG_ENV_SIZE 0x2000 496 #define CONFIG_ENV_SECT_SIZE 0x20000 497 #endif 498 499 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 500 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 501 502 /* 503 * Miscellaneous configurable options 504 */ 505 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 506 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 507 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 508 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 509 510 /* 511 * For booting Linux, the board info and command line data 512 * have to be in the first 64 MB of memory, since this is 513 * the maximum mapped by the Linux kernel during initialization. 514 */ 515 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 516 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 517 518 #if defined(CONFIG_CMD_KGDB) 519 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 520 #endif 521 522 /* 523 * Dynamic MTD Partition support with mtdparts 524 */ 525 #ifdef CONFIG_MTD_NOR_FLASH 526 #define CONFIG_MTD_DEVICE 527 #define CONFIG_MTD_PARTITIONS 528 #define CONFIG_FLASH_CFI_MTD 529 #endif 530 /* 531 * Environment Configuration 532 */ 533 534 #if defined(CONFIG_TSEC_ENET) 535 #define CONFIG_HAS_ETH0 536 #define CONFIG_HAS_ETH1 537 #endif 538 539 #define CONFIG_HOSTNAME BSC9132qds 540 #define CONFIG_ROOTPATH "/opt/nfsroot" 541 #define CONFIG_BOOTFILE "uImage" 542 #define CONFIG_UBOOTPATH "u-boot.bin" 543 544 #ifdef CONFIG_SDCARD 545 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 546 #else 547 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 548 #endif 549 550 #define CONFIG_EXTRA_ENV_SETTINGS \ 551 "netdev=eth0\0" \ 552 "uboot=" CONFIG_UBOOTPATH "\0" \ 553 "loadaddr=1000000\0" \ 554 "bootfile=uImage\0" \ 555 "consoledev=ttyS0\0" \ 556 "ramdiskaddr=2000000\0" \ 557 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 558 "fdtaddr=1e00000\0" \ 559 "fdtfile=bsc9132qds.dtb\0" \ 560 "bdev=sda1\0" \ 561 CONFIG_DEF_HWCONFIG\ 562 "othbootargs=mem=880M ramdisk_size=600000 " \ 563 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 564 "isolcpus=0\0" \ 565 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 566 "console=$consoledev,$baudrate $othbootargs; " \ 567 "usb start;" \ 568 "ext2load usb 0:4 $loadaddr $bootfile;" \ 569 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 570 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 571 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 572 "debug_halt_off=mw ff7e0e30 0xf0000000;" 573 574 #define CONFIG_NFSBOOTCOMMAND \ 575 "setenv bootargs root=/dev/nfs rw " \ 576 "nfsroot=$serverip:$rootpath " \ 577 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 578 "console=$consoledev,$baudrate $othbootargs;" \ 579 "tftp $loadaddr $bootfile;" \ 580 "tftp $fdtaddr $fdtfile;" \ 581 "bootm $loadaddr - $fdtaddr" 582 583 #define CONFIG_HDBOOT \ 584 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 585 "console=$consoledev,$baudrate $othbootargs;" \ 586 "usb start;" \ 587 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 588 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 589 "bootm $loadaddr - $fdtaddr" 590 591 #define CONFIG_RAMBOOTCOMMAND \ 592 "setenv bootargs root=/dev/ram rw " \ 593 "console=$consoledev,$baudrate $othbootargs; " \ 594 "tftp $ramdiskaddr $ramdiskfile;" \ 595 "tftp $loadaddr $bootfile;" \ 596 "tftp $fdtaddr $fdtfile;" \ 597 "bootm $loadaddr $ramdiskaddr $fdtaddr" 598 599 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 600 601 #include <asm/fsl_secure_boot.h> 602 603 #endif /* __CONFIG_H */ 604