1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9132 QDS board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_MISC_INIT_R 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 18 #define CONFIG_SYS_RAMBOOT 19 #define CONFIG_SYS_EXTRA_ENV_RELOC 20 #define CONFIG_SYS_TEXT_BASE 0x11000000 21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 22 #endif 23 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 24 #ifdef CONFIG_SPIFLASH 25 #define CONFIG_RAMBOOT_SPIFLASH 26 #define CONFIG_SYS_RAMBOOT 27 #define CONFIG_SYS_EXTRA_ENV_RELOC 28 #define CONFIG_SYS_TEXT_BASE 0x11000000 29 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 30 #endif 31 #ifdef CONFIG_NAND_SECBOOT 32 #define CONFIG_RAMBOOT_NAND 33 #define CONFIG_SYS_RAMBOOT 34 #define CONFIG_SYS_EXTRA_ENV_RELOC 35 #define CONFIG_SYS_TEXT_BASE 0x11000000 36 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 37 #endif 38 39 #ifdef CONFIG_NAND 40 #define CONFIG_SPL_INIT_MINIMAL 41 #define CONFIG_SPL_NAND_BOOT 42 #define CONFIG_SPL_FLUSH_IMAGE 43 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 44 45 #define CONFIG_SYS_TEXT_BASE 0x00201000 46 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 47 #define CONFIG_SPL_MAX_SIZE 8192 48 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 49 #define CONFIG_SPL_RELOC_STACK 0x00100000 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 51 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 55 #endif 56 57 #ifndef CONFIG_SYS_TEXT_BASE 58 #define CONFIG_SYS_TEXT_BASE 0x8ff40000 59 #endif 60 61 #ifndef CONFIG_RESET_VECTOR_ADDRESS 62 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 63 #endif 64 65 #ifdef CONFIG_SPL_BUILD 66 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 67 #else 68 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 69 #endif 70 71 /* High Level Configuration Options */ 72 #define CONFIG_BOOKE /* BOOKE */ 73 #define CONFIG_E500 /* BOOKE e500 family */ 74 #define CONFIG_FSL_IFC /* Enable IFC Support */ 75 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 76 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 77 78 #if defined(CONFIG_PCI) 79 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 80 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 81 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 82 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 83 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 84 85 #define CONFIG_CMD_PCI 86 87 /* 88 * PCI Windows 89 * Memory space is mapped 1-1, but I/O space must start from 0. 90 */ 91 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 92 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 93 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 94 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 95 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 96 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 97 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 98 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 99 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 100 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 101 102 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 103 #define CONFIG_DOS_PARTITION 104 #endif 105 106 #define CONFIG_FSL_LAW /* Use common FSL init code */ 107 #define CONFIG_ENV_OVERWRITE 108 #define CONFIG_TSEC_ENET /* ethernet */ 109 110 #if defined(CONFIG_SYS_CLK_100_DDR_100) 111 #define CONFIG_SYS_CLK_FREQ 100000000 112 #define CONFIG_DDR_CLK_FREQ 100000000 113 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 114 #define CONFIG_SYS_CLK_FREQ 100000000 115 #define CONFIG_DDR_CLK_FREQ 133000000 116 #endif 117 118 #define CONFIG_MP 119 120 #define CONFIG_HWCONFIG 121 /* 122 * These can be toggled for performance analysis, otherwise use default. 123 */ 124 #define CONFIG_L2_CACHE /* toggle L2 cache */ 125 #define CONFIG_BTB /* enable branch predition */ 126 127 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 128 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 129 130 /* DDR Setup */ 131 #define CONFIG_SYS_FSL_DDR3 132 #define CONFIG_SYS_SPD_BUS_NUM 0 133 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 134 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 135 #define CONFIG_FSL_DDR_INTERACTIVE 136 137 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 138 139 #define CONFIG_SYS_SDRAM_SIZE (1024) 140 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 141 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 142 143 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 144 145 /* DDR3 Controller Settings */ 146 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 147 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 148 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 149 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 150 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 151 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 152 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 153 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 154 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 155 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 156 157 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 158 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 159 #define CONFIG_SYS_DDR_RCW_1 0x00000000 160 #define CONFIG_SYS_DDR_RCW_2 0x00000000 161 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 162 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 163 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 164 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 165 166 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 167 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 168 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 169 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 170 171 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 172 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 173 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 174 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 175 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 176 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 177 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 178 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 179 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 180 181 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 182 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 183 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 184 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 185 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 186 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 187 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 188 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 189 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 190 191 /*FIXME: the following params are constant w.r.t diff freq 192 combinations. this should be removed later 193 */ 194 #if CONFIG_DDR_CLK_FREQ == 100000000 195 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 196 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 197 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 198 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 199 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 200 #elif CONFIG_DDR_CLK_FREQ == 133000000 201 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 202 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 203 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 204 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 205 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 206 #else 207 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 208 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 209 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 210 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 211 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 212 #endif 213 214 /* relocated CCSRBAR */ 215 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 216 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 217 218 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 219 220 /* DSP CCSRBAR */ 221 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 222 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 223 224 /* 225 * IFC Definitions 226 */ 227 /* NOR Flash on IFC */ 228 229 #ifdef CONFIG_SPL_BUILD 230 #define CONFIG_SYS_NO_FLASH 231 #endif 232 #define CONFIG_SYS_FLASH_BASE 0x88000000 233 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 234 235 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 236 237 #define CONFIG_SYS_NOR_CSPR 0x88000101 238 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 239 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 240 /* NOR Flash Timing Params */ 241 242 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 243 | FTIM0_NOR_TEADC(0x03) \ 244 | FTIM0_NOR_TAVDS(0x00) \ 245 | FTIM0_NOR_TEAHC(0x0f)) 246 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 247 | FTIM1_NOR_TRAD_NOR(0x09) \ 248 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 249 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 250 | FTIM2_NOR_TCH(0x4) \ 251 | FTIM2_NOR_TWPH(0x7) \ 252 | FTIM2_NOR_TWP(0x1e)) 253 #define CONFIG_SYS_NOR_FTIM3 0x0 254 255 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 256 #define CONFIG_SYS_FLASH_QUIET_TEST 257 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 258 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 259 260 #undef CONFIG_SYS_FLASH_CHECKSUM 261 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 262 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 263 264 /* CFI for NOR Flash */ 265 #define CONFIG_FLASH_CFI_DRIVER 266 #define CONFIG_SYS_FLASH_CFI 267 #define CONFIG_SYS_FLASH_EMPTY_INFO 268 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 269 270 /* NAND Flash on IFC */ 271 #define CONFIG_SYS_NAND_BASE 0xff800000 272 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 273 274 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 275 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 276 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 277 | CSPR_V) 278 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 279 280 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 281 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 282 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 283 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 284 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 285 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 286 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 287 288 /* NAND Flash Timing Params */ 289 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 290 | FTIM0_NAND_TWP(0x05) \ 291 | FTIM0_NAND_TWCHT(0x02) \ 292 | FTIM0_NAND_TWH(0x04)) 293 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 294 | FTIM1_NAND_TWBE(0x1e) \ 295 | FTIM1_NAND_TRR(0x07) \ 296 | FTIM1_NAND_TRP(0x05)) 297 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 298 | FTIM2_NAND_TREH(0x04) \ 299 | FTIM2_NAND_TWHRE(0x11)) 300 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 301 302 #define CONFIG_SYS_NAND_DDR_LAW 11 303 304 /* NAND */ 305 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 306 #define CONFIG_SYS_MAX_NAND_DEVICE 1 307 #define CONFIG_CMD_NAND 308 309 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 310 311 #ifndef CONFIG_SPL_BUILD 312 #define CONFIG_FSL_QIXIS 313 #endif 314 #ifdef CONFIG_FSL_QIXIS 315 #define CONFIG_SYS_FPGA_BASE 0xffb00000 316 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 317 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 318 #define QIXIS_LBMAP_SWITCH 9 319 #define QIXIS_LBMAP_MASK 0x07 320 #define QIXIS_LBMAP_SHIFT 0 321 #define QIXIS_LBMAP_DFLTBANK 0x00 322 #define QIXIS_LBMAP_ALTBANK 0x04 323 #define QIXIS_RST_CTL_RESET 0x83 324 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 325 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 326 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 327 328 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 329 330 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 331 | CSPR_PORT_SIZE_8 \ 332 | CSPR_MSEL_GPCM \ 333 | CSPR_V) 334 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 335 #define CONFIG_SYS_CSOR2 0x0 336 /* CPLD Timing parameters for IFC CS3 */ 337 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 338 FTIM0_GPCM_TEADC(0x0e) | \ 339 FTIM0_GPCM_TEAHC(0x0e)) 340 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 341 FTIM1_GPCM_TRAD(0x1f)) 342 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 343 FTIM2_GPCM_TCH(0x8) | \ 344 FTIM2_GPCM_TWP(0x1f)) 345 #define CONFIG_SYS_CS2_FTIM3 0x0 346 #endif 347 348 /* Set up IFC registers for boot location NOR/NAND */ 349 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 350 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 351 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 352 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 353 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 354 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 355 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 356 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 357 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 358 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 359 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 360 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 361 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 362 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 363 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 364 #else 365 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 366 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 367 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 368 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 369 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 370 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 371 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 372 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 373 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 374 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 375 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 376 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 377 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 378 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 379 #endif 380 381 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 382 #define CONFIG_BOARD_EARLY_INIT_R 383 384 #define CONFIG_SYS_INIT_RAM_LOCK 385 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 386 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 387 388 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 389 - GENERATED_GBL_DATA_SIZE) 390 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 391 392 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 393 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 394 395 /* Serial Port */ 396 #define CONFIG_CONS_INDEX 1 397 #undef CONFIG_SERIAL_SOFTWARE_FIFO 398 #define CONFIG_SYS_NS16550_SERIAL 399 #define CONFIG_SYS_NS16550_REG_SIZE 1 400 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 401 #ifdef CONFIG_SPL_BUILD 402 #define CONFIG_NS16550_MIN_FUNCTIONS 403 #endif 404 405 #define CONFIG_SYS_BAUDRATE_TABLE \ 406 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 407 408 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 409 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 410 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 411 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 412 413 #define CONFIG_SYS_I2C 414 #define CONFIG_SYS_I2C_FSL 415 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 416 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 417 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 418 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 419 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 420 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 421 422 /* I2C EEPROM */ 423 #define CONFIG_ID_EEPROM 424 #ifdef CONFIG_ID_EEPROM 425 #define CONFIG_SYS_I2C_EEPROM_NXID 426 #endif 427 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 428 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 429 #define CONFIG_SYS_EEPROM_BUS_NUM 0 430 431 /* enable read and write access to EEPROM */ 432 #define CONFIG_CMD_EEPROM 433 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 434 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 435 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 436 437 /* I2C FPGA */ 438 #define CONFIG_I2C_FPGA 439 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 440 441 #define CONFIG_RTC_DS3231 442 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 443 444 /* 445 * SPI interface will not be available in case of NAND boot SPI CS0 will be 446 * used for SLIC 447 */ 448 /* eSPI - Enhanced SPI */ 449 #ifdef CONFIG_FSL_ESPI 450 #define CONFIG_SF_DEFAULT_SPEED 10000000 451 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 452 #endif 453 454 #if defined(CONFIG_TSEC_ENET) 455 456 #define CONFIG_MII /* MII PHY management */ 457 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 458 #define CONFIG_TSEC1 1 459 #define CONFIG_TSEC1_NAME "eTSEC1" 460 #define CONFIG_TSEC2 1 461 #define CONFIG_TSEC2_NAME "eTSEC2" 462 463 #define TSEC1_PHY_ADDR 0 464 #define TSEC2_PHY_ADDR 1 465 466 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 467 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 468 469 #define TSEC1_PHYIDX 0 470 #define TSEC2_PHYIDX 0 471 472 #define CONFIG_ETHPRIME "eTSEC1" 473 474 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 475 476 /* TBI PHY configuration for SGMII mode */ 477 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 478 TBICR_PHY_RESET \ 479 | TBICR_ANEG_ENABLE \ 480 | TBICR_FULL_DUPLEX \ 481 | TBICR_SPEED1_SET \ 482 ) 483 484 #endif /* CONFIG_TSEC_ENET */ 485 486 #define CONFIG_MMC 487 #ifdef CONFIG_MMC 488 #define CONFIG_DOS_PARTITION 489 #define CONFIG_FSL_ESDHC 490 #define CONFIG_GENERIC_MMC 491 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 492 #endif 493 494 #define CONFIG_USB_EHCI /* USB */ 495 #ifdef CONFIG_USB_EHCI 496 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 497 #define CONFIG_USB_EHCI_FSL 498 #define CONFIG_HAS_FSL_DR_USB 499 #endif 500 501 /* 502 * Environment 503 */ 504 #if defined(CONFIG_RAMBOOT_SDCARD) 505 #define CONFIG_ENV_IS_IN_MMC 506 #define CONFIG_FSL_FIXED_MMC_LOCATION 507 #define CONFIG_SYS_MMC_ENV_DEV 0 508 #define CONFIG_ENV_SIZE 0x2000 509 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 510 #define CONFIG_ENV_IS_IN_SPI_FLASH 511 #define CONFIG_ENV_SPI_BUS 0 512 #define CONFIG_ENV_SPI_CS 0 513 #define CONFIG_ENV_SPI_MAX_HZ 10000000 514 #define CONFIG_ENV_SPI_MODE 0 515 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 516 #define CONFIG_ENV_SECT_SIZE 0x10000 517 #define CONFIG_ENV_SIZE 0x2000 518 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 519 #define CONFIG_ENV_IS_IN_NAND 520 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 521 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 522 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 523 #elif defined(CONFIG_SYS_RAMBOOT) 524 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 525 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 526 #define CONFIG_ENV_SIZE 0x2000 527 #else 528 #define CONFIG_ENV_IS_IN_FLASH 529 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 530 #define CONFIG_ENV_SIZE 0x2000 531 #define CONFIG_ENV_SECT_SIZE 0x20000 532 #endif 533 534 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 535 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 536 537 /* 538 * Command line configuration. 539 */ 540 #define CONFIG_CMD_DATE 541 #define CONFIG_CMD_ERRATA 542 #define CONFIG_CMD_IRQ 543 #define CONFIG_CMD_REGINFO 544 545 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 546 #define CONFIG_DOS_PARTITION 547 #endif 548 549 /* Hash command with SHA acceleration supported in hardware */ 550 #ifdef CONFIG_FSL_CAAM 551 #define CONFIG_CMD_HASH 552 #define CONFIG_SHA_HW_ACCEL 553 #endif 554 555 /* 556 * Miscellaneous configurable options 557 */ 558 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 559 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 560 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 561 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 562 563 #if defined(CONFIG_CMD_KGDB) 564 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 565 #else 566 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 567 #endif 568 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 569 /* Print Buffer Size */ 570 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 571 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 572 573 /* 574 * For booting Linux, the board info and command line data 575 * have to be in the first 64 MB of memory, since this is 576 * the maximum mapped by the Linux kernel during initialization. 577 */ 578 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 579 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 580 581 #if defined(CONFIG_CMD_KGDB) 582 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 583 #endif 584 585 /* 586 * Dynamic MTD Partition support with mtdparts 587 */ 588 #ifndef CONFIG_SYS_NO_FLASH 589 #define CONFIG_MTD_DEVICE 590 #define CONFIG_MTD_PARTITIONS 591 #define CONFIG_CMD_MTDPARTS 592 #define CONFIG_FLASH_CFI_MTD 593 #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," 594 #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ 595 "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ 596 "8m(kernel),512k(dtb),-(fs)" 597 #endif 598 /* 599 * Environment Configuration 600 */ 601 602 #if defined(CONFIG_TSEC_ENET) 603 #define CONFIG_HAS_ETH0 604 #define CONFIG_HAS_ETH1 605 #endif 606 607 #define CONFIG_HOSTNAME BSC9132qds 608 #define CONFIG_ROOTPATH "/opt/nfsroot" 609 #define CONFIG_BOOTFILE "uImage" 610 #define CONFIG_UBOOTPATH "u-boot.bin" 611 612 #define CONFIG_BAUDRATE 115200 613 614 #ifdef CONFIG_SDCARD 615 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 616 #else 617 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 618 #endif 619 620 #define CONFIG_EXTRA_ENV_SETTINGS \ 621 "netdev=eth0\0" \ 622 "uboot=" CONFIG_UBOOTPATH "\0" \ 623 "loadaddr=1000000\0" \ 624 "bootfile=uImage\0" \ 625 "consoledev=ttyS0\0" \ 626 "ramdiskaddr=2000000\0" \ 627 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 628 "fdtaddr=1e00000\0" \ 629 "fdtfile=bsc9132qds.dtb\0" \ 630 "bdev=sda1\0" \ 631 CONFIG_DEF_HWCONFIG\ 632 "othbootargs=mem=880M ramdisk_size=600000 " \ 633 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 634 "isolcpus=0\0" \ 635 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 636 "console=$consoledev,$baudrate $othbootargs; " \ 637 "usb start;" \ 638 "ext2load usb 0:4 $loadaddr $bootfile;" \ 639 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 640 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 641 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 642 "debug_halt_off=mw ff7e0e30 0xf0000000;" 643 644 #define CONFIG_NFSBOOTCOMMAND \ 645 "setenv bootargs root=/dev/nfs rw " \ 646 "nfsroot=$serverip:$rootpath " \ 647 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 648 "console=$consoledev,$baudrate $othbootargs;" \ 649 "tftp $loadaddr $bootfile;" \ 650 "tftp $fdtaddr $fdtfile;" \ 651 "bootm $loadaddr - $fdtaddr" 652 653 #define CONFIG_HDBOOT \ 654 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 655 "console=$consoledev,$baudrate $othbootargs;" \ 656 "usb start;" \ 657 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 658 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 659 "bootm $loadaddr - $fdtaddr" 660 661 #define CONFIG_RAMBOOTCOMMAND \ 662 "setenv bootargs root=/dev/ram rw " \ 663 "console=$consoledev,$baudrate $othbootargs; " \ 664 "tftp $ramdiskaddr $ramdiskfile;" \ 665 "tftp $loadaddr $bootfile;" \ 666 "tftp $fdtaddr $fdtfile;" \ 667 "bootm $loadaddr $ramdiskaddr $fdtaddr" 668 669 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 670 671 #include <asm/fsl_secure_boot.h> 672 673 #endif /* __CONFIG_H */ 674