1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9132 QDS board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_MISC_INIT_R 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 18 #define CONFIG_SYS_RAMBOOT 19 #define CONFIG_SYS_EXTRA_ENV_RELOC 20 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 21 #endif 22 #ifdef CONFIG_SPIFLASH 23 #define CONFIG_RAMBOOT_SPIFLASH 24 #define CONFIG_SYS_RAMBOOT 25 #define CONFIG_SYS_EXTRA_ENV_RELOC 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 27 #endif 28 #ifdef CONFIG_NAND_SECBOOT 29 #define CONFIG_RAMBOOT_NAND 30 #define CONFIG_SYS_RAMBOOT 31 #define CONFIG_SYS_EXTRA_ENV_RELOC 32 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 33 #endif 34 35 #ifdef CONFIG_NAND 36 #define CONFIG_SPL_INIT_MINIMAL 37 #define CONFIG_SPL_NAND_BOOT 38 #define CONFIG_SPL_FLUSH_IMAGE 39 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 40 41 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 42 #define CONFIG_SPL_MAX_SIZE 8192 43 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 44 #define CONFIG_SPL_RELOC_STACK 0x00100000 45 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 46 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 47 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 48 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 50 #endif 51 52 #ifndef CONFIG_RESET_VECTOR_ADDRESS 53 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 54 #endif 55 56 #ifdef CONFIG_SPL_BUILD 57 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 58 #else 59 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 60 #endif 61 62 /* High Level Configuration Options */ 63 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 64 65 #if defined(CONFIG_PCI) 66 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 67 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 68 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 69 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 70 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 71 72 /* 73 * PCI Windows 74 * Memory space is mapped 1-1, but I/O space must start from 0. 75 */ 76 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 77 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 78 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 79 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 80 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 81 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 82 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 83 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 84 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 85 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 86 87 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 88 #endif 89 90 #define CONFIG_ENV_OVERWRITE 91 92 #if defined(CONFIG_SYS_CLK_100_DDR_100) 93 #define CONFIG_SYS_CLK_FREQ 100000000 94 #define CONFIG_DDR_CLK_FREQ 100000000 95 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 96 #define CONFIG_SYS_CLK_FREQ 100000000 97 #define CONFIG_DDR_CLK_FREQ 133000000 98 #endif 99 100 #define CONFIG_MP 101 102 #define CONFIG_HWCONFIG 103 /* 104 * These can be toggled for performance analysis, otherwise use default. 105 */ 106 #define CONFIG_L2_CACHE /* toggle L2 cache */ 107 #define CONFIG_BTB /* enable branch predition */ 108 109 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 110 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 111 112 /* DDR Setup */ 113 #define CONFIG_SYS_SPD_BUS_NUM 0 114 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 115 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 116 #define CONFIG_FSL_DDR_INTERACTIVE 117 118 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 119 120 #define CONFIG_SYS_SDRAM_SIZE (1024) 121 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 122 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 123 124 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 125 126 /* DDR3 Controller Settings */ 127 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 128 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 129 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 130 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 131 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 132 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 133 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 134 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 135 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 136 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 137 138 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 139 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 140 #define CONFIG_SYS_DDR_RCW_1 0x00000000 141 #define CONFIG_SYS_DDR_RCW_2 0x00000000 142 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 143 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 144 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 145 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 146 147 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 148 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 149 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 150 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 151 152 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 153 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 154 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 155 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 156 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 157 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 158 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 159 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 160 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 161 162 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 163 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 164 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 165 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 166 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 167 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 168 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 169 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 170 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 171 172 /*FIXME: the following params are constant w.r.t diff freq 173 combinations. this should be removed later 174 */ 175 #if CONFIG_DDR_CLK_FREQ == 100000000 176 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 177 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 178 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 179 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 180 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 181 #elif CONFIG_DDR_CLK_FREQ == 133000000 182 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 183 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 184 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 185 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 186 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 187 #else 188 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 189 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 190 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 191 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 192 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 193 #endif 194 195 /* relocated CCSRBAR */ 196 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 197 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 198 199 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 200 201 /* DSP CCSRBAR */ 202 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 203 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 204 205 /* 206 * IFC Definitions 207 */ 208 /* NOR Flash on IFC */ 209 210 #define CONFIG_SYS_FLASH_BASE 0x88000000 211 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 212 213 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 214 215 #define CONFIG_SYS_NOR_CSPR 0x88000101 216 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 217 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 218 /* NOR Flash Timing Params */ 219 220 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 221 | FTIM0_NOR_TEADC(0x03) \ 222 | FTIM0_NOR_TAVDS(0x00) \ 223 | FTIM0_NOR_TEAHC(0x0f)) 224 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 225 | FTIM1_NOR_TRAD_NOR(0x09) \ 226 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 227 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 228 | FTIM2_NOR_TCH(0x4) \ 229 | FTIM2_NOR_TWPH(0x7) \ 230 | FTIM2_NOR_TWP(0x1e)) 231 #define CONFIG_SYS_NOR_FTIM3 0x0 232 233 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 234 #define CONFIG_SYS_FLASH_QUIET_TEST 235 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 236 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 237 238 #undef CONFIG_SYS_FLASH_CHECKSUM 239 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 240 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 241 242 /* CFI for NOR Flash */ 243 #define CONFIG_FLASH_CFI_DRIVER 244 #define CONFIG_SYS_FLASH_CFI 245 #define CONFIG_SYS_FLASH_EMPTY_INFO 246 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 247 248 /* NAND Flash on IFC */ 249 #define CONFIG_SYS_NAND_BASE 0xff800000 250 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 251 252 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 253 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 254 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 255 | CSPR_V) 256 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 257 258 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 259 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 260 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 261 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 262 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 263 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 264 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 265 266 /* NAND Flash Timing Params */ 267 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 268 | FTIM0_NAND_TWP(0x05) \ 269 | FTIM0_NAND_TWCHT(0x02) \ 270 | FTIM0_NAND_TWH(0x04)) 271 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 272 | FTIM1_NAND_TWBE(0x1e) \ 273 | FTIM1_NAND_TRR(0x07) \ 274 | FTIM1_NAND_TRP(0x05)) 275 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 276 | FTIM2_NAND_TREH(0x04) \ 277 | FTIM2_NAND_TWHRE(0x11)) 278 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 279 280 #define CONFIG_SYS_NAND_DDR_LAW 11 281 282 /* NAND */ 283 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 284 #define CONFIG_SYS_MAX_NAND_DEVICE 1 285 286 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 287 288 #ifndef CONFIG_SPL_BUILD 289 #define CONFIG_FSL_QIXIS 290 #endif 291 #ifdef CONFIG_FSL_QIXIS 292 #define CONFIG_SYS_FPGA_BASE 0xffb00000 293 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 294 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 295 #define QIXIS_LBMAP_SWITCH 9 296 #define QIXIS_LBMAP_MASK 0x07 297 #define QIXIS_LBMAP_SHIFT 0 298 #define QIXIS_LBMAP_DFLTBANK 0x00 299 #define QIXIS_LBMAP_ALTBANK 0x04 300 #define QIXIS_RST_CTL_RESET 0x83 301 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 302 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 303 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 304 305 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 306 307 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 308 | CSPR_PORT_SIZE_8 \ 309 | CSPR_MSEL_GPCM \ 310 | CSPR_V) 311 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 312 #define CONFIG_SYS_CSOR2 0x0 313 /* CPLD Timing parameters for IFC CS3 */ 314 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 315 FTIM0_GPCM_TEADC(0x0e) | \ 316 FTIM0_GPCM_TEAHC(0x0e)) 317 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 318 FTIM1_GPCM_TRAD(0x1f)) 319 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 320 FTIM2_GPCM_TCH(0x8) | \ 321 FTIM2_GPCM_TWP(0x1f)) 322 #define CONFIG_SYS_CS2_FTIM3 0x0 323 #endif 324 325 /* Set up IFC registers for boot location NOR/NAND */ 326 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 327 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 328 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 329 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 330 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 331 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 332 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 333 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 334 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 335 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 336 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 337 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 338 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 339 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 340 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 341 #else 342 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 343 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 344 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 345 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 346 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 347 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 348 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 349 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 350 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 351 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 352 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 353 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 354 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 355 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 356 #endif 357 358 #define CONFIG_SYS_INIT_RAM_LOCK 359 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 360 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 361 362 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 363 - GENERATED_GBL_DATA_SIZE) 364 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 365 366 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 367 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 368 369 /* Serial Port */ 370 #undef CONFIG_SERIAL_SOFTWARE_FIFO 371 #define CONFIG_SYS_NS16550_SERIAL 372 #define CONFIG_SYS_NS16550_REG_SIZE 1 373 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 374 #ifdef CONFIG_SPL_BUILD 375 #define CONFIG_NS16550_MIN_FUNCTIONS 376 #endif 377 378 #define CONFIG_SYS_BAUDRATE_TABLE \ 379 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 380 381 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 382 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 383 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 384 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 385 386 #define CONFIG_SYS_I2C 387 #define CONFIG_SYS_I2C_FSL 388 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 389 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 390 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 391 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 392 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 393 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 394 395 /* I2C EEPROM */ 396 #define CONFIG_ID_EEPROM 397 #ifdef CONFIG_ID_EEPROM 398 #define CONFIG_SYS_I2C_EEPROM_NXID 399 #endif 400 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 401 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 402 #define CONFIG_SYS_EEPROM_BUS_NUM 0 403 404 /* enable read and write access to EEPROM */ 405 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 406 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 407 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 408 409 /* I2C FPGA */ 410 #define CONFIG_I2C_FPGA 411 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 412 413 #define CONFIG_RTC_DS3231 414 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 415 416 /* 417 * SPI interface will not be available in case of NAND boot SPI CS0 will be 418 * used for SLIC 419 */ 420 /* eSPI - Enhanced SPI */ 421 #ifdef CONFIG_FSL_ESPI 422 #define CONFIG_SF_DEFAULT_SPEED 10000000 423 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 424 #endif 425 426 #if defined(CONFIG_TSEC_ENET) 427 428 #define CONFIG_MII /* MII PHY management */ 429 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 430 #define CONFIG_TSEC1 1 431 #define CONFIG_TSEC1_NAME "eTSEC1" 432 #define CONFIG_TSEC2 1 433 #define CONFIG_TSEC2_NAME "eTSEC2" 434 435 #define TSEC1_PHY_ADDR 0 436 #define TSEC2_PHY_ADDR 1 437 438 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 439 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 440 441 #define TSEC1_PHYIDX 0 442 #define TSEC2_PHYIDX 0 443 444 #define CONFIG_ETHPRIME "eTSEC1" 445 446 /* TBI PHY configuration for SGMII mode */ 447 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 448 TBICR_PHY_RESET \ 449 | TBICR_ANEG_ENABLE \ 450 | TBICR_FULL_DUPLEX \ 451 | TBICR_SPEED1_SET \ 452 ) 453 454 #endif /* CONFIG_TSEC_ENET */ 455 456 #ifdef CONFIG_MMC 457 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 458 #endif 459 460 #ifdef CONFIG_USB_EHCI_HCD 461 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 462 #define CONFIG_USB_EHCI_FSL 463 #define CONFIG_HAS_FSL_DR_USB 464 #endif 465 466 /* 467 * Environment 468 */ 469 #if defined(CONFIG_RAMBOOT_SDCARD) 470 #define CONFIG_FSL_FIXED_MMC_LOCATION 471 #define CONFIG_SYS_MMC_ENV_DEV 0 472 #define CONFIG_ENV_SIZE 0x2000 473 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 474 #define CONFIG_ENV_SPI_BUS 0 475 #define CONFIG_ENV_SPI_CS 0 476 #define CONFIG_ENV_SPI_MAX_HZ 10000000 477 #define CONFIG_ENV_SPI_MODE 0 478 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 479 #define CONFIG_ENV_SECT_SIZE 0x10000 480 #define CONFIG_ENV_SIZE 0x2000 481 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 482 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 483 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 484 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 485 #elif defined(CONFIG_SYS_RAMBOOT) 486 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 487 #define CONFIG_ENV_SIZE 0x2000 488 #else 489 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 490 #define CONFIG_ENV_SIZE 0x2000 491 #define CONFIG_ENV_SECT_SIZE 0x20000 492 #endif 493 494 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 495 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 496 497 /* 498 * Miscellaneous configurable options 499 */ 500 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 501 502 /* 503 * For booting Linux, the board info and command line data 504 * have to be in the first 64 MB of memory, since this is 505 * the maximum mapped by the Linux kernel during initialization. 506 */ 507 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 508 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 509 510 #if defined(CONFIG_CMD_KGDB) 511 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 512 #endif 513 514 /* 515 * Dynamic MTD Partition support with mtdparts 516 */ 517 #ifdef CONFIG_MTD_NOR_FLASH 518 #define CONFIG_MTD_DEVICE 519 #define CONFIG_MTD_PARTITIONS 520 #define CONFIG_FLASH_CFI_MTD 521 #endif 522 /* 523 * Environment Configuration 524 */ 525 526 #if defined(CONFIG_TSEC_ENET) 527 #define CONFIG_HAS_ETH0 528 #define CONFIG_HAS_ETH1 529 #endif 530 531 #define CONFIG_HOSTNAME "BSC9132qds" 532 #define CONFIG_ROOTPATH "/opt/nfsroot" 533 #define CONFIG_BOOTFILE "uImage" 534 #define CONFIG_UBOOTPATH "u-boot.bin" 535 536 #ifdef CONFIG_SDCARD 537 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 538 #else 539 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 540 #endif 541 542 #define CONFIG_EXTRA_ENV_SETTINGS \ 543 "netdev=eth0\0" \ 544 "uboot=" CONFIG_UBOOTPATH "\0" \ 545 "loadaddr=1000000\0" \ 546 "bootfile=uImage\0" \ 547 "consoledev=ttyS0\0" \ 548 "ramdiskaddr=2000000\0" \ 549 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 550 "fdtaddr=1e00000\0" \ 551 "fdtfile=bsc9132qds.dtb\0" \ 552 "bdev=sda1\0" \ 553 CONFIG_DEF_HWCONFIG\ 554 "othbootargs=mem=880M ramdisk_size=600000 " \ 555 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 556 "isolcpus=0\0" \ 557 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 558 "console=$consoledev,$baudrate $othbootargs; " \ 559 "usb start;" \ 560 "ext2load usb 0:4 $loadaddr $bootfile;" \ 561 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 562 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 563 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 564 "debug_halt_off=mw ff7e0e30 0xf0000000;" 565 566 #define CONFIG_NFSBOOTCOMMAND \ 567 "setenv bootargs root=/dev/nfs rw " \ 568 "nfsroot=$serverip:$rootpath " \ 569 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 570 "console=$consoledev,$baudrate $othbootargs;" \ 571 "tftp $loadaddr $bootfile;" \ 572 "tftp $fdtaddr $fdtfile;" \ 573 "bootm $loadaddr - $fdtaddr" 574 575 #define CONFIG_HDBOOT \ 576 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 577 "console=$consoledev,$baudrate $othbootargs;" \ 578 "usb start;" \ 579 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 580 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 581 "bootm $loadaddr - $fdtaddr" 582 583 #define CONFIG_RAMBOOTCOMMAND \ 584 "setenv bootargs root=/dev/ram rw " \ 585 "console=$consoledev,$baudrate $othbootargs; " \ 586 "tftp $ramdiskaddr $ramdiskfile;" \ 587 "tftp $loadaddr $bootfile;" \ 588 "tftp $fdtaddr $fdtfile;" \ 589 "bootm $loadaddr $ramdiskaddr $fdtaddr" 590 591 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 592 593 #include <asm/fsl_secure_boot.h> 594 595 #endif /* __CONFIG_H */ 596