xref: /openbmc/u-boot/include/configs/BSC9132QDS.h (revision 83bf0057)
1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 /*
8  * BSC9132 QDS board configuration file
9  */
10 
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 #define CONFIG_DISPLAY_BOARDINFO
15 
16 #ifdef CONFIG_BSC9132QDS
17 #define CONFIG_BSC9132
18 #endif
19 
20 #define CONFIG_MISC_INIT_R
21 
22 #ifdef CONFIG_SDCARD
23 #define CONFIG_RAMBOOT_SDCARD
24 #define CONFIG_SYS_RAMBOOT
25 #define CONFIG_SYS_EXTRA_ENV_RELOC
26 #define CONFIG_SYS_TEXT_BASE		0x11000000
27 #define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
28 #endif
29 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769	1
30 #ifdef CONFIG_SPIFLASH
31 #define CONFIG_RAMBOOT_SPIFLASH
32 #define CONFIG_SYS_RAMBOOT
33 #define CONFIG_SYS_EXTRA_ENV_RELOC
34 #define CONFIG_SYS_TEXT_BASE		0x11000000
35 #define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
36 #endif
37 #ifdef CONFIG_NAND_SECBOOT
38 #define CONFIG_RAMBOOT_NAND
39 #define CONFIG_SYS_RAMBOOT
40 #define CONFIG_SYS_EXTRA_ENV_RELOC
41 #define CONFIG_SYS_TEXT_BASE		0x11000000
42 #define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
43 #endif
44 
45 #ifdef CONFIG_NAND
46 #define CONFIG_SPL_INIT_MINIMAL
47 #define CONFIG_SPL_SERIAL_SUPPORT
48 #define CONFIG_SPL_NAND_SUPPORT
49 #define CONFIG_SPL_NAND_BOOT
50 #define CONFIG_SPL_FLUSH_IMAGE
51 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
52 
53 #define CONFIG_SYS_TEXT_BASE		0x00201000
54 #define CONFIG_SPL_TEXT_BASE		0xFFFFE000
55 #define CONFIG_SPL_MAX_SIZE		8192
56 #define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
57 #define CONFIG_SPL_RELOC_STACK		0x00100000
58 #define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
59 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
60 #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
61 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0
62 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
63 #endif
64 
65 #ifndef CONFIG_SYS_TEXT_BASE
66 #define CONFIG_SYS_TEXT_BASE		0x8ff40000
67 #endif
68 
69 #ifndef CONFIG_RESET_VECTOR_ADDRESS
70 #define CONFIG_RESET_VECTOR_ADDRESS	0x8ffffffc
71 #endif
72 
73 #ifdef CONFIG_SPL_BUILD
74 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
75 #else
76 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
77 #endif
78 
79 /* High Level Configuration Options */
80 #define CONFIG_BOOKE			/* BOOKE */
81 #define CONFIG_E500			/* BOOKE e500 family */
82 #define CONFIG_FSL_IFC			/* Enable IFC Support */
83 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
84 #define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
85 
86 #define CONFIG_PCI			/* Enable PCI/PCIE */
87 #if defined(CONFIG_PCI)
88 #define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
89 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
90 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
91 #define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
92 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
93 
94 #define CONFIG_CMD_PCI
95 
96 
97 /*
98  * PCI Windows
99  * Memory space is mapped 1-1, but I/O space must start from 0.
100  */
101 /* controller 1, Slot 1, tgtid 1, Base address a000 */
102 #define CONFIG_SYS_PCIE1_NAME		"PCIe Slot"
103 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x90000000
104 #define CONFIG_SYS_PCIE1_MEM_BUS	0x90000000
105 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x90000000
106 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
107 #define CONFIG_SYS_PCIE1_IO_VIRT	0xC0010000
108 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
109 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
110 #define CONFIG_SYS_PCIE1_IO_PHYS	0xC0010000
111 
112 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
113 
114 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
115 #define CONFIG_DOS_PARTITION
116 #endif
117 
118 #define CONFIG_FSL_LAW			/* Use common FSL init code */
119 #define CONFIG_ENV_OVERWRITE
120 #define CONFIG_TSEC_ENET /* ethernet */
121 
122 #if defined(CONFIG_SYS_CLK_100_DDR_100)
123 #define CONFIG_SYS_CLK_FREQ	100000000
124 #define CONFIG_DDR_CLK_FREQ	100000000
125 #elif defined(CONFIG_SYS_CLK_100_DDR_133)
126 #define CONFIG_SYS_CLK_FREQ	100000000
127 #define CONFIG_DDR_CLK_FREQ	133000000
128 #endif
129 
130 #define CONFIG_MP
131 
132 #define CONFIG_HWCONFIG
133 /*
134  * These can be toggled for performance analysis, otherwise use default.
135  */
136 #define CONFIG_L2_CACHE			/* toggle L2 cache */
137 #define CONFIG_BTB			/* enable branch predition */
138 
139 #define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
140 #define CONFIG_SYS_MEMTEST_END		0x01ffffff
141 
142 /* DDR Setup */
143 #define CONFIG_SYS_FSL_DDR3
144 #define CONFIG_SYS_SPD_BUS_NUM		0
145 #define SPD_EEPROM_ADDRESS1		0x54 /* I2C access */
146 #define SPD_EEPROM_ADDRESS2		0x56 /* I2C access */
147 #define CONFIG_FSL_DDR_INTERACTIVE
148 
149 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
150 
151 #define CONFIG_SYS_SDRAM_SIZE		(1024)
152 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
153 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
154 
155 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
156 
157 /* DDR3 Controller Settings */
158 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
159 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
160 #define CONFIG_SYS_DDR_CS0_CONFIG_1333	0x80004302
161 #define CONFIG_SYS_DDR_CS0_CONFIG_800	0x80014302
162 #define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
163 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
164 #define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
165 #define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
166 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
167 #define CONFIG_SYS_DDR1_CS0_BNDS       0x0040007F
168 
169 #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
170 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
171 #define CONFIG_SYS_DDR_RCW_1		0x00000000
172 #define CONFIG_SYS_DDR_RCW_2		0x00000000
173 #define CONFIG_SYS_DDR_CONTROL_800		0x470C0000
174 #define CONFIG_SYS_DDR_CONTROL_2_800	0x04401050
175 #define CONFIG_SYS_DDR_TIMING_4_800		0x00220001
176 #define CONFIG_SYS_DDR_TIMING_5_800		0x03402400
177 
178 #define CONFIG_SYS_DDR_CONTROL_1333		0x470C0008
179 #define CONFIG_SYS_DDR_CONTROL_2_1333	0x24401010
180 #define CONFIG_SYS_DDR_TIMING_4_1333		0x00000001
181 #define CONFIG_SYS_DDR_TIMING_5_1333		0x03401400
182 
183 #define CONFIG_SYS_DDR_TIMING_3_800		0x00020000
184 #define CONFIG_SYS_DDR_TIMING_0_800		0x00330004
185 #define CONFIG_SYS_DDR_TIMING_1_800		0x6f6B4846
186 #define CONFIG_SYS_DDR_TIMING_2_800		0x0FA8C8CF
187 #define CONFIG_SYS_DDR_CLK_CTRL_800		0x03000000
188 #define CONFIG_SYS_DDR_MODE_1_800		0x40461520
189 #define CONFIG_SYS_DDR_MODE_2_800		0x8000c000
190 #define CONFIG_SYS_DDR_INTERVAL_800		0x0C300000
191 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800	0x8655A608
192 
193 #define CONFIG_SYS_DDR_TIMING_3_1333		0x01061000
194 #define CONFIG_SYS_DDR_TIMING_0_1333		0x00440104
195 #define CONFIG_SYS_DDR_TIMING_1_1333		0x98913A45
196 #define CONFIG_SYS_DDR_TIMING_2_1333		0x0FB8B114
197 #define CONFIG_SYS_DDR_CLK_CTRL_1333		0x02800000
198 #define CONFIG_SYS_DDR_MODE_1_1333		0x00061A50
199 #define CONFIG_SYS_DDR_MODE_2_1333		0x00100000
200 #define CONFIG_SYS_DDR_INTERVAL_1333		0x144E0513
201 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333	0x8655F607
202 
203 /*FIXME: the following params are constant w.r.t diff freq
204 combinations. this should be removed later
205 */
206 #if CONFIG_DDR_CLK_FREQ == 100000000
207 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
208 #define CONFIG_SYS_DDR_CONTROL		CONFIG_SYS_DDR_CONTROL_800
209 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
210 #define CONFIG_SYS_DDR_TIMING_4	CONFIG_SYS_DDR_TIMING_4_800
211 #define CONFIG_SYS_DDR_TIMING_5	CONFIG_SYS_DDR_TIMING_5_800
212 #elif CONFIG_DDR_CLK_FREQ == 133000000
213 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
214 #define CONFIG_SYS_DDR_CONTROL		CONFIG_SYS_DDR_CONTROL_1333
215 #define CONFIG_SYS_DDR_CONTROL_2	CONFIG_SYS_DDR_CONTROL_2_1333
216 #define CONFIG_SYS_DDR_TIMING_4	CONFIG_SYS_DDR_TIMING_4_1333
217 #define CONFIG_SYS_DDR_TIMING_5	CONFIG_SYS_DDR_TIMING_5_1333
218 #else
219 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
220 #define CONFIG_SYS_DDR_CONTROL		CONFIG_SYS_DDR_CONTROL_800
221 #define CONFIG_SYS_DDR_CONTROL_2	CONFIG_SYS_DDR_CONTROL_2_800
222 #define CONFIG_SYS_DDR_TIMING_4	CONFIG_SYS_DDR_TIMING_4_800
223 #define CONFIG_SYS_DDR_TIMING_5	CONFIG_SYS_DDR_TIMING_5_800
224 #endif
225 
226 
227 /* relocated CCSRBAR */
228 #define CONFIG_SYS_CCSRBAR	CONFIG_SYS_CCSRBAR_DEFAULT
229 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR_DEFAULT
230 
231 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR
232 
233 /* DSP CCSRBAR */
234 #define CONFIG_SYS_FSL_DSP_CCSRBAR	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
235 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
236 
237 /*
238  * IFC Definitions
239  */
240 /* NOR Flash on IFC */
241 
242 #ifdef CONFIG_SPL_BUILD
243 #define CONFIG_SYS_NO_FLASH
244 #endif
245 #define CONFIG_SYS_FLASH_BASE		0x88000000
246 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* Max number of sector: 32M */
247 
248 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
249 
250 #define CONFIG_SYS_NOR_CSPR	0x88000101
251 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
252 #define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(5)
253 /* NOR Flash Timing Params */
254 
255 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x01) \
256 				| FTIM0_NOR_TEADC(0x03) \
257 				| FTIM0_NOR_TAVDS(0x00) \
258 				| FTIM0_NOR_TEAHC(0x0f))
259 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1d) \
260 				| FTIM1_NOR_TRAD_NOR(0x09) \
261 				| FTIM1_NOR_TSEQRAD_NOR(0x09))
262 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x1) \
263 				| FTIM2_NOR_TCH(0x4) \
264 				| FTIM2_NOR_TWPH(0x7) \
265 				| FTIM2_NOR_TWP(0x1e))
266 #define CONFIG_SYS_NOR_FTIM3	0x0
267 
268 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
269 #define CONFIG_SYS_FLASH_QUIET_TEST
270 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
271 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
272 
273 #undef CONFIG_SYS_FLASH_CHECKSUM
274 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
275 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
276 
277 /* CFI for NOR Flash */
278 #define CONFIG_FLASH_CFI_DRIVER
279 #define CONFIG_SYS_FLASH_CFI
280 #define CONFIG_SYS_FLASH_EMPTY_INFO
281 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
282 
283 /* NAND Flash on IFC */
284 #define CONFIG_SYS_NAND_BASE		0xff800000
285 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
286 
287 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
288 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
289 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
290 				| CSPR_V)
291 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
292 
293 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
294 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
295 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
296 				| CSOR_NAND_RAL_2	/* RAL = 2Byes */ \
297 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
298 				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
299 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
300 
301 /* NAND Flash Timing Params */
302 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x03) \
303 					| FTIM0_NAND_TWP(0x05) \
304 					| FTIM0_NAND_TWCHT(0x02) \
305 					| FTIM0_NAND_TWH(0x04))
306 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1c) \
307 					| FTIM1_NAND_TWBE(0x1e) \
308 					| FTIM1_NAND_TRR(0x07) \
309 					| FTIM1_NAND_TRP(0x05))
310 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x08) \
311 					| FTIM2_NAND_TREH(0x04) \
312 					| FTIM2_NAND_TWHRE(0x11))
313 #define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
314 
315 #define CONFIG_SYS_NAND_DDR_LAW		11
316 
317 /* NAND */
318 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
319 #define CONFIG_SYS_MAX_NAND_DEVICE	1
320 #define CONFIG_CMD_NAND
321 
322 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
323 
324 #ifndef CONFIG_SPL_BUILD
325 #define CONFIG_FSL_QIXIS
326 #endif
327 #ifdef CONFIG_FSL_QIXIS
328 #define CONFIG_SYS_FPGA_BASE	0xffb00000
329 #define CONFIG_SYS_I2C_FPGA_ADDR	0x66
330 #define QIXIS_BASE	CONFIG_SYS_FPGA_BASE
331 #define QIXIS_LBMAP_SWITCH	9
332 #define QIXIS_LBMAP_MASK	0x07
333 #define QIXIS_LBMAP_SHIFT	0
334 #define QIXIS_LBMAP_DFLTBANK		0x00
335 #define QIXIS_LBMAP_ALTBANK		0x04
336 #define QIXIS_RST_CTL_RESET		0x83
337 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
338 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
339 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
340 
341 #define CONFIG_SYS_FPGA_BASE_PHYS	CONFIG_SYS_FPGA_BASE
342 
343 #define CONFIG_SYS_CSPR2		(CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
344 					| CSPR_PORT_SIZE_8 \
345 					| CSPR_MSEL_GPCM \
346 					| CSPR_V)
347 #define CONFIG_SYS_AMASK2		IFC_AMASK(64*1024)
348 #define CONFIG_SYS_CSOR2		0x0
349 /* CPLD Timing parameters for IFC CS3 */
350 #define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
351 					FTIM0_GPCM_TEADC(0x0e) | \
352 					FTIM0_GPCM_TEAHC(0x0e))
353 #define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
354 					FTIM1_GPCM_TRAD(0x1f))
355 #define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
356 					FTIM2_GPCM_TCH(0x8) | \
357 					FTIM2_GPCM_TWP(0x1f))
358 #define CONFIG_SYS_CS2_FTIM3		0x0
359 #endif
360 
361 /* Set up IFC registers for boot location NOR/NAND */
362 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
363 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
364 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
365 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
366 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
367 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
368 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
369 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
370 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
371 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
372 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
373 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
374 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
375 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
376 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
377 #else
378 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
379 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
380 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
381 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
382 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
383 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
384 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
385 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
386 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
387 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
388 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
389 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
390 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
391 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
392 #endif
393 
394 #define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
395 #define CONFIG_BOARD_EARLY_INIT_R
396 
397 #define CONFIG_SYS_INIT_RAM_LOCK
398 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* stack in RAM */
399 #define CONFIG_SYS_INIT_RAM_END		0x00004000 /* End of used area in RAM */
400 
401 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
402 						- GENERATED_GBL_DATA_SIZE)
403 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
404 
405 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
406 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
407 
408 /* Serial Port */
409 #define CONFIG_CONS_INDEX	1
410 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
411 #define CONFIG_SYS_NS16550
412 #define CONFIG_SYS_NS16550_SERIAL
413 #define CONFIG_SYS_NS16550_REG_SIZE	1
414 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
415 #ifdef CONFIG_SPL_BUILD
416 #define CONFIG_NS16550_MIN_FUNCTIONS
417 #endif
418 
419 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
420 
421 #define CONFIG_SYS_BAUDRATE_TABLE	\
422 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
423 
424 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
425 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
426 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR + 0x4700)
427 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR + 0x4800)
428 
429 /* Use the HUSH parser */
430 #define CONFIG_SYS_HUSH_PARSER    /* hush parser */
431 #ifdef	CONFIG_SYS_HUSH_PARSER
432 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
433 #endif
434 
435 /*
436  * Pass open firmware flat tree
437  */
438 #define CONFIG_OF_LIBFDT
439 #define CONFIG_OF_BOARD_SETUP
440 #define CONFIG_OF_STDOUT_VIA_ALIAS
441 
442 /* new uImage format support */
443 #define CONFIG_FIT
444 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
445 
446 #define CONFIG_SYS_I2C
447 #define CONFIG_SYS_I2C_FSL
448 #define CONFIG_SYS_FSL_I2C_SPEED	400800 /* I2C speed and slave address*/
449 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
450 #define CONFIG_SYS_FSL_I2C2_SPEED	400800 /* I2C speed and slave address*/
451 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
452 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
453 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
454 
455 /* I2C EEPROM */
456 #define CONFIG_ID_EEPROM
457 #ifdef CONFIG_ID_EEPROM
458 #define CONFIG_SYS_I2C_EEPROM_NXID
459 #endif
460 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
461 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
462 #define CONFIG_SYS_EEPROM_BUS_NUM	0
463 
464 /* enable read and write access to EEPROM */
465 #define CONFIG_CMD_EEPROM
466 #define CONFIG_SYS_I2C_MULTI_EEPROMS
467 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
468 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
469 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
470 
471 /* I2C FPGA */
472 #define CONFIG_I2C_FPGA
473 #define CONFIG_SYS_I2C_FPGA_ADDR	0x66
474 
475 #define CONFIG_RTC_DS3231
476 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
477 
478 /*
479  * SPI interface will not be available in case of NAND boot SPI CS0 will be
480  * used for SLIC
481  */
482 /* eSPI - Enhanced SPI */
483 #define CONFIG_FSL_ESPI  /* SPI */
484 #ifdef CONFIG_FSL_ESPI
485 #define CONFIG_SPI_FLASH_SPANSION
486 #define CONFIG_CMD_SF
487 #define CONFIG_SF_DEFAULT_SPEED		10000000
488 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
489 #endif
490 
491 #if defined(CONFIG_TSEC_ENET)
492 
493 #define CONFIG_MII			/* MII PHY management */
494 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
495 #define CONFIG_TSEC1	1
496 #define CONFIG_TSEC1_NAME	"eTSEC1"
497 #define CONFIG_TSEC2	1
498 #define CONFIG_TSEC2_NAME	"eTSEC2"
499 
500 #define TSEC1_PHY_ADDR		0
501 #define TSEC2_PHY_ADDR		1
502 
503 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
504 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
505 
506 #define TSEC1_PHYIDX		0
507 #define TSEC2_PHYIDX		0
508 
509 #define CONFIG_ETHPRIME		"eTSEC1"
510 
511 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
512 
513 /* TBI PHY configuration for SGMII mode */
514 #define CONFIG_TSEC_TBICR_SETTINGS ( \
515 		TBICR_PHY_RESET \
516 		| TBICR_ANEG_ENABLE \
517 		| TBICR_FULL_DUPLEX \
518 		| TBICR_SPEED1_SET \
519 		)
520 
521 #endif	/* CONFIG_TSEC_ENET */
522 
523 #define CONFIG_MMC
524 #ifdef CONFIG_MMC
525 #define CONFIG_CMD_MMC
526 #define CONFIG_DOS_PARTITION
527 #define CONFIG_FSL_ESDHC
528 #define CONFIG_GENERIC_MMC
529 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
530 #endif
531 
532 #define CONFIG_USB_EHCI  /* USB */
533 #ifdef CONFIG_USB_EHCI
534 #define CONFIG_CMD_USB
535 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
536 #define CONFIG_USB_EHCI_FSL
537 #define CONFIG_USB_STORAGE
538 #define CONFIG_HAS_FSL_DR_USB
539 #endif
540 
541 /*
542  * Environment
543  */
544 #if defined(CONFIG_RAMBOOT_SDCARD)
545 #define CONFIG_ENV_IS_IN_MMC
546 #define CONFIG_FSL_FIXED_MMC_LOCATION
547 #define CONFIG_SYS_MMC_ENV_DEV		0
548 #define CONFIG_ENV_SIZE			0x2000
549 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
550 #define CONFIG_ENV_IS_IN_SPI_FLASH
551 #define CONFIG_ENV_SPI_BUS	0
552 #define CONFIG_ENV_SPI_CS	0
553 #define CONFIG_ENV_SPI_MAX_HZ	10000000
554 #define CONFIG_ENV_SPI_MODE	0
555 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
556 #define CONFIG_ENV_SECT_SIZE	0x10000
557 #define CONFIG_ENV_SIZE		0x2000
558 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
559 #define CONFIG_ENV_IS_IN_NAND
560 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
561 #define CONFIG_ENV_OFFSET	((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
562 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
563 #elif defined(CONFIG_SYS_RAMBOOT)
564 #define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
565 #define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
566 #define CONFIG_ENV_SIZE			0x2000
567 #else
568 #define CONFIG_ENV_IS_IN_FLASH
569 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
570 #define CONFIG_ENV_SIZE		0x2000
571 #define CONFIG_ENV_SECT_SIZE	0x20000
572 #endif
573 
574 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
575 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
576 
577 /*
578  * Command line configuration.
579  */
580 #define CONFIG_CMD_DATE
581 #define CONFIG_CMD_DHCP
582 #define CONFIG_CMD_ERRATA
583 #define CONFIG_CMD_I2C
584 #define CONFIG_CMD_IRQ
585 #define CONFIG_CMD_MII
586 #define CONFIG_CMD_PING
587 #define CONFIG_CMD_REGINFO
588 
589 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
590 #define CONFIG_CMD_EXT2
591 #define CONFIG_CMD_FAT
592 #define CONFIG_DOS_PARTITION
593 #endif
594 
595 /* Hash command with SHA acceleration supported in hardware */
596 #ifdef CONFIG_FSL_CAAM
597 #define CONFIG_CMD_HASH
598 #define CONFIG_SHA_HW_ACCEL
599 #endif
600 
601 /*
602  * Miscellaneous configurable options
603  */
604 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
605 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
606 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
607 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
608 
609 #if defined(CONFIG_CMD_KGDB)
610 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
611 #else
612 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
613 #endif
614 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
615 						/* Print Buffer Size */
616 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
617 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
618 
619 
620 /*
621  * For booting Linux, the board info and command line data
622  * have to be in the first 64 MB of memory, since this is
623  * the maximum mapped by the Linux kernel during initialization.
624  */
625 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
626 #define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
627 
628 #if defined(CONFIG_CMD_KGDB)
629 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
630 #endif
631 
632 /*
633  * Dynamic MTD Partition support with mtdparts
634  */
635 #ifndef CONFIG_SYS_NO_FLASH
636 #define CONFIG_MTD_DEVICE
637 #define CONFIG_MTD_PARTITIONS
638 #define CONFIG_CMD_MTDPARTS
639 #define CONFIG_FLASH_CFI_MTD
640 #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash,"
641 #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \
642 			"55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \
643 			"8m(kernel),512k(dtb),-(fs)"
644 #endif
645 /*
646  * Override partitions in device tree using info
647  * in "mtdparts" environment variable
648  */
649 #ifdef CONFIG_CMD_MTDPARTS
650 #define CONFIG_FDT_FIXUP_PARTITIONS
651 #endif
652 
653 /*
654  * Environment Configuration
655  */
656 
657 #if defined(CONFIG_TSEC_ENET)
658 #define CONFIG_HAS_ETH0
659 #define CONFIG_HAS_ETH1
660 #endif
661 
662 #define CONFIG_HOSTNAME		BSC9132qds
663 #define CONFIG_ROOTPATH		"/opt/nfsroot"
664 #define CONFIG_BOOTFILE		"uImage"
665 #define CONFIG_UBOOTPATH	"u-boot.bin"
666 
667 #define CONFIG_BAUDRATE		115200
668 #define CONFIG_BOOTDELAY	10 /* -1 disable auto-boot */
669 
670 #ifdef CONFIG_SDCARD
671 #define CONFIG_DEF_HWCONFIG	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
672 #else
673 #define CONFIG_DEF_HWCONFIG	"hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
674 #endif
675 
676 #define	CONFIG_EXTRA_ENV_SETTINGS				\
677 	"netdev=eth0\0"						\
678 	"uboot=" CONFIG_UBOOTPATH "\0"				\
679 	"loadaddr=1000000\0"			\
680 	"bootfile=uImage\0"	\
681 	"consoledev=ttyS0\0"				\
682 	"ramdiskaddr=2000000\0"			\
683 	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
684 	"fdtaddr=c00000\0"				\
685 	"fdtfile=bsc9132qds.dtb\0"		\
686 	"bdev=sda1\0"	\
687 	CONFIG_DEF_HWCONFIG\
688 	"othbootargs=mem=880M ramdisk_size=600000 " \
689 		"default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
690 		"isolcpus=0\0" \
691 	"usbext2boot=setenv bootargs root=/dev/ram rw "	\
692 		"console=$consoledev,$baudrate $othbootargs; "	\
693 		"usb start;"			\
694 		"ext2load usb 0:4 $loadaddr $bootfile;"		\
695 		"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
696 		"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
697 		"bootm $loadaddr $ramdiskaddr $fdtaddr\0"	\
698 	"debug_halt_off=mw ff7e0e30 0xf0000000;"
699 
700 #define CONFIG_NFSBOOTCOMMAND	\
701 	"setenv bootargs root=/dev/nfs rw "	\
702 	"nfsroot=$serverip:$rootpath "	\
703 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
704 	"console=$consoledev,$baudrate $othbootargs;" \
705 	"tftp $loadaddr $bootfile;"	\
706 	"tftp $fdtaddr $fdtfile;"	\
707 	"bootm $loadaddr - $fdtaddr"
708 
709 #define CONFIG_HDBOOT	\
710 	"setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
711 	"console=$consoledev,$baudrate $othbootargs;" \
712 	"usb start;"	\
713 	"ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
714 	"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
715 	"bootm $loadaddr - $fdtaddr"
716 
717 #define CONFIG_RAMBOOTCOMMAND		\
718 	"setenv bootargs root=/dev/ram rw "	\
719 	"console=$consoledev,$baudrate $othbootargs; "	\
720 	"tftp $ramdiskaddr $ramdiskfile;"	\
721 	"tftp $loadaddr $bootfile;"		\
722 	"tftp $fdtaddr $fdtfile;"		\
723 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
724 
725 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
726 
727 #include <asm/fsl_secure_boot.h>
728 
729 #ifdef CONFIG_SECURE_BOOT
730 #define CONFIG_CMD_BLOB
731 #endif
732 
733 #endif	/* __CONFIG_H */
734