1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9132 QDS board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_BSC9132QDS 15 #define CONFIG_BSC9132 16 #endif 17 18 #define CONFIG_MISC_INIT_R 19 20 #ifdef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_SDCARD 22 #define CONFIG_SYS_RAMBOOT 23 #define CONFIG_SYS_EXTRA_ENV_RELOC 24 #define CONFIG_SYS_TEXT_BASE 0x11000000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 26 #endif 27 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 28 #ifdef CONFIG_SPIFLASH 29 #define CONFIG_RAMBOOT_SPIFLASH 30 #define CONFIG_SYS_RAMBOOT 31 #define CONFIG_SYS_EXTRA_ENV_RELOC 32 #define CONFIG_SYS_TEXT_BASE 0x11000000 33 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 34 #endif 35 #ifdef CONFIG_NAND_SECBOOT 36 #define CONFIG_RAMBOOT_NAND 37 #define CONFIG_SYS_RAMBOOT 38 #define CONFIG_SYS_EXTRA_ENV_RELOC 39 #define CONFIG_SYS_TEXT_BASE 0x11000000 40 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 41 #endif 42 43 #ifdef CONFIG_NAND 44 #define CONFIG_SPL_INIT_MINIMAL 45 #define CONFIG_SPL_NAND_BOOT 46 #define CONFIG_SPL_FLUSH_IMAGE 47 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 48 49 #define CONFIG_SYS_TEXT_BASE 0x00201000 50 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 51 #define CONFIG_SPL_MAX_SIZE 8192 52 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 53 #define CONFIG_SPL_RELOC_STACK 0x00100000 54 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 55 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 56 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 57 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 58 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 59 #endif 60 61 #ifndef CONFIG_SYS_TEXT_BASE 62 #define CONFIG_SYS_TEXT_BASE 0x8ff40000 63 #endif 64 65 #ifndef CONFIG_RESET_VECTOR_ADDRESS 66 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 67 #endif 68 69 #ifdef CONFIG_SPL_BUILD 70 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 71 #else 72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 73 #endif 74 75 /* High Level Configuration Options */ 76 #define CONFIG_BOOKE /* BOOKE */ 77 #define CONFIG_E500 /* BOOKE e500 family */ 78 #define CONFIG_FSL_IFC /* Enable IFC Support */ 79 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 80 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 81 82 #if defined(CONFIG_PCI) 83 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 84 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 85 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 86 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 87 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 88 89 #define CONFIG_CMD_PCI 90 91 /* 92 * PCI Windows 93 * Memory space is mapped 1-1, but I/O space must start from 0. 94 */ 95 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 96 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 97 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 98 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 99 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 100 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 101 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 102 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 103 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 104 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 105 106 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 107 #define CONFIG_DOS_PARTITION 108 #endif 109 110 #define CONFIG_FSL_LAW /* Use common FSL init code */ 111 #define CONFIG_ENV_OVERWRITE 112 #define CONFIG_TSEC_ENET /* ethernet */ 113 114 #if defined(CONFIG_SYS_CLK_100_DDR_100) 115 #define CONFIG_SYS_CLK_FREQ 100000000 116 #define CONFIG_DDR_CLK_FREQ 100000000 117 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 118 #define CONFIG_SYS_CLK_FREQ 100000000 119 #define CONFIG_DDR_CLK_FREQ 133000000 120 #endif 121 122 #define CONFIG_MP 123 124 #define CONFIG_HWCONFIG 125 /* 126 * These can be toggled for performance analysis, otherwise use default. 127 */ 128 #define CONFIG_L2_CACHE /* toggle L2 cache */ 129 #define CONFIG_BTB /* enable branch predition */ 130 131 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 132 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 133 134 /* DDR Setup */ 135 #define CONFIG_SYS_FSL_DDR3 136 #define CONFIG_SYS_SPD_BUS_NUM 0 137 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 138 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 139 #define CONFIG_FSL_DDR_INTERACTIVE 140 141 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 142 143 #define CONFIG_SYS_SDRAM_SIZE (1024) 144 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 145 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 146 147 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 148 149 /* DDR3 Controller Settings */ 150 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 151 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 152 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 153 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 154 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 155 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 156 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 157 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 158 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 159 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 160 161 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 162 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 163 #define CONFIG_SYS_DDR_RCW_1 0x00000000 164 #define CONFIG_SYS_DDR_RCW_2 0x00000000 165 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 166 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 167 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 168 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 169 170 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 171 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 172 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 173 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 174 175 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 176 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 177 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 178 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 179 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 180 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 181 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 182 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 183 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 184 185 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 186 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 187 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 188 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 189 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 190 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 191 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 192 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 193 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 194 195 /*FIXME: the following params are constant w.r.t diff freq 196 combinations. this should be removed later 197 */ 198 #if CONFIG_DDR_CLK_FREQ == 100000000 199 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 200 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 201 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 202 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 203 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 204 #elif CONFIG_DDR_CLK_FREQ == 133000000 205 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 206 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 207 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 208 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 209 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 210 #else 211 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 212 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 213 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 214 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 215 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 216 #endif 217 218 /* relocated CCSRBAR */ 219 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 220 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 221 222 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 223 224 /* DSP CCSRBAR */ 225 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 226 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 227 228 /* 229 * IFC Definitions 230 */ 231 /* NOR Flash on IFC */ 232 233 #ifdef CONFIG_SPL_BUILD 234 #define CONFIG_SYS_NO_FLASH 235 #endif 236 #define CONFIG_SYS_FLASH_BASE 0x88000000 237 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 238 239 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 240 241 #define CONFIG_SYS_NOR_CSPR 0x88000101 242 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 243 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 244 /* NOR Flash Timing Params */ 245 246 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 247 | FTIM0_NOR_TEADC(0x03) \ 248 | FTIM0_NOR_TAVDS(0x00) \ 249 | FTIM0_NOR_TEAHC(0x0f)) 250 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 251 | FTIM1_NOR_TRAD_NOR(0x09) \ 252 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 253 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 254 | FTIM2_NOR_TCH(0x4) \ 255 | FTIM2_NOR_TWPH(0x7) \ 256 | FTIM2_NOR_TWP(0x1e)) 257 #define CONFIG_SYS_NOR_FTIM3 0x0 258 259 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 260 #define CONFIG_SYS_FLASH_QUIET_TEST 261 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 262 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 263 264 #undef CONFIG_SYS_FLASH_CHECKSUM 265 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 266 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 267 268 /* CFI for NOR Flash */ 269 #define CONFIG_FLASH_CFI_DRIVER 270 #define CONFIG_SYS_FLASH_CFI 271 #define CONFIG_SYS_FLASH_EMPTY_INFO 272 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 273 274 /* NAND Flash on IFC */ 275 #define CONFIG_SYS_NAND_BASE 0xff800000 276 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 277 278 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 279 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 280 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 281 | CSPR_V) 282 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 283 284 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 285 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 286 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 287 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 288 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 289 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 290 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 291 292 /* NAND Flash Timing Params */ 293 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 294 | FTIM0_NAND_TWP(0x05) \ 295 | FTIM0_NAND_TWCHT(0x02) \ 296 | FTIM0_NAND_TWH(0x04)) 297 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 298 | FTIM1_NAND_TWBE(0x1e) \ 299 | FTIM1_NAND_TRR(0x07) \ 300 | FTIM1_NAND_TRP(0x05)) 301 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 302 | FTIM2_NAND_TREH(0x04) \ 303 | FTIM2_NAND_TWHRE(0x11)) 304 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 305 306 #define CONFIG_SYS_NAND_DDR_LAW 11 307 308 /* NAND */ 309 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 310 #define CONFIG_SYS_MAX_NAND_DEVICE 1 311 #define CONFIG_CMD_NAND 312 313 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 314 315 #ifndef CONFIG_SPL_BUILD 316 #define CONFIG_FSL_QIXIS 317 #endif 318 #ifdef CONFIG_FSL_QIXIS 319 #define CONFIG_SYS_FPGA_BASE 0xffb00000 320 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 321 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 322 #define QIXIS_LBMAP_SWITCH 9 323 #define QIXIS_LBMAP_MASK 0x07 324 #define QIXIS_LBMAP_SHIFT 0 325 #define QIXIS_LBMAP_DFLTBANK 0x00 326 #define QIXIS_LBMAP_ALTBANK 0x04 327 #define QIXIS_RST_CTL_RESET 0x83 328 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 329 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 330 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 331 332 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 333 334 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 335 | CSPR_PORT_SIZE_8 \ 336 | CSPR_MSEL_GPCM \ 337 | CSPR_V) 338 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 339 #define CONFIG_SYS_CSOR2 0x0 340 /* CPLD Timing parameters for IFC CS3 */ 341 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 342 FTIM0_GPCM_TEADC(0x0e) | \ 343 FTIM0_GPCM_TEAHC(0x0e)) 344 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 345 FTIM1_GPCM_TRAD(0x1f)) 346 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 347 FTIM2_GPCM_TCH(0x8) | \ 348 FTIM2_GPCM_TWP(0x1f)) 349 #define CONFIG_SYS_CS2_FTIM3 0x0 350 #endif 351 352 /* Set up IFC registers for boot location NOR/NAND */ 353 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 354 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 355 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 356 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 357 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 358 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 359 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 360 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 361 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 362 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 363 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 364 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 365 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 366 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 367 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 368 #else 369 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 370 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 371 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 372 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 373 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 374 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 375 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 376 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 377 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 378 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 379 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 380 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 381 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 382 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 383 #endif 384 385 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 386 #define CONFIG_BOARD_EARLY_INIT_R 387 388 #define CONFIG_SYS_INIT_RAM_LOCK 389 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 390 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 391 392 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 393 - GENERATED_GBL_DATA_SIZE) 394 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 395 396 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 397 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 398 399 /* Serial Port */ 400 #define CONFIG_CONS_INDEX 1 401 #undef CONFIG_SERIAL_SOFTWARE_FIFO 402 #define CONFIG_SYS_NS16550_SERIAL 403 #define CONFIG_SYS_NS16550_REG_SIZE 1 404 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 405 #ifdef CONFIG_SPL_BUILD 406 #define CONFIG_NS16550_MIN_FUNCTIONS 407 #endif 408 409 #define CONFIG_SYS_BAUDRATE_TABLE \ 410 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 411 412 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 413 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 414 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 415 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 416 417 #define CONFIG_SYS_I2C 418 #define CONFIG_SYS_I2C_FSL 419 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 420 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 421 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 422 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 423 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 424 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 425 426 /* I2C EEPROM */ 427 #define CONFIG_ID_EEPROM 428 #ifdef CONFIG_ID_EEPROM 429 #define CONFIG_SYS_I2C_EEPROM_NXID 430 #endif 431 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 432 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 433 #define CONFIG_SYS_EEPROM_BUS_NUM 0 434 435 /* enable read and write access to EEPROM */ 436 #define CONFIG_CMD_EEPROM 437 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 438 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 439 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 440 441 /* I2C FPGA */ 442 #define CONFIG_I2C_FPGA 443 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 444 445 #define CONFIG_RTC_DS3231 446 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 447 448 /* 449 * SPI interface will not be available in case of NAND boot SPI CS0 will be 450 * used for SLIC 451 */ 452 /* eSPI - Enhanced SPI */ 453 #ifdef CONFIG_FSL_ESPI 454 #define CONFIG_SF_DEFAULT_SPEED 10000000 455 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 456 #endif 457 458 #if defined(CONFIG_TSEC_ENET) 459 460 #define CONFIG_MII /* MII PHY management */ 461 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 462 #define CONFIG_TSEC1 1 463 #define CONFIG_TSEC1_NAME "eTSEC1" 464 #define CONFIG_TSEC2 1 465 #define CONFIG_TSEC2_NAME "eTSEC2" 466 467 #define TSEC1_PHY_ADDR 0 468 #define TSEC2_PHY_ADDR 1 469 470 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 471 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 472 473 #define TSEC1_PHYIDX 0 474 #define TSEC2_PHYIDX 0 475 476 #define CONFIG_ETHPRIME "eTSEC1" 477 478 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 479 480 /* TBI PHY configuration for SGMII mode */ 481 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 482 TBICR_PHY_RESET \ 483 | TBICR_ANEG_ENABLE \ 484 | TBICR_FULL_DUPLEX \ 485 | TBICR_SPEED1_SET \ 486 ) 487 488 #endif /* CONFIG_TSEC_ENET */ 489 490 #define CONFIG_MMC 491 #ifdef CONFIG_MMC 492 #define CONFIG_DOS_PARTITION 493 #define CONFIG_FSL_ESDHC 494 #define CONFIG_GENERIC_MMC 495 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 496 #endif 497 498 #define CONFIG_USB_EHCI /* USB */ 499 #ifdef CONFIG_USB_EHCI 500 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 501 #define CONFIG_USB_EHCI_FSL 502 #define CONFIG_HAS_FSL_DR_USB 503 #endif 504 505 /* 506 * Environment 507 */ 508 #if defined(CONFIG_RAMBOOT_SDCARD) 509 #define CONFIG_ENV_IS_IN_MMC 510 #define CONFIG_FSL_FIXED_MMC_LOCATION 511 #define CONFIG_SYS_MMC_ENV_DEV 0 512 #define CONFIG_ENV_SIZE 0x2000 513 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 514 #define CONFIG_ENV_IS_IN_SPI_FLASH 515 #define CONFIG_ENV_SPI_BUS 0 516 #define CONFIG_ENV_SPI_CS 0 517 #define CONFIG_ENV_SPI_MAX_HZ 10000000 518 #define CONFIG_ENV_SPI_MODE 0 519 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 520 #define CONFIG_ENV_SECT_SIZE 0x10000 521 #define CONFIG_ENV_SIZE 0x2000 522 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 523 #define CONFIG_ENV_IS_IN_NAND 524 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 525 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 526 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 527 #elif defined(CONFIG_SYS_RAMBOOT) 528 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 529 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 530 #define CONFIG_ENV_SIZE 0x2000 531 #else 532 #define CONFIG_ENV_IS_IN_FLASH 533 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 534 #define CONFIG_ENV_SIZE 0x2000 535 #define CONFIG_ENV_SECT_SIZE 0x20000 536 #endif 537 538 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 539 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 540 541 /* 542 * Command line configuration. 543 */ 544 #define CONFIG_CMD_DATE 545 #define CONFIG_CMD_ERRATA 546 #define CONFIG_CMD_IRQ 547 #define CONFIG_CMD_REGINFO 548 549 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 550 #define CONFIG_DOS_PARTITION 551 #endif 552 553 /* Hash command with SHA acceleration supported in hardware */ 554 #ifdef CONFIG_FSL_CAAM 555 #define CONFIG_CMD_HASH 556 #define CONFIG_SHA_HW_ACCEL 557 #endif 558 559 /* 560 * Miscellaneous configurable options 561 */ 562 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 563 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 564 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 565 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 566 567 #if defined(CONFIG_CMD_KGDB) 568 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 569 #else 570 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 571 #endif 572 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 573 /* Print Buffer Size */ 574 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 575 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 576 577 /* 578 * For booting Linux, the board info and command line data 579 * have to be in the first 64 MB of memory, since this is 580 * the maximum mapped by the Linux kernel during initialization. 581 */ 582 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 583 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 584 585 #if defined(CONFIG_CMD_KGDB) 586 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 587 #endif 588 589 /* 590 * Dynamic MTD Partition support with mtdparts 591 */ 592 #ifndef CONFIG_SYS_NO_FLASH 593 #define CONFIG_MTD_DEVICE 594 #define CONFIG_MTD_PARTITIONS 595 #define CONFIG_CMD_MTDPARTS 596 #define CONFIG_FLASH_CFI_MTD 597 #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," 598 #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ 599 "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ 600 "8m(kernel),512k(dtb),-(fs)" 601 #endif 602 /* 603 * Environment Configuration 604 */ 605 606 #if defined(CONFIG_TSEC_ENET) 607 #define CONFIG_HAS_ETH0 608 #define CONFIG_HAS_ETH1 609 #endif 610 611 #define CONFIG_HOSTNAME BSC9132qds 612 #define CONFIG_ROOTPATH "/opt/nfsroot" 613 #define CONFIG_BOOTFILE "uImage" 614 #define CONFIG_UBOOTPATH "u-boot.bin" 615 616 #define CONFIG_BAUDRATE 115200 617 618 #ifdef CONFIG_SDCARD 619 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 620 #else 621 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 622 #endif 623 624 #define CONFIG_EXTRA_ENV_SETTINGS \ 625 "netdev=eth0\0" \ 626 "uboot=" CONFIG_UBOOTPATH "\0" \ 627 "loadaddr=1000000\0" \ 628 "bootfile=uImage\0" \ 629 "consoledev=ttyS0\0" \ 630 "ramdiskaddr=2000000\0" \ 631 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 632 "fdtaddr=1e00000\0" \ 633 "fdtfile=bsc9132qds.dtb\0" \ 634 "bdev=sda1\0" \ 635 CONFIG_DEF_HWCONFIG\ 636 "othbootargs=mem=880M ramdisk_size=600000 " \ 637 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 638 "isolcpus=0\0" \ 639 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 640 "console=$consoledev,$baudrate $othbootargs; " \ 641 "usb start;" \ 642 "ext2load usb 0:4 $loadaddr $bootfile;" \ 643 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 644 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 645 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 646 "debug_halt_off=mw ff7e0e30 0xf0000000;" 647 648 #define CONFIG_NFSBOOTCOMMAND \ 649 "setenv bootargs root=/dev/nfs rw " \ 650 "nfsroot=$serverip:$rootpath " \ 651 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 652 "console=$consoledev,$baudrate $othbootargs;" \ 653 "tftp $loadaddr $bootfile;" \ 654 "tftp $fdtaddr $fdtfile;" \ 655 "bootm $loadaddr - $fdtaddr" 656 657 #define CONFIG_HDBOOT \ 658 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 659 "console=$consoledev,$baudrate $othbootargs;" \ 660 "usb start;" \ 661 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 662 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 663 "bootm $loadaddr - $fdtaddr" 664 665 #define CONFIG_RAMBOOTCOMMAND \ 666 "setenv bootargs root=/dev/ram rw " \ 667 "console=$consoledev,$baudrate $othbootargs; " \ 668 "tftp $ramdiskaddr $ramdiskfile;" \ 669 "tftp $loadaddr $bootfile;" \ 670 "tftp $fdtaddr $fdtfile;" \ 671 "bootm $loadaddr $ramdiskaddr $fdtaddr" 672 673 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 674 675 #include <asm/fsl_secure_boot.h> 676 677 #endif /* __CONFIG_H */ 678