1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9132 QDS board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_BSC9132QDS 15 #define CONFIG_BSC9132 16 #endif 17 18 #define CONFIG_MISC_INIT_R 19 20 #ifdef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_SDCARD 22 #define CONFIG_SYS_RAMBOOT 23 #define CONFIG_SYS_EXTRA_ENV_RELOC 24 #define CONFIG_SYS_TEXT_BASE 0x11000000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 26 #endif 27 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 28 #ifdef CONFIG_SPIFLASH 29 #define CONFIG_RAMBOOT_SPIFLASH 30 #define CONFIG_SYS_RAMBOOT 31 #define CONFIG_SYS_EXTRA_ENV_RELOC 32 #define CONFIG_SYS_TEXT_BASE 0x11000000 33 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 34 #endif 35 #ifdef CONFIG_NAND_SECBOOT 36 #define CONFIG_RAMBOOT_NAND 37 #define CONFIG_SYS_RAMBOOT 38 #define CONFIG_SYS_EXTRA_ENV_RELOC 39 #define CONFIG_SYS_TEXT_BASE 0x11000000 40 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 41 #endif 42 43 #ifdef CONFIG_NAND 44 #define CONFIG_SPL_INIT_MINIMAL 45 #define CONFIG_SPL_SERIAL_SUPPORT 46 #define CONFIG_SPL_NAND_SUPPORT 47 #define CONFIG_SPL_NAND_BOOT 48 #define CONFIG_SPL_FLUSH_IMAGE 49 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 50 51 #define CONFIG_SYS_TEXT_BASE 0x00201000 52 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 53 #define CONFIG_SPL_MAX_SIZE 8192 54 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 55 #define CONFIG_SPL_RELOC_STACK 0x00100000 56 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 57 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 58 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 59 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 60 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 61 #endif 62 63 #ifndef CONFIG_SYS_TEXT_BASE 64 #define CONFIG_SYS_TEXT_BASE 0x8ff40000 65 #endif 66 67 #ifndef CONFIG_RESET_VECTOR_ADDRESS 68 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 69 #endif 70 71 #ifdef CONFIG_SPL_BUILD 72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 73 #else 74 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 75 #endif 76 77 /* High Level Configuration Options */ 78 #define CONFIG_BOOKE /* BOOKE */ 79 #define CONFIG_E500 /* BOOKE e500 family */ 80 #define CONFIG_FSL_IFC /* Enable IFC Support */ 81 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 82 83 #define CONFIG_PCI /* Enable PCI/PCIE */ 84 #if defined(CONFIG_PCI) 85 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 86 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 87 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 88 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 89 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 90 91 #define CONFIG_CMD_NET 92 #define CONFIG_CMD_PCI 93 94 #define CONFIG_E1000 /* E1000 pci Ethernet card*/ 95 96 /* 97 * PCI Windows 98 * Memory space is mapped 1-1, but I/O space must start from 0. 99 */ 100 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 101 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 102 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 103 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 104 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 105 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 106 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 107 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 108 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 109 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 110 111 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 112 113 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 114 #define CONFIG_DOS_PARTITION 115 #endif 116 117 #define CONFIG_FSL_LAW /* Use common FSL init code */ 118 #define CONFIG_ENV_OVERWRITE 119 #define CONFIG_TSEC_ENET /* ethernet */ 120 121 #if defined(CONFIG_SYS_CLK_100_DDR_100) 122 #define CONFIG_SYS_CLK_FREQ 100000000 123 #define CONFIG_DDR_CLK_FREQ 100000000 124 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 125 #define CONFIG_SYS_CLK_FREQ 100000000 126 #define CONFIG_DDR_CLK_FREQ 133000000 127 #endif 128 129 #define CONFIG_MP 130 131 #define CONFIG_HWCONFIG 132 /* 133 * These can be toggled for performance analysis, otherwise use default. 134 */ 135 #define CONFIG_L2_CACHE /* toggle L2 cache */ 136 #define CONFIG_BTB /* enable branch predition */ 137 138 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 139 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 140 141 /* DDR Setup */ 142 #define CONFIG_SYS_FSL_DDR3 143 #define CONFIG_SYS_SPD_BUS_NUM 0 144 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 145 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 146 #define CONFIG_FSL_DDR_INTERACTIVE 147 148 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 149 150 #define CONFIG_SYS_SDRAM_SIZE (1024) 151 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 152 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 153 154 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 155 156 /* DDR3 Controller Settings */ 157 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 158 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 159 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 160 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 161 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 162 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 163 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 164 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 165 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 166 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 167 168 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 169 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 170 #define CONFIG_SYS_DDR_RCW_1 0x00000000 171 #define CONFIG_SYS_DDR_RCW_2 0x00000000 172 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 173 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 174 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 175 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 176 177 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 178 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 179 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 180 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 181 182 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 183 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 184 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 185 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 186 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 187 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 188 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 189 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 190 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 191 192 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 193 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 194 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 195 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 196 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 197 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 198 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 199 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 200 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 201 202 /*FIXME: the following params are constant w.r.t diff freq 203 combinations. this should be removed later 204 */ 205 #if CONFIG_DDR_CLK_FREQ == 100000000 206 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 207 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 208 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 209 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 210 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 211 #elif CONFIG_DDR_CLK_FREQ == 133000000 212 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 213 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 214 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 215 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 216 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 217 #else 218 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 219 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 220 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 221 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 222 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 223 #endif 224 225 226 /* relocated CCSRBAR */ 227 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 228 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 229 230 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 231 232 /* DSP CCSRBAR */ 233 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 234 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 235 236 /* 237 * IFC Definitions 238 */ 239 /* NOR Flash on IFC */ 240 241 #ifdef CONFIG_SPL_BUILD 242 #define CONFIG_SYS_NO_FLASH 243 #endif 244 #define CONFIG_SYS_FLASH_BASE 0x88000000 245 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 246 247 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 248 249 #define CONFIG_SYS_NOR_CSPR 0x88000101 250 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 251 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 252 /* NOR Flash Timing Params */ 253 254 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 255 | FTIM0_NOR_TEADC(0x03) \ 256 | FTIM0_NOR_TAVDS(0x00) \ 257 | FTIM0_NOR_TEAHC(0x0f)) 258 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 259 | FTIM1_NOR_TRAD_NOR(0x09) \ 260 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 261 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 262 | FTIM2_NOR_TCH(0x4) \ 263 | FTIM2_NOR_TWPH(0x7) \ 264 | FTIM2_NOR_TWP(0x1e)) 265 #define CONFIG_SYS_NOR_FTIM3 0x0 266 267 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 268 #define CONFIG_SYS_FLASH_QUIET_TEST 269 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 270 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 271 272 #undef CONFIG_SYS_FLASH_CHECKSUM 273 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 274 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 275 276 /* CFI for NOR Flash */ 277 #define CONFIG_FLASH_CFI_DRIVER 278 #define CONFIG_SYS_FLASH_CFI 279 #define CONFIG_SYS_FLASH_EMPTY_INFO 280 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 281 282 /* NAND Flash on IFC */ 283 #define CONFIG_SYS_NAND_BASE 0xff800000 284 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 285 286 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 287 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 288 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 289 | CSPR_V) 290 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 291 292 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 293 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 294 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 295 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 296 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 297 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 298 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 299 300 /* NAND Flash Timing Params */ 301 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 302 | FTIM0_NAND_TWP(0x05) \ 303 | FTIM0_NAND_TWCHT(0x02) \ 304 | FTIM0_NAND_TWH(0x04)) 305 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 306 | FTIM1_NAND_TWBE(0x1e) \ 307 | FTIM1_NAND_TRR(0x07) \ 308 | FTIM1_NAND_TRP(0x05)) 309 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 310 | FTIM2_NAND_TREH(0x04) \ 311 | FTIM2_NAND_TWHRE(0x11)) 312 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 313 314 #define CONFIG_SYS_NAND_DDR_LAW 11 315 316 /* NAND */ 317 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 318 #define CONFIG_SYS_MAX_NAND_DEVICE 1 319 #define CONFIG_MTD_NAND_VERIFY_WRITE 320 #define CONFIG_CMD_NAND 321 322 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 323 324 #ifndef CONFIG_SPL_BUILD 325 #define CONFIG_FSL_QIXIS 326 #endif 327 #ifdef CONFIG_FSL_QIXIS 328 #define CONFIG_SYS_FPGA_BASE 0xffb00000 329 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 330 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 331 #define QIXIS_LBMAP_SWITCH 9 332 #define QIXIS_LBMAP_MASK 0x07 333 #define QIXIS_LBMAP_SHIFT 0 334 #define QIXIS_LBMAP_DFLTBANK 0x00 335 #define QIXIS_LBMAP_ALTBANK 0x04 336 #define QIXIS_RST_CTL_RESET 0x83 337 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 338 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 339 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 340 341 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 342 343 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 344 | CSPR_PORT_SIZE_8 \ 345 | CSPR_MSEL_GPCM \ 346 | CSPR_V) 347 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 348 #define CONFIG_SYS_CSOR2 0x0 349 /* CPLD Timing parameters for IFC CS3 */ 350 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 351 FTIM0_GPCM_TEADC(0x0e) | \ 352 FTIM0_GPCM_TEAHC(0x0e)) 353 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 354 FTIM1_GPCM_TRAD(0x1f)) 355 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 356 FTIM2_GPCM_TCH(0x8) | \ 357 FTIM2_GPCM_TWP(0x1f)) 358 #define CONFIG_SYS_CS2_FTIM3 0x0 359 #endif 360 361 /* Set up IFC registers for boot location NOR/NAND */ 362 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 363 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 364 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 365 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 366 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 367 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 368 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 369 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 370 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 371 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 372 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 373 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 374 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 375 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 376 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 377 #else 378 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 379 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 380 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 381 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 382 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 383 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 384 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 385 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 386 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 387 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 388 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 389 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 390 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 391 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 392 #endif 393 394 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 395 #define CONFIG_BOARD_EARLY_INIT_R 396 397 #define CONFIG_SYS_INIT_RAM_LOCK 398 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 399 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 400 401 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 402 - GENERATED_GBL_DATA_SIZE) 403 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 404 405 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 406 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 407 408 /* Serial Port */ 409 #define CONFIG_CONS_INDEX 1 410 #undef CONFIG_SERIAL_SOFTWARE_FIFO 411 #define CONFIG_SYS_NS16550 412 #define CONFIG_SYS_NS16550_SERIAL 413 #define CONFIG_SYS_NS16550_REG_SIZE 1 414 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 415 #ifdef CONFIG_SPL_BUILD 416 #define CONFIG_NS16550_MIN_FUNCTIONS 417 #endif 418 419 #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */ 420 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 421 422 #define CONFIG_SYS_BAUDRATE_TABLE \ 423 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 424 425 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 426 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 427 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 428 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 429 430 /* Use the HUSH parser */ 431 #define CONFIG_SYS_HUSH_PARSER /* hush parser */ 432 #ifdef CONFIG_SYS_HUSH_PARSER 433 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 434 #endif 435 436 /* 437 * Pass open firmware flat tree 438 */ 439 #define CONFIG_OF_LIBFDT 440 #define CONFIG_OF_BOARD_SETUP 441 #define CONFIG_OF_STDOUT_VIA_ALIAS 442 443 /* new uImage format support */ 444 #define CONFIG_FIT 445 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 446 447 #define CONFIG_SYS_I2C 448 #define CONFIG_SYS_I2C_FSL 449 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 450 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 451 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 452 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 453 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 454 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 455 456 /* I2C EEPROM */ 457 #define CONFIG_ID_EEPROM 458 #ifdef CONFIG_ID_EEPROM 459 #define CONFIG_SYS_I2C_EEPROM_NXID 460 #endif 461 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 462 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 463 #define CONFIG_SYS_EEPROM_BUS_NUM 0 464 465 /* enable read and write access to EEPROM */ 466 #define CONFIG_CMD_EEPROM 467 #define CONFIG_SYS_I2C_MULTI_EEPROMS 468 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 469 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 470 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 471 472 /* I2C FPGA */ 473 #define CONFIG_I2C_FPGA 474 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 475 476 #define CONFIG_RTC_DS3231 477 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 478 479 /* 480 * SPI interface will not be available in case of NAND boot SPI CS0 will be 481 * used for SLIC 482 */ 483 /* eSPI - Enhanced SPI */ 484 #define CONFIG_FSL_ESPI /* SPI */ 485 #ifdef CONFIG_FSL_ESPI 486 #define CONFIG_SPI_FLASH 487 #define CONFIG_SPI_FLASH_SPANSION 488 #define CONFIG_CMD_SF 489 #define CONFIG_SF_DEFAULT_SPEED 10000000 490 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 491 #endif 492 493 #if defined(CONFIG_TSEC_ENET) 494 495 #define CONFIG_MII /* MII PHY management */ 496 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 497 #define CONFIG_TSEC1 1 498 #define CONFIG_TSEC1_NAME "eTSEC1" 499 #define CONFIG_TSEC2 1 500 #define CONFIG_TSEC2_NAME "eTSEC2" 501 502 #define TSEC1_PHY_ADDR 0 503 #define TSEC2_PHY_ADDR 1 504 505 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 506 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 507 508 #define TSEC1_PHYIDX 0 509 #define TSEC2_PHYIDX 0 510 511 #define CONFIG_ETHPRIME "eTSEC1" 512 513 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 514 515 /* TBI PHY configuration for SGMII mode */ 516 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 517 TBICR_PHY_RESET \ 518 | TBICR_ANEG_ENABLE \ 519 | TBICR_FULL_DUPLEX \ 520 | TBICR_SPEED1_SET \ 521 ) 522 523 #endif /* CONFIG_TSEC_ENET */ 524 525 #define CONFIG_MMC 526 #ifdef CONFIG_MMC 527 #define CONFIG_CMD_MMC 528 #define CONFIG_DOS_PARTITION 529 #define CONFIG_FSL_ESDHC 530 #define CONFIG_GENERIC_MMC 531 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 532 #endif 533 534 #define CONFIG_USB_EHCI /* USB */ 535 #ifdef CONFIG_USB_EHCI 536 #define CONFIG_CMD_USB 537 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 538 #define CONFIG_USB_EHCI_FSL 539 #define CONFIG_USB_STORAGE 540 #define CONFIG_HAS_FSL_DR_USB 541 #endif 542 543 /* 544 * Environment 545 */ 546 #if defined(CONFIG_RAMBOOT_SDCARD) 547 #define CONFIG_ENV_IS_IN_MMC 548 #define CONFIG_FSL_FIXED_MMC_LOCATION 549 #define CONFIG_SYS_MMC_ENV_DEV 0 550 #define CONFIG_ENV_SIZE 0x2000 551 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 552 #define CONFIG_ENV_IS_IN_SPI_FLASH 553 #define CONFIG_ENV_SPI_BUS 0 554 #define CONFIG_ENV_SPI_CS 0 555 #define CONFIG_ENV_SPI_MAX_HZ 10000000 556 #define CONFIG_ENV_SPI_MODE 0 557 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 558 #define CONFIG_ENV_SECT_SIZE 0x10000 559 #define CONFIG_ENV_SIZE 0x2000 560 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 561 #define CONFIG_ENV_IS_IN_NAND 562 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 563 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 564 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 565 #elif defined(CONFIG_SYS_RAMBOOT) 566 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 567 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 568 #define CONFIG_ENV_SIZE 0x2000 569 #else 570 #define CONFIG_ENV_IS_IN_FLASH 571 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 572 #define CONFIG_ENV_SIZE 0x2000 573 #define CONFIG_ENV_SECT_SIZE 0x20000 574 #endif 575 576 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 577 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 578 579 /* 580 * Command line configuration. 581 */ 582 #include <config_cmd_default.h> 583 584 #define CONFIG_CMD_DATE 585 #define CONFIG_CMD_DHCP 586 #define CONFIG_CMD_ELF 587 #define CONFIG_CMD_ERRATA 588 #define CONFIG_CMD_I2C 589 #define CONFIG_CMD_IRQ 590 #define CONFIG_CMD_MII 591 #define CONFIG_CMD_PING 592 #define CONFIG_CMD_SETEXPR 593 #define CONFIG_CMD_REGINFO 594 595 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 596 #define CONFIG_CMD_EXT2 597 #define CONFIG_CMD_FAT 598 #define CONFIG_DOS_PARTITION 599 #endif 600 601 /* 602 * Miscellaneous configurable options 603 */ 604 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 605 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 606 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 607 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 608 609 #if defined(CONFIG_CMD_KGDB) 610 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 611 #else 612 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 613 #endif 614 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 615 /* Print Buffer Size */ 616 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 617 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 618 619 620 /* 621 * For booting Linux, the board info and command line data 622 * have to be in the first 64 MB of memory, since this is 623 * the maximum mapped by the Linux kernel during initialization. 624 */ 625 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 626 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 627 628 #if defined(CONFIG_CMD_KGDB) 629 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 630 #endif 631 632 /* 633 * Environment Configuration 634 */ 635 636 #if defined(CONFIG_TSEC_ENET) 637 #define CONFIG_HAS_ETH0 638 #define CONFIG_HAS_ETH1 639 #endif 640 641 #define CONFIG_HOSTNAME BSC9132qds 642 #define CONFIG_ROOTPATH "/opt/nfsroot" 643 #define CONFIG_BOOTFILE "uImage" 644 #define CONFIG_UBOOTPATH "u-boot.bin" 645 646 #define CONFIG_BAUDRATE 115200 647 648 #ifdef CONFIG_SDCARD 649 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 650 #else 651 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 652 #endif 653 654 #define CONFIG_EXTRA_ENV_SETTINGS \ 655 "netdev=eth0\0" \ 656 "uboot=" CONFIG_UBOOTPATH "\0" \ 657 "loadaddr=1000000\0" \ 658 "bootfile=uImage\0" \ 659 "consoledev=ttyS0\0" \ 660 "ramdiskaddr=2000000\0" \ 661 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 662 "fdtaddr=c00000\0" \ 663 "fdtfile=bsc9132qds.dtb\0" \ 664 "bdev=sda1\0" \ 665 CONFIG_DEF_HWCONFIG\ 666 "othbootargs=mem=880M ramdisk_size=600000 " \ 667 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 668 "isolcpus=0\0" \ 669 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 670 "console=$consoledev,$baudrate $othbootargs; " \ 671 "usb start;" \ 672 "ext2load usb 0:4 $loadaddr $bootfile;" \ 673 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 674 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 675 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 676 "debug_halt_off=mw ff7e0e30 0xf0000000;" 677 678 #define CONFIG_NFSBOOTCOMMAND \ 679 "setenv bootargs root=/dev/nfs rw " \ 680 "nfsroot=$serverip:$rootpath " \ 681 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 682 "console=$consoledev,$baudrate $othbootargs;" \ 683 "tftp $loadaddr $bootfile;" \ 684 "tftp $fdtaddr $fdtfile;" \ 685 "bootm $loadaddr - $fdtaddr" 686 687 #define CONFIG_HDBOOT \ 688 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 689 "console=$consoledev,$baudrate $othbootargs;" \ 690 "usb start;" \ 691 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 692 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 693 "bootm $loadaddr - $fdtaddr" 694 695 #define CONFIG_RAMBOOTCOMMAND \ 696 "setenv bootargs root=/dev/ram rw " \ 697 "console=$consoledev,$baudrate $othbootargs; " \ 698 "tftp $ramdiskaddr $ramdiskfile;" \ 699 "tftp $loadaddr $bootfile;" \ 700 "tftp $fdtaddr $fdtfile;" \ 701 "bootm $loadaddr $ramdiskaddr $fdtaddr" 702 703 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 704 705 #include <asm/fsl_secure_boot.h> 706 707 #endif /* __CONFIG_H */ 708