1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9132 QDS board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_MISC_INIT_R 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 18 #define CONFIG_SYS_RAMBOOT 19 #define CONFIG_SYS_EXTRA_ENV_RELOC 20 #define CONFIG_SYS_TEXT_BASE 0x11000000 21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 22 #endif 23 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 24 #ifdef CONFIG_SPIFLASH 25 #define CONFIG_RAMBOOT_SPIFLASH 26 #define CONFIG_SYS_RAMBOOT 27 #define CONFIG_SYS_EXTRA_ENV_RELOC 28 #define CONFIG_SYS_TEXT_BASE 0x11000000 29 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 30 #endif 31 #ifdef CONFIG_NAND_SECBOOT 32 #define CONFIG_RAMBOOT_NAND 33 #define CONFIG_SYS_RAMBOOT 34 #define CONFIG_SYS_EXTRA_ENV_RELOC 35 #define CONFIG_SYS_TEXT_BASE 0x11000000 36 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 37 #endif 38 39 #ifdef CONFIG_NAND 40 #define CONFIG_SPL_INIT_MINIMAL 41 #define CONFIG_SPL_NAND_BOOT 42 #define CONFIG_SPL_FLUSH_IMAGE 43 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 44 45 #define CONFIG_SYS_TEXT_BASE 0x00201000 46 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 47 #define CONFIG_SPL_MAX_SIZE 8192 48 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 49 #define CONFIG_SPL_RELOC_STACK 0x00100000 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 51 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 55 #endif 56 57 #ifndef CONFIG_SYS_TEXT_BASE 58 #define CONFIG_SYS_TEXT_BASE 0x8ff40000 59 #endif 60 61 #ifndef CONFIG_RESET_VECTOR_ADDRESS 62 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 63 #endif 64 65 #ifdef CONFIG_SPL_BUILD 66 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 67 #else 68 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 69 #endif 70 71 /* High Level Configuration Options */ 72 #define CONFIG_BOOKE /* BOOKE */ 73 #define CONFIG_E500 /* BOOKE e500 family */ 74 #define CONFIG_FSL_IFC /* Enable IFC Support */ 75 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 76 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 77 78 #if defined(CONFIG_PCI) 79 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 80 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 81 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 82 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 83 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 84 85 #define CONFIG_CMD_PCI 86 87 /* 88 * PCI Windows 89 * Memory space is mapped 1-1, but I/O space must start from 0. 90 */ 91 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 92 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 93 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 94 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 95 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 96 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 97 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 98 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 99 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 100 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 101 102 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 103 #define CONFIG_DOS_PARTITION 104 #endif 105 106 #define CONFIG_ENV_OVERWRITE 107 #define CONFIG_TSEC_ENET /* ethernet */ 108 109 #if defined(CONFIG_SYS_CLK_100_DDR_100) 110 #define CONFIG_SYS_CLK_FREQ 100000000 111 #define CONFIG_DDR_CLK_FREQ 100000000 112 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 113 #define CONFIG_SYS_CLK_FREQ 100000000 114 #define CONFIG_DDR_CLK_FREQ 133000000 115 #endif 116 117 #define CONFIG_MP 118 119 #define CONFIG_HWCONFIG 120 /* 121 * These can be toggled for performance analysis, otherwise use default. 122 */ 123 #define CONFIG_L2_CACHE /* toggle L2 cache */ 124 #define CONFIG_BTB /* enable branch predition */ 125 126 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 127 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 128 129 /* DDR Setup */ 130 #define CONFIG_SYS_FSL_DDR3 131 #define CONFIG_SYS_SPD_BUS_NUM 0 132 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 133 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 134 #define CONFIG_FSL_DDR_INTERACTIVE 135 136 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 137 138 #define CONFIG_SYS_SDRAM_SIZE (1024) 139 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 140 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 141 142 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 143 144 /* DDR3 Controller Settings */ 145 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 146 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 147 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 148 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 149 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 150 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 151 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 152 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 153 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 154 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 155 156 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 157 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 158 #define CONFIG_SYS_DDR_RCW_1 0x00000000 159 #define CONFIG_SYS_DDR_RCW_2 0x00000000 160 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 161 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 162 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 163 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 164 165 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 166 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 167 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 168 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 169 170 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 171 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 172 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 173 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 174 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 175 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 176 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 177 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 178 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 179 180 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 181 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 182 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 183 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 184 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 185 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 186 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 187 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 188 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 189 190 /*FIXME: the following params are constant w.r.t diff freq 191 combinations. this should be removed later 192 */ 193 #if CONFIG_DDR_CLK_FREQ == 100000000 194 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 195 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 196 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 197 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 198 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 199 #elif CONFIG_DDR_CLK_FREQ == 133000000 200 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 201 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 202 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 203 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 204 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 205 #else 206 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 207 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 208 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 209 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 210 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 211 #endif 212 213 /* relocated CCSRBAR */ 214 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 215 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 216 217 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 218 219 /* DSP CCSRBAR */ 220 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 221 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 222 223 /* 224 * IFC Definitions 225 */ 226 /* NOR Flash on IFC */ 227 228 #ifdef CONFIG_SPL_BUILD 229 #define CONFIG_SYS_NO_FLASH 230 #endif 231 #define CONFIG_SYS_FLASH_BASE 0x88000000 232 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 233 234 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 235 236 #define CONFIG_SYS_NOR_CSPR 0x88000101 237 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 238 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 239 /* NOR Flash Timing Params */ 240 241 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 242 | FTIM0_NOR_TEADC(0x03) \ 243 | FTIM0_NOR_TAVDS(0x00) \ 244 | FTIM0_NOR_TEAHC(0x0f)) 245 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 246 | FTIM1_NOR_TRAD_NOR(0x09) \ 247 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 248 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 249 | FTIM2_NOR_TCH(0x4) \ 250 | FTIM2_NOR_TWPH(0x7) \ 251 | FTIM2_NOR_TWP(0x1e)) 252 #define CONFIG_SYS_NOR_FTIM3 0x0 253 254 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 255 #define CONFIG_SYS_FLASH_QUIET_TEST 256 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 257 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 258 259 #undef CONFIG_SYS_FLASH_CHECKSUM 260 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 261 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 262 263 /* CFI for NOR Flash */ 264 #define CONFIG_FLASH_CFI_DRIVER 265 #define CONFIG_SYS_FLASH_CFI 266 #define CONFIG_SYS_FLASH_EMPTY_INFO 267 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 268 269 /* NAND Flash on IFC */ 270 #define CONFIG_SYS_NAND_BASE 0xff800000 271 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 272 273 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 274 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 275 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 276 | CSPR_V) 277 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 278 279 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 280 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 281 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 282 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 283 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 284 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 285 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 286 287 /* NAND Flash Timing Params */ 288 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 289 | FTIM0_NAND_TWP(0x05) \ 290 | FTIM0_NAND_TWCHT(0x02) \ 291 | FTIM0_NAND_TWH(0x04)) 292 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 293 | FTIM1_NAND_TWBE(0x1e) \ 294 | FTIM1_NAND_TRR(0x07) \ 295 | FTIM1_NAND_TRP(0x05)) 296 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 297 | FTIM2_NAND_TREH(0x04) \ 298 | FTIM2_NAND_TWHRE(0x11)) 299 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 300 301 #define CONFIG_SYS_NAND_DDR_LAW 11 302 303 /* NAND */ 304 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 305 #define CONFIG_SYS_MAX_NAND_DEVICE 1 306 #define CONFIG_CMD_NAND 307 308 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 309 310 #ifndef CONFIG_SPL_BUILD 311 #define CONFIG_FSL_QIXIS 312 #endif 313 #ifdef CONFIG_FSL_QIXIS 314 #define CONFIG_SYS_FPGA_BASE 0xffb00000 315 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 316 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 317 #define QIXIS_LBMAP_SWITCH 9 318 #define QIXIS_LBMAP_MASK 0x07 319 #define QIXIS_LBMAP_SHIFT 0 320 #define QIXIS_LBMAP_DFLTBANK 0x00 321 #define QIXIS_LBMAP_ALTBANK 0x04 322 #define QIXIS_RST_CTL_RESET 0x83 323 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 324 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 325 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 326 327 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 328 329 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 330 | CSPR_PORT_SIZE_8 \ 331 | CSPR_MSEL_GPCM \ 332 | CSPR_V) 333 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 334 #define CONFIG_SYS_CSOR2 0x0 335 /* CPLD Timing parameters for IFC CS3 */ 336 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 337 FTIM0_GPCM_TEADC(0x0e) | \ 338 FTIM0_GPCM_TEAHC(0x0e)) 339 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 340 FTIM1_GPCM_TRAD(0x1f)) 341 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 342 FTIM2_GPCM_TCH(0x8) | \ 343 FTIM2_GPCM_TWP(0x1f)) 344 #define CONFIG_SYS_CS2_FTIM3 0x0 345 #endif 346 347 /* Set up IFC registers for boot location NOR/NAND */ 348 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 349 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 350 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 351 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 352 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 353 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 354 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 355 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 356 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 357 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 358 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 359 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 360 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 361 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 362 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 363 #else 364 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 365 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 366 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 367 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 368 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 369 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 370 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 371 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 372 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 373 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 374 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 375 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 376 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 377 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 378 #endif 379 380 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 381 #define CONFIG_BOARD_EARLY_INIT_R 382 383 #define CONFIG_SYS_INIT_RAM_LOCK 384 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 385 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 386 387 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 388 - GENERATED_GBL_DATA_SIZE) 389 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 390 391 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 392 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 393 394 /* Serial Port */ 395 #define CONFIG_CONS_INDEX 1 396 #undef CONFIG_SERIAL_SOFTWARE_FIFO 397 #define CONFIG_SYS_NS16550_SERIAL 398 #define CONFIG_SYS_NS16550_REG_SIZE 1 399 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 400 #ifdef CONFIG_SPL_BUILD 401 #define CONFIG_NS16550_MIN_FUNCTIONS 402 #endif 403 404 #define CONFIG_SYS_BAUDRATE_TABLE \ 405 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 406 407 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 408 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 409 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 410 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 411 412 #define CONFIG_SYS_I2C 413 #define CONFIG_SYS_I2C_FSL 414 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 415 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 416 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 417 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 418 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 419 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 420 421 /* I2C EEPROM */ 422 #define CONFIG_ID_EEPROM 423 #ifdef CONFIG_ID_EEPROM 424 #define CONFIG_SYS_I2C_EEPROM_NXID 425 #endif 426 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 427 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 428 #define CONFIG_SYS_EEPROM_BUS_NUM 0 429 430 /* enable read and write access to EEPROM */ 431 #define CONFIG_CMD_EEPROM 432 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 433 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 434 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 435 436 /* I2C FPGA */ 437 #define CONFIG_I2C_FPGA 438 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 439 440 #define CONFIG_RTC_DS3231 441 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 442 443 /* 444 * SPI interface will not be available in case of NAND boot SPI CS0 will be 445 * used for SLIC 446 */ 447 /* eSPI - Enhanced SPI */ 448 #ifdef CONFIG_FSL_ESPI 449 #define CONFIG_SF_DEFAULT_SPEED 10000000 450 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 451 #endif 452 453 #if defined(CONFIG_TSEC_ENET) 454 455 #define CONFIG_MII /* MII PHY management */ 456 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 457 #define CONFIG_TSEC1 1 458 #define CONFIG_TSEC1_NAME "eTSEC1" 459 #define CONFIG_TSEC2 1 460 #define CONFIG_TSEC2_NAME "eTSEC2" 461 462 #define TSEC1_PHY_ADDR 0 463 #define TSEC2_PHY_ADDR 1 464 465 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 466 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 467 468 #define TSEC1_PHYIDX 0 469 #define TSEC2_PHYIDX 0 470 471 #define CONFIG_ETHPRIME "eTSEC1" 472 473 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 474 475 /* TBI PHY configuration for SGMII mode */ 476 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 477 TBICR_PHY_RESET \ 478 | TBICR_ANEG_ENABLE \ 479 | TBICR_FULL_DUPLEX \ 480 | TBICR_SPEED1_SET \ 481 ) 482 483 #endif /* CONFIG_TSEC_ENET */ 484 485 #define CONFIG_MMC 486 #ifdef CONFIG_MMC 487 #define CONFIG_DOS_PARTITION 488 #define CONFIG_FSL_ESDHC 489 #define CONFIG_GENERIC_MMC 490 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 491 #endif 492 493 #define CONFIG_USB_EHCI /* USB */ 494 #ifdef CONFIG_USB_EHCI 495 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 496 #define CONFIG_USB_EHCI_FSL 497 #define CONFIG_HAS_FSL_DR_USB 498 #endif 499 500 /* 501 * Environment 502 */ 503 #if defined(CONFIG_RAMBOOT_SDCARD) 504 #define CONFIG_ENV_IS_IN_MMC 505 #define CONFIG_FSL_FIXED_MMC_LOCATION 506 #define CONFIG_SYS_MMC_ENV_DEV 0 507 #define CONFIG_ENV_SIZE 0x2000 508 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 509 #define CONFIG_ENV_IS_IN_SPI_FLASH 510 #define CONFIG_ENV_SPI_BUS 0 511 #define CONFIG_ENV_SPI_CS 0 512 #define CONFIG_ENV_SPI_MAX_HZ 10000000 513 #define CONFIG_ENV_SPI_MODE 0 514 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 515 #define CONFIG_ENV_SECT_SIZE 0x10000 516 #define CONFIG_ENV_SIZE 0x2000 517 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 518 #define CONFIG_ENV_IS_IN_NAND 519 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 520 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 521 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 522 #elif defined(CONFIG_SYS_RAMBOOT) 523 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 524 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 525 #define CONFIG_ENV_SIZE 0x2000 526 #else 527 #define CONFIG_ENV_IS_IN_FLASH 528 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 529 #define CONFIG_ENV_SIZE 0x2000 530 #define CONFIG_ENV_SECT_SIZE 0x20000 531 #endif 532 533 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 534 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 535 536 /* 537 * Command line configuration. 538 */ 539 #define CONFIG_CMD_DATE 540 #define CONFIG_CMD_ERRATA 541 #define CONFIG_CMD_IRQ 542 #define CONFIG_CMD_REGINFO 543 544 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 545 #define CONFIG_DOS_PARTITION 546 #endif 547 548 /* Hash command with SHA acceleration supported in hardware */ 549 #ifdef CONFIG_FSL_CAAM 550 #define CONFIG_CMD_HASH 551 #define CONFIG_SHA_HW_ACCEL 552 #endif 553 554 /* 555 * Miscellaneous configurable options 556 */ 557 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 558 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 559 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 560 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 561 562 #if defined(CONFIG_CMD_KGDB) 563 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 564 #else 565 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 566 #endif 567 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 568 /* Print Buffer Size */ 569 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 570 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 571 572 /* 573 * For booting Linux, the board info and command line data 574 * have to be in the first 64 MB of memory, since this is 575 * the maximum mapped by the Linux kernel during initialization. 576 */ 577 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 578 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 579 580 #if defined(CONFIG_CMD_KGDB) 581 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 582 #endif 583 584 /* 585 * Dynamic MTD Partition support with mtdparts 586 */ 587 #ifndef CONFIG_SYS_NO_FLASH 588 #define CONFIG_MTD_DEVICE 589 #define CONFIG_MTD_PARTITIONS 590 #define CONFIG_CMD_MTDPARTS 591 #define CONFIG_FLASH_CFI_MTD 592 #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," 593 #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ 594 "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ 595 "8m(kernel),512k(dtb),-(fs)" 596 #endif 597 /* 598 * Environment Configuration 599 */ 600 601 #if defined(CONFIG_TSEC_ENET) 602 #define CONFIG_HAS_ETH0 603 #define CONFIG_HAS_ETH1 604 #endif 605 606 #define CONFIG_HOSTNAME BSC9132qds 607 #define CONFIG_ROOTPATH "/opt/nfsroot" 608 #define CONFIG_BOOTFILE "uImage" 609 #define CONFIG_UBOOTPATH "u-boot.bin" 610 611 #define CONFIG_BAUDRATE 115200 612 613 #ifdef CONFIG_SDCARD 614 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 615 #else 616 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 617 #endif 618 619 #define CONFIG_EXTRA_ENV_SETTINGS \ 620 "netdev=eth0\0" \ 621 "uboot=" CONFIG_UBOOTPATH "\0" \ 622 "loadaddr=1000000\0" \ 623 "bootfile=uImage\0" \ 624 "consoledev=ttyS0\0" \ 625 "ramdiskaddr=2000000\0" \ 626 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 627 "fdtaddr=1e00000\0" \ 628 "fdtfile=bsc9132qds.dtb\0" \ 629 "bdev=sda1\0" \ 630 CONFIG_DEF_HWCONFIG\ 631 "othbootargs=mem=880M ramdisk_size=600000 " \ 632 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 633 "isolcpus=0\0" \ 634 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 635 "console=$consoledev,$baudrate $othbootargs; " \ 636 "usb start;" \ 637 "ext2load usb 0:4 $loadaddr $bootfile;" \ 638 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 639 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 640 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 641 "debug_halt_off=mw ff7e0e30 0xf0000000;" 642 643 #define CONFIG_NFSBOOTCOMMAND \ 644 "setenv bootargs root=/dev/nfs rw " \ 645 "nfsroot=$serverip:$rootpath " \ 646 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 647 "console=$consoledev,$baudrate $othbootargs;" \ 648 "tftp $loadaddr $bootfile;" \ 649 "tftp $fdtaddr $fdtfile;" \ 650 "bootm $loadaddr - $fdtaddr" 651 652 #define CONFIG_HDBOOT \ 653 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 654 "console=$consoledev,$baudrate $othbootargs;" \ 655 "usb start;" \ 656 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 657 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 658 "bootm $loadaddr - $fdtaddr" 659 660 #define CONFIG_RAMBOOTCOMMAND \ 661 "setenv bootargs root=/dev/ram rw " \ 662 "console=$consoledev,$baudrate $othbootargs; " \ 663 "tftp $ramdiskaddr $ramdiskfile;" \ 664 "tftp $loadaddr $bootfile;" \ 665 "tftp $fdtaddr $fdtfile;" \ 666 "bootm $loadaddr $ramdiskaddr $fdtaddr" 667 668 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 669 670 #include <asm/fsl_secure_boot.h> 671 672 #endif /* __CONFIG_H */ 673