1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9132 QDS board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_MISC_INIT_R 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 18 #define CONFIG_SYS_RAMBOOT 19 #define CONFIG_SYS_EXTRA_ENV_RELOC 20 #define CONFIG_SYS_TEXT_BASE 0x11000000 21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 22 #endif 23 #ifdef CONFIG_SPIFLASH 24 #define CONFIG_RAMBOOT_SPIFLASH 25 #define CONFIG_SYS_RAMBOOT 26 #define CONFIG_SYS_EXTRA_ENV_RELOC 27 #define CONFIG_SYS_TEXT_BASE 0x11000000 28 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 29 #endif 30 #ifdef CONFIG_NAND_SECBOOT 31 #define CONFIG_RAMBOOT_NAND 32 #define CONFIG_SYS_RAMBOOT 33 #define CONFIG_SYS_EXTRA_ENV_RELOC 34 #define CONFIG_SYS_TEXT_BASE 0x11000000 35 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 36 #endif 37 38 #ifdef CONFIG_NAND 39 #define CONFIG_SPL_INIT_MINIMAL 40 #define CONFIG_SPL_NAND_BOOT 41 #define CONFIG_SPL_FLUSH_IMAGE 42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 43 44 #define CONFIG_SYS_TEXT_BASE 0x00201000 45 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 46 #define CONFIG_SPL_MAX_SIZE 8192 47 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 48 #define CONFIG_SPL_RELOC_STACK 0x00100000 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 50 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 51 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 52 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #endif 55 56 #ifndef CONFIG_SYS_TEXT_BASE 57 #define CONFIG_SYS_TEXT_BASE 0x8ff40000 58 #endif 59 60 #ifndef CONFIG_RESET_VECTOR_ADDRESS 61 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 62 #endif 63 64 #ifdef CONFIG_SPL_BUILD 65 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 66 #else 67 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 68 #endif 69 70 /* High Level Configuration Options */ 71 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 72 73 #if defined(CONFIG_PCI) 74 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 75 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 76 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 77 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 78 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 79 80 #define CONFIG_CMD_PCI 81 82 /* 83 * PCI Windows 84 * Memory space is mapped 1-1, but I/O space must start from 0. 85 */ 86 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 87 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 88 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 89 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 90 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 91 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 92 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 93 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 94 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 95 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 96 97 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 98 #endif 99 100 #define CONFIG_ENV_OVERWRITE 101 #define CONFIG_TSEC_ENET /* ethernet */ 102 103 #if defined(CONFIG_SYS_CLK_100_DDR_100) 104 #define CONFIG_SYS_CLK_FREQ 100000000 105 #define CONFIG_DDR_CLK_FREQ 100000000 106 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 107 #define CONFIG_SYS_CLK_FREQ 100000000 108 #define CONFIG_DDR_CLK_FREQ 133000000 109 #endif 110 111 #define CONFIG_MP 112 113 #define CONFIG_HWCONFIG 114 /* 115 * These can be toggled for performance analysis, otherwise use default. 116 */ 117 #define CONFIG_L2_CACHE /* toggle L2 cache */ 118 #define CONFIG_BTB /* enable branch predition */ 119 120 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 121 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 122 123 /* DDR Setup */ 124 #define CONFIG_SYS_SPD_BUS_NUM 0 125 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 126 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 127 #define CONFIG_FSL_DDR_INTERACTIVE 128 129 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 130 131 #define CONFIG_SYS_SDRAM_SIZE (1024) 132 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 133 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 134 135 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 136 137 /* DDR3 Controller Settings */ 138 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 139 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 140 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 141 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 142 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 143 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 144 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 145 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 146 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 147 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 148 149 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 150 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 151 #define CONFIG_SYS_DDR_RCW_1 0x00000000 152 #define CONFIG_SYS_DDR_RCW_2 0x00000000 153 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 154 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 155 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 156 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 157 158 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 159 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 160 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 161 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 162 163 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 164 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 165 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 166 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 167 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 168 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 169 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 170 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 171 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 172 173 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 174 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 175 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 176 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 177 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 178 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 179 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 180 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 181 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 182 183 /*FIXME: the following params are constant w.r.t diff freq 184 combinations. this should be removed later 185 */ 186 #if CONFIG_DDR_CLK_FREQ == 100000000 187 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 188 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 189 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 190 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 191 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 192 #elif CONFIG_DDR_CLK_FREQ == 133000000 193 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 194 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 195 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 196 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 197 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 198 #else 199 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 200 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 201 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 202 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 203 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 204 #endif 205 206 /* relocated CCSRBAR */ 207 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 208 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 209 210 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 211 212 /* DSP CCSRBAR */ 213 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 214 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 215 216 /* 217 * IFC Definitions 218 */ 219 /* NOR Flash on IFC */ 220 221 #define CONFIG_SYS_FLASH_BASE 0x88000000 222 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 223 224 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 225 226 #define CONFIG_SYS_NOR_CSPR 0x88000101 227 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 228 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 229 /* NOR Flash Timing Params */ 230 231 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 232 | FTIM0_NOR_TEADC(0x03) \ 233 | FTIM0_NOR_TAVDS(0x00) \ 234 | FTIM0_NOR_TEAHC(0x0f)) 235 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 236 | FTIM1_NOR_TRAD_NOR(0x09) \ 237 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 238 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 239 | FTIM2_NOR_TCH(0x4) \ 240 | FTIM2_NOR_TWPH(0x7) \ 241 | FTIM2_NOR_TWP(0x1e)) 242 #define CONFIG_SYS_NOR_FTIM3 0x0 243 244 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 245 #define CONFIG_SYS_FLASH_QUIET_TEST 246 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 247 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 248 249 #undef CONFIG_SYS_FLASH_CHECKSUM 250 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 251 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 252 253 /* CFI for NOR Flash */ 254 #define CONFIG_FLASH_CFI_DRIVER 255 #define CONFIG_SYS_FLASH_CFI 256 #define CONFIG_SYS_FLASH_EMPTY_INFO 257 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 258 259 /* NAND Flash on IFC */ 260 #define CONFIG_SYS_NAND_BASE 0xff800000 261 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 262 263 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 264 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 265 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 266 | CSPR_V) 267 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 268 269 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 270 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 271 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 272 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 273 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 274 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 275 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 276 277 /* NAND Flash Timing Params */ 278 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 279 | FTIM0_NAND_TWP(0x05) \ 280 | FTIM0_NAND_TWCHT(0x02) \ 281 | FTIM0_NAND_TWH(0x04)) 282 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 283 | FTIM1_NAND_TWBE(0x1e) \ 284 | FTIM1_NAND_TRR(0x07) \ 285 | FTIM1_NAND_TRP(0x05)) 286 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 287 | FTIM2_NAND_TREH(0x04) \ 288 | FTIM2_NAND_TWHRE(0x11)) 289 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 290 291 #define CONFIG_SYS_NAND_DDR_LAW 11 292 293 /* NAND */ 294 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 295 #define CONFIG_SYS_MAX_NAND_DEVICE 1 296 #define CONFIG_CMD_NAND 297 298 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 299 300 #ifndef CONFIG_SPL_BUILD 301 #define CONFIG_FSL_QIXIS 302 #endif 303 #ifdef CONFIG_FSL_QIXIS 304 #define CONFIG_SYS_FPGA_BASE 0xffb00000 305 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 306 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 307 #define QIXIS_LBMAP_SWITCH 9 308 #define QIXIS_LBMAP_MASK 0x07 309 #define QIXIS_LBMAP_SHIFT 0 310 #define QIXIS_LBMAP_DFLTBANK 0x00 311 #define QIXIS_LBMAP_ALTBANK 0x04 312 #define QIXIS_RST_CTL_RESET 0x83 313 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 314 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 315 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 316 317 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 318 319 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 320 | CSPR_PORT_SIZE_8 \ 321 | CSPR_MSEL_GPCM \ 322 | CSPR_V) 323 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 324 #define CONFIG_SYS_CSOR2 0x0 325 /* CPLD Timing parameters for IFC CS3 */ 326 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 327 FTIM0_GPCM_TEADC(0x0e) | \ 328 FTIM0_GPCM_TEAHC(0x0e)) 329 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 330 FTIM1_GPCM_TRAD(0x1f)) 331 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 332 FTIM2_GPCM_TCH(0x8) | \ 333 FTIM2_GPCM_TWP(0x1f)) 334 #define CONFIG_SYS_CS2_FTIM3 0x0 335 #endif 336 337 /* Set up IFC registers for boot location NOR/NAND */ 338 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 339 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 340 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 341 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 342 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 343 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 344 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 345 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 346 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 347 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 348 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 349 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 350 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 351 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 352 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 353 #else 354 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 355 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 356 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 357 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 358 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 359 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 360 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 361 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 362 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 363 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 364 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 365 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 366 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 367 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 368 #endif 369 370 #define CONFIG_BOARD_EARLY_INIT_R 371 372 #define CONFIG_SYS_INIT_RAM_LOCK 373 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 374 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 375 376 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 377 - GENERATED_GBL_DATA_SIZE) 378 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 379 380 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 381 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 382 383 /* Serial Port */ 384 #define CONFIG_CONS_INDEX 1 385 #undef CONFIG_SERIAL_SOFTWARE_FIFO 386 #define CONFIG_SYS_NS16550_SERIAL 387 #define CONFIG_SYS_NS16550_REG_SIZE 1 388 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 389 #ifdef CONFIG_SPL_BUILD 390 #define CONFIG_NS16550_MIN_FUNCTIONS 391 #endif 392 393 #define CONFIG_SYS_BAUDRATE_TABLE \ 394 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 395 396 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 397 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 398 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 399 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 400 401 #define CONFIG_SYS_I2C 402 #define CONFIG_SYS_I2C_FSL 403 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 404 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 405 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 406 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 407 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 408 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 409 410 /* I2C EEPROM */ 411 #define CONFIG_ID_EEPROM 412 #ifdef CONFIG_ID_EEPROM 413 #define CONFIG_SYS_I2C_EEPROM_NXID 414 #endif 415 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 416 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 417 #define CONFIG_SYS_EEPROM_BUS_NUM 0 418 419 /* enable read and write access to EEPROM */ 420 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 421 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 422 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 423 424 /* I2C FPGA */ 425 #define CONFIG_I2C_FPGA 426 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 427 428 #define CONFIG_RTC_DS3231 429 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 430 431 /* 432 * SPI interface will not be available in case of NAND boot SPI CS0 will be 433 * used for SLIC 434 */ 435 /* eSPI - Enhanced SPI */ 436 #ifdef CONFIG_FSL_ESPI 437 #define CONFIG_SF_DEFAULT_SPEED 10000000 438 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 439 #endif 440 441 #if defined(CONFIG_TSEC_ENET) 442 443 #define CONFIG_MII /* MII PHY management */ 444 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 445 #define CONFIG_TSEC1 1 446 #define CONFIG_TSEC1_NAME "eTSEC1" 447 #define CONFIG_TSEC2 1 448 #define CONFIG_TSEC2_NAME "eTSEC2" 449 450 #define TSEC1_PHY_ADDR 0 451 #define TSEC2_PHY_ADDR 1 452 453 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 454 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 455 456 #define TSEC1_PHYIDX 0 457 #define TSEC2_PHYIDX 0 458 459 #define CONFIG_ETHPRIME "eTSEC1" 460 461 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 462 463 /* TBI PHY configuration for SGMII mode */ 464 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 465 TBICR_PHY_RESET \ 466 | TBICR_ANEG_ENABLE \ 467 | TBICR_FULL_DUPLEX \ 468 | TBICR_SPEED1_SET \ 469 ) 470 471 #endif /* CONFIG_TSEC_ENET */ 472 473 #ifdef CONFIG_MMC 474 #define CONFIG_FSL_ESDHC 475 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 476 #endif 477 478 #ifdef CONFIG_USB_EHCI_HCD 479 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 480 #define CONFIG_USB_EHCI_FSL 481 #define CONFIG_HAS_FSL_DR_USB 482 #endif 483 484 /* 485 * Environment 486 */ 487 #if defined(CONFIG_RAMBOOT_SDCARD) 488 #define CONFIG_ENV_IS_IN_MMC 489 #define CONFIG_FSL_FIXED_MMC_LOCATION 490 #define CONFIG_SYS_MMC_ENV_DEV 0 491 #define CONFIG_ENV_SIZE 0x2000 492 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 493 #define CONFIG_ENV_IS_IN_SPI_FLASH 494 #define CONFIG_ENV_SPI_BUS 0 495 #define CONFIG_ENV_SPI_CS 0 496 #define CONFIG_ENV_SPI_MAX_HZ 10000000 497 #define CONFIG_ENV_SPI_MODE 0 498 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 499 #define CONFIG_ENV_SECT_SIZE 0x10000 500 #define CONFIG_ENV_SIZE 0x2000 501 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 502 #define CONFIG_ENV_IS_IN_NAND 503 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 504 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 505 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 506 #elif defined(CONFIG_SYS_RAMBOOT) 507 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 508 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 509 #define CONFIG_ENV_SIZE 0x2000 510 #else 511 #define CONFIG_ENV_IS_IN_FLASH 512 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 513 #define CONFIG_ENV_SIZE 0x2000 514 #define CONFIG_ENV_SECT_SIZE 0x20000 515 #endif 516 517 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 518 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 519 520 /* 521 * Command line configuration. 522 */ 523 #define CONFIG_CMD_REGINFO 524 525 /* 526 * Miscellaneous configurable options 527 */ 528 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 529 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 530 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 531 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 532 533 #if defined(CONFIG_CMD_KGDB) 534 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 535 #else 536 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 537 #endif 538 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 539 /* Print Buffer Size */ 540 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 541 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 542 543 /* 544 * For booting Linux, the board info and command line data 545 * have to be in the first 64 MB of memory, since this is 546 * the maximum mapped by the Linux kernel during initialization. 547 */ 548 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 549 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 550 551 #if defined(CONFIG_CMD_KGDB) 552 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 553 #endif 554 555 /* 556 * Dynamic MTD Partition support with mtdparts 557 */ 558 #ifdef CONFIG_MTD_NOR_FLASH 559 #define CONFIG_MTD_DEVICE 560 #define CONFIG_MTD_PARTITIONS 561 #define CONFIG_CMD_MTDPARTS 562 #define CONFIG_FLASH_CFI_MTD 563 #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," 564 #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ 565 "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ 566 "8m(kernel),512k(dtb),-(fs)" 567 #endif 568 /* 569 * Environment Configuration 570 */ 571 572 #if defined(CONFIG_TSEC_ENET) 573 #define CONFIG_HAS_ETH0 574 #define CONFIG_HAS_ETH1 575 #endif 576 577 #define CONFIG_HOSTNAME BSC9132qds 578 #define CONFIG_ROOTPATH "/opt/nfsroot" 579 #define CONFIG_BOOTFILE "uImage" 580 #define CONFIG_UBOOTPATH "u-boot.bin" 581 582 #ifdef CONFIG_SDCARD 583 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 584 #else 585 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 586 #endif 587 588 #define CONFIG_EXTRA_ENV_SETTINGS \ 589 "netdev=eth0\0" \ 590 "uboot=" CONFIG_UBOOTPATH "\0" \ 591 "loadaddr=1000000\0" \ 592 "bootfile=uImage\0" \ 593 "consoledev=ttyS0\0" \ 594 "ramdiskaddr=2000000\0" \ 595 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 596 "fdtaddr=1e00000\0" \ 597 "fdtfile=bsc9132qds.dtb\0" \ 598 "bdev=sda1\0" \ 599 CONFIG_DEF_HWCONFIG\ 600 "othbootargs=mem=880M ramdisk_size=600000 " \ 601 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 602 "isolcpus=0\0" \ 603 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 604 "console=$consoledev,$baudrate $othbootargs; " \ 605 "usb start;" \ 606 "ext2load usb 0:4 $loadaddr $bootfile;" \ 607 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 608 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 609 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 610 "debug_halt_off=mw ff7e0e30 0xf0000000;" 611 612 #define CONFIG_NFSBOOTCOMMAND \ 613 "setenv bootargs root=/dev/nfs rw " \ 614 "nfsroot=$serverip:$rootpath " \ 615 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 616 "console=$consoledev,$baudrate $othbootargs;" \ 617 "tftp $loadaddr $bootfile;" \ 618 "tftp $fdtaddr $fdtfile;" \ 619 "bootm $loadaddr - $fdtaddr" 620 621 #define CONFIG_HDBOOT \ 622 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 623 "console=$consoledev,$baudrate $othbootargs;" \ 624 "usb start;" \ 625 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 626 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 627 "bootm $loadaddr - $fdtaddr" 628 629 #define CONFIG_RAMBOOTCOMMAND \ 630 "setenv bootargs root=/dev/ram rw " \ 631 "console=$consoledev,$baudrate $othbootargs; " \ 632 "tftp $ramdiskaddr $ramdiskfile;" \ 633 "tftp $loadaddr $bootfile;" \ 634 "tftp $fdtaddr $fdtfile;" \ 635 "bootm $loadaddr $ramdiskaddr $fdtaddr" 636 637 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 638 639 #include <asm/fsl_secure_boot.h> 640 641 #endif /* __CONFIG_H */ 642