1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * BSC9132 QDS board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifdef CONFIG_SDCARD 14 #define CONFIG_RAMBOOT_SDCARD 15 #define CONFIG_SYS_RAMBOOT 16 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 17 #endif 18 #ifdef CONFIG_SPIFLASH 19 #define CONFIG_RAMBOOT_SPIFLASH 20 #define CONFIG_SYS_RAMBOOT 21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 22 #endif 23 #ifdef CONFIG_NAND_SECBOOT 24 #define CONFIG_RAMBOOT_NAND 25 #define CONFIG_SYS_RAMBOOT 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 27 #endif 28 29 #ifdef CONFIG_NAND 30 #define CONFIG_SPL_INIT_MINIMAL 31 #define CONFIG_SPL_NAND_BOOT 32 #define CONFIG_SPL_FLUSH_IMAGE 33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 34 35 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 36 #define CONFIG_SPL_MAX_SIZE 8192 37 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 38 #define CONFIG_SPL_RELOC_STACK 0x00100000 39 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 40 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 41 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 42 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 44 #endif 45 46 #ifndef CONFIG_RESET_VECTOR_ADDRESS 47 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 48 #endif 49 50 #ifdef CONFIG_SPL_BUILD 51 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 52 #else 53 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 54 #endif 55 56 /* High Level Configuration Options */ 57 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 58 59 #if defined(CONFIG_PCI) 60 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 61 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 62 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 63 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 65 66 /* 67 * PCI Windows 68 * Memory space is mapped 1-1, but I/O space must start from 0. 69 */ 70 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 71 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 72 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 73 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 74 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 75 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 76 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 77 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 78 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 79 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 80 81 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 82 #endif 83 84 #define CONFIG_ENV_OVERWRITE 85 86 #if defined(CONFIG_SYS_CLK_100_DDR_100) 87 #define CONFIG_SYS_CLK_FREQ 100000000 88 #define CONFIG_DDR_CLK_FREQ 100000000 89 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 90 #define CONFIG_SYS_CLK_FREQ 100000000 91 #define CONFIG_DDR_CLK_FREQ 133000000 92 #endif 93 94 #define CONFIG_HWCONFIG 95 /* 96 * These can be toggled for performance analysis, otherwise use default. 97 */ 98 #define CONFIG_L2_CACHE /* toggle L2 cache */ 99 #define CONFIG_BTB /* enable branch predition */ 100 101 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 102 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 103 104 /* DDR Setup */ 105 #define CONFIG_SYS_SPD_BUS_NUM 0 106 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 107 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 108 #define CONFIG_FSL_DDR_INTERACTIVE 109 110 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 111 112 #define CONFIG_SYS_SDRAM_SIZE (1024) 113 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 114 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 115 116 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 117 118 /* DDR3 Controller Settings */ 119 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 120 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 121 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 122 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 123 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 124 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 125 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 126 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 127 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 128 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 129 130 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 131 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 132 #define CONFIG_SYS_DDR_RCW_1 0x00000000 133 #define CONFIG_SYS_DDR_RCW_2 0x00000000 134 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 135 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 136 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 137 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 138 139 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 140 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 141 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 142 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 143 144 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 145 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 146 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 147 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 148 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 149 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 150 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 151 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 152 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 153 154 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 155 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 156 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 157 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 158 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 159 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 160 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 161 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 162 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 163 164 /*FIXME: the following params are constant w.r.t diff freq 165 combinations. this should be removed later 166 */ 167 #if CONFIG_DDR_CLK_FREQ == 100000000 168 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 169 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 170 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 171 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 172 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 173 #elif CONFIG_DDR_CLK_FREQ == 133000000 174 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 175 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 176 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 177 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 178 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 179 #else 180 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 181 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 182 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 183 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 184 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 185 #endif 186 187 /* relocated CCSRBAR */ 188 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 189 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 190 191 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 192 193 /* DSP CCSRBAR */ 194 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 195 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 196 197 /* 198 * IFC Definitions 199 */ 200 /* NOR Flash on IFC */ 201 202 #define CONFIG_SYS_FLASH_BASE 0x88000000 203 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 204 205 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 206 207 #define CONFIG_SYS_NOR_CSPR 0x88000101 208 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 209 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 210 /* NOR Flash Timing Params */ 211 212 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 213 | FTIM0_NOR_TEADC(0x03) \ 214 | FTIM0_NOR_TAVDS(0x00) \ 215 | FTIM0_NOR_TEAHC(0x0f)) 216 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 217 | FTIM1_NOR_TRAD_NOR(0x09) \ 218 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 219 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 220 | FTIM2_NOR_TCH(0x4) \ 221 | FTIM2_NOR_TWPH(0x7) \ 222 | FTIM2_NOR_TWP(0x1e)) 223 #define CONFIG_SYS_NOR_FTIM3 0x0 224 225 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 226 #define CONFIG_SYS_FLASH_QUIET_TEST 227 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 228 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 229 230 #undef CONFIG_SYS_FLASH_CHECKSUM 231 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 232 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 233 234 /* CFI for NOR Flash */ 235 #define CONFIG_FLASH_CFI_DRIVER 236 #define CONFIG_SYS_FLASH_CFI 237 #define CONFIG_SYS_FLASH_EMPTY_INFO 238 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 239 240 /* NAND Flash on IFC */ 241 #define CONFIG_SYS_NAND_BASE 0xff800000 242 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 243 244 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 245 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 246 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 247 | CSPR_V) 248 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 249 250 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 251 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 252 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 253 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 254 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 255 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 256 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 257 258 /* NAND Flash Timing Params */ 259 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 260 | FTIM0_NAND_TWP(0x05) \ 261 | FTIM0_NAND_TWCHT(0x02) \ 262 | FTIM0_NAND_TWH(0x04)) 263 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 264 | FTIM1_NAND_TWBE(0x1e) \ 265 | FTIM1_NAND_TRR(0x07) \ 266 | FTIM1_NAND_TRP(0x05)) 267 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 268 | FTIM2_NAND_TREH(0x04) \ 269 | FTIM2_NAND_TWHRE(0x11)) 270 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 271 272 #define CONFIG_SYS_NAND_DDR_LAW 11 273 274 /* NAND */ 275 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 276 #define CONFIG_SYS_MAX_NAND_DEVICE 1 277 278 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 279 280 #ifndef CONFIG_SPL_BUILD 281 #define CONFIG_FSL_QIXIS 282 #endif 283 #ifdef CONFIG_FSL_QIXIS 284 #define CONFIG_SYS_FPGA_BASE 0xffb00000 285 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 286 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 287 #define QIXIS_LBMAP_SWITCH 9 288 #define QIXIS_LBMAP_MASK 0x07 289 #define QIXIS_LBMAP_SHIFT 0 290 #define QIXIS_LBMAP_DFLTBANK 0x00 291 #define QIXIS_LBMAP_ALTBANK 0x04 292 #define QIXIS_RST_CTL_RESET 0x83 293 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 294 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 295 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 296 297 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 298 299 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 300 | CSPR_PORT_SIZE_8 \ 301 | CSPR_MSEL_GPCM \ 302 | CSPR_V) 303 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 304 #define CONFIG_SYS_CSOR2 0x0 305 /* CPLD Timing parameters for IFC CS3 */ 306 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 307 FTIM0_GPCM_TEADC(0x0e) | \ 308 FTIM0_GPCM_TEAHC(0x0e)) 309 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 310 FTIM1_GPCM_TRAD(0x1f)) 311 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 312 FTIM2_GPCM_TCH(0x8) | \ 313 FTIM2_GPCM_TWP(0x1f)) 314 #define CONFIG_SYS_CS2_FTIM3 0x0 315 #endif 316 317 /* Set up IFC registers for boot location NOR/NAND */ 318 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 319 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 320 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 321 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 322 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 323 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 324 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 325 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 326 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 327 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 328 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 329 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 330 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 331 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 332 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 333 #else 334 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 335 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 336 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 337 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 338 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 339 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 340 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 341 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 342 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 343 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 344 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 345 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 346 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 347 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 348 #endif 349 350 #define CONFIG_SYS_INIT_RAM_LOCK 351 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 352 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 353 354 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 355 - GENERATED_GBL_DATA_SIZE) 356 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 357 358 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 359 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 360 361 /* Serial Port */ 362 #undef CONFIG_SERIAL_SOFTWARE_FIFO 363 #define CONFIG_SYS_NS16550_SERIAL 364 #define CONFIG_SYS_NS16550_REG_SIZE 1 365 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 366 #ifdef CONFIG_SPL_BUILD 367 #define CONFIG_NS16550_MIN_FUNCTIONS 368 #endif 369 370 #define CONFIG_SYS_BAUDRATE_TABLE \ 371 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 372 373 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 374 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 375 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 376 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 377 378 #define CONFIG_SYS_I2C 379 #define CONFIG_SYS_I2C_FSL 380 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 381 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 382 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 383 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 384 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 385 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 386 387 /* I2C EEPROM */ 388 #define CONFIG_ID_EEPROM 389 #ifdef CONFIG_ID_EEPROM 390 #define CONFIG_SYS_I2C_EEPROM_NXID 391 #endif 392 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 393 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 394 #define CONFIG_SYS_EEPROM_BUS_NUM 0 395 396 /* enable read and write access to EEPROM */ 397 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 398 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 399 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 400 401 /* I2C FPGA */ 402 #define CONFIG_I2C_FPGA 403 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 404 405 #define CONFIG_RTC_DS3231 406 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 407 408 /* 409 * SPI interface will not be available in case of NAND boot SPI CS0 will be 410 * used for SLIC 411 */ 412 /* eSPI - Enhanced SPI */ 413 #ifdef CONFIG_FSL_ESPI 414 #define CONFIG_SF_DEFAULT_SPEED 10000000 415 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 416 #endif 417 418 #if defined(CONFIG_TSEC_ENET) 419 420 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 421 #define CONFIG_TSEC1 1 422 #define CONFIG_TSEC1_NAME "eTSEC1" 423 #define CONFIG_TSEC2 1 424 #define CONFIG_TSEC2_NAME "eTSEC2" 425 426 #define TSEC1_PHY_ADDR 0 427 #define TSEC2_PHY_ADDR 1 428 429 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 430 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 431 432 #define TSEC1_PHYIDX 0 433 #define TSEC2_PHYIDX 0 434 435 #define CONFIG_ETHPRIME "eTSEC1" 436 437 /* TBI PHY configuration for SGMII mode */ 438 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 439 TBICR_PHY_RESET \ 440 | TBICR_ANEG_ENABLE \ 441 | TBICR_FULL_DUPLEX \ 442 | TBICR_SPEED1_SET \ 443 ) 444 445 #endif /* CONFIG_TSEC_ENET */ 446 447 #ifdef CONFIG_MMC 448 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 449 #endif 450 451 #ifdef CONFIG_USB_EHCI_HCD 452 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 453 #define CONFIG_USB_EHCI_FSL 454 #define CONFIG_HAS_FSL_DR_USB 455 #endif 456 457 /* 458 * Environment 459 */ 460 #if defined(CONFIG_RAMBOOT_SDCARD) 461 #define CONFIG_FSL_FIXED_MMC_LOCATION 462 #define CONFIG_SYS_MMC_ENV_DEV 0 463 #define CONFIG_ENV_SIZE 0x2000 464 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 465 #define CONFIG_ENV_SPI_BUS 0 466 #define CONFIG_ENV_SPI_CS 0 467 #define CONFIG_ENV_SPI_MAX_HZ 10000000 468 #define CONFIG_ENV_SPI_MODE 0 469 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 470 #define CONFIG_ENV_SECT_SIZE 0x10000 471 #define CONFIG_ENV_SIZE 0x2000 472 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 473 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 474 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 475 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 476 #elif defined(CONFIG_SYS_RAMBOOT) 477 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 478 #define CONFIG_ENV_SIZE 0x2000 479 #else 480 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 481 #define CONFIG_ENV_SIZE 0x2000 482 #define CONFIG_ENV_SECT_SIZE 0x20000 483 #endif 484 485 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 486 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 487 488 /* 489 * Miscellaneous configurable options 490 */ 491 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 492 493 /* 494 * For booting Linux, the board info and command line data 495 * have to be in the first 64 MB of memory, since this is 496 * the maximum mapped by the Linux kernel during initialization. 497 */ 498 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 499 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 500 501 #if defined(CONFIG_CMD_KGDB) 502 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 503 #endif 504 505 /* 506 * Dynamic MTD Partition support with mtdparts 507 */ 508 #ifdef CONFIG_MTD_NOR_FLASH 509 #define CONFIG_FLASH_CFI_MTD 510 #endif 511 /* 512 * Environment Configuration 513 */ 514 515 #if defined(CONFIG_TSEC_ENET) 516 #define CONFIG_HAS_ETH0 517 #define CONFIG_HAS_ETH1 518 #endif 519 520 #define CONFIG_HOSTNAME "BSC9132qds" 521 #define CONFIG_ROOTPATH "/opt/nfsroot" 522 #define CONFIG_BOOTFILE "uImage" 523 #define CONFIG_UBOOTPATH "u-boot.bin" 524 525 #ifdef CONFIG_SDCARD 526 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 527 #else 528 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 529 #endif 530 531 #define CONFIG_EXTRA_ENV_SETTINGS \ 532 "netdev=eth0\0" \ 533 "uboot=" CONFIG_UBOOTPATH "\0" \ 534 "loadaddr=1000000\0" \ 535 "bootfile=uImage\0" \ 536 "consoledev=ttyS0\0" \ 537 "ramdiskaddr=2000000\0" \ 538 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 539 "fdtaddr=1e00000\0" \ 540 "fdtfile=bsc9132qds.dtb\0" \ 541 "bdev=sda1\0" \ 542 CONFIG_DEF_HWCONFIG\ 543 "othbootargs=mem=880M ramdisk_size=600000 " \ 544 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 545 "isolcpus=0\0" \ 546 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 547 "console=$consoledev,$baudrate $othbootargs; " \ 548 "usb start;" \ 549 "ext2load usb 0:4 $loadaddr $bootfile;" \ 550 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 551 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 552 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 553 "debug_halt_off=mw ff7e0e30 0xf0000000;" 554 555 #define CONFIG_NFSBOOTCOMMAND \ 556 "setenv bootargs root=/dev/nfs rw " \ 557 "nfsroot=$serverip:$rootpath " \ 558 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 559 "console=$consoledev,$baudrate $othbootargs;" \ 560 "tftp $loadaddr $bootfile;" \ 561 "tftp $fdtaddr $fdtfile;" \ 562 "bootm $loadaddr - $fdtaddr" 563 564 #define CONFIG_HDBOOT \ 565 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 566 "console=$consoledev,$baudrate $othbootargs;" \ 567 "usb start;" \ 568 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 569 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 570 "bootm $loadaddr - $fdtaddr" 571 572 #define CONFIG_RAMBOOTCOMMAND \ 573 "setenv bootargs root=/dev/ram rw " \ 574 "console=$consoledev,$baudrate $othbootargs; " \ 575 "tftp $ramdiskaddr $ramdiskfile;" \ 576 "tftp $loadaddr $bootfile;" \ 577 "tftp $fdtaddr $fdtfile;" \ 578 "bootm $loadaddr $ramdiskaddr $fdtaddr" 579 580 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 581 582 #include <asm/fsl_secure_boot.h> 583 584 #endif /* __CONFIG_H */ 585