1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * BSC9132 QDS board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifdef CONFIG_SDCARD 14 #define CONFIG_RAMBOOT_SDCARD 15 #define CONFIG_SYS_RAMBOOT 16 #define CONFIG_SYS_EXTRA_ENV_RELOC 17 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 18 #endif 19 #ifdef CONFIG_SPIFLASH 20 #define CONFIG_RAMBOOT_SPIFLASH 21 #define CONFIG_SYS_RAMBOOT 22 #define CONFIG_SYS_EXTRA_ENV_RELOC 23 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 24 #endif 25 #ifdef CONFIG_NAND_SECBOOT 26 #define CONFIG_RAMBOOT_NAND 27 #define CONFIG_SYS_RAMBOOT 28 #define CONFIG_SYS_EXTRA_ENV_RELOC 29 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 30 #endif 31 32 #ifdef CONFIG_NAND 33 #define CONFIG_SPL_INIT_MINIMAL 34 #define CONFIG_SPL_NAND_BOOT 35 #define CONFIG_SPL_FLUSH_IMAGE 36 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 37 38 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 39 #define CONFIG_SPL_MAX_SIZE 8192 40 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 41 #define CONFIG_SPL_RELOC_STACK 0x00100000 42 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 43 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 44 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 45 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 46 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 47 #endif 48 49 #ifndef CONFIG_RESET_VECTOR_ADDRESS 50 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 51 #endif 52 53 #ifdef CONFIG_SPL_BUILD 54 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 55 #else 56 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 57 #endif 58 59 /* High Level Configuration Options */ 60 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 61 62 #if defined(CONFIG_PCI) 63 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 64 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 65 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 66 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 67 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 68 69 /* 70 * PCI Windows 71 * Memory space is mapped 1-1, but I/O space must start from 0. 72 */ 73 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 74 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 75 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 76 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 77 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 78 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 79 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 80 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 81 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 82 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 83 84 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 85 #endif 86 87 #define CONFIG_ENV_OVERWRITE 88 89 #if defined(CONFIG_SYS_CLK_100_DDR_100) 90 #define CONFIG_SYS_CLK_FREQ 100000000 91 #define CONFIG_DDR_CLK_FREQ 100000000 92 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 93 #define CONFIG_SYS_CLK_FREQ 100000000 94 #define CONFIG_DDR_CLK_FREQ 133000000 95 #endif 96 97 #define CONFIG_HWCONFIG 98 /* 99 * These can be toggled for performance analysis, otherwise use default. 100 */ 101 #define CONFIG_L2_CACHE /* toggle L2 cache */ 102 #define CONFIG_BTB /* enable branch predition */ 103 104 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 105 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 106 107 /* DDR Setup */ 108 #define CONFIG_SYS_SPD_BUS_NUM 0 109 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 110 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 111 #define CONFIG_FSL_DDR_INTERACTIVE 112 113 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 114 115 #define CONFIG_SYS_SDRAM_SIZE (1024) 116 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 117 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 118 119 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 120 121 /* DDR3 Controller Settings */ 122 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 123 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 124 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 125 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 126 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 127 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 128 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 129 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 130 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 131 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 132 133 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 134 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 135 #define CONFIG_SYS_DDR_RCW_1 0x00000000 136 #define CONFIG_SYS_DDR_RCW_2 0x00000000 137 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 138 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 139 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 140 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 141 142 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 143 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 144 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 145 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 146 147 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 148 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 149 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 150 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 151 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 152 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 153 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 154 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 155 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 156 157 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 158 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 159 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 160 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 161 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 162 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 163 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 164 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 165 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 166 167 /*FIXME: the following params are constant w.r.t diff freq 168 combinations. this should be removed later 169 */ 170 #if CONFIG_DDR_CLK_FREQ == 100000000 171 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 172 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 173 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 174 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 175 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 176 #elif CONFIG_DDR_CLK_FREQ == 133000000 177 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 178 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 179 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 180 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 181 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 182 #else 183 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 184 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 185 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 186 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 187 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 188 #endif 189 190 /* relocated CCSRBAR */ 191 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 192 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 193 194 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 195 196 /* DSP CCSRBAR */ 197 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 198 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 199 200 /* 201 * IFC Definitions 202 */ 203 /* NOR Flash on IFC */ 204 205 #define CONFIG_SYS_FLASH_BASE 0x88000000 206 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 207 208 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 209 210 #define CONFIG_SYS_NOR_CSPR 0x88000101 211 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 212 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 213 /* NOR Flash Timing Params */ 214 215 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 216 | FTIM0_NOR_TEADC(0x03) \ 217 | FTIM0_NOR_TAVDS(0x00) \ 218 | FTIM0_NOR_TEAHC(0x0f)) 219 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 220 | FTIM1_NOR_TRAD_NOR(0x09) \ 221 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 222 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 223 | FTIM2_NOR_TCH(0x4) \ 224 | FTIM2_NOR_TWPH(0x7) \ 225 | FTIM2_NOR_TWP(0x1e)) 226 #define CONFIG_SYS_NOR_FTIM3 0x0 227 228 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 229 #define CONFIG_SYS_FLASH_QUIET_TEST 230 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 231 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 232 233 #undef CONFIG_SYS_FLASH_CHECKSUM 234 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 235 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 236 237 /* CFI for NOR Flash */ 238 #define CONFIG_FLASH_CFI_DRIVER 239 #define CONFIG_SYS_FLASH_CFI 240 #define CONFIG_SYS_FLASH_EMPTY_INFO 241 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 242 243 /* NAND Flash on IFC */ 244 #define CONFIG_SYS_NAND_BASE 0xff800000 245 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 246 247 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 248 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 249 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 250 | CSPR_V) 251 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 252 253 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 254 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 255 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 256 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 257 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 258 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 259 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 260 261 /* NAND Flash Timing Params */ 262 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 263 | FTIM0_NAND_TWP(0x05) \ 264 | FTIM0_NAND_TWCHT(0x02) \ 265 | FTIM0_NAND_TWH(0x04)) 266 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 267 | FTIM1_NAND_TWBE(0x1e) \ 268 | FTIM1_NAND_TRR(0x07) \ 269 | FTIM1_NAND_TRP(0x05)) 270 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 271 | FTIM2_NAND_TREH(0x04) \ 272 | FTIM2_NAND_TWHRE(0x11)) 273 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 274 275 #define CONFIG_SYS_NAND_DDR_LAW 11 276 277 /* NAND */ 278 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 279 #define CONFIG_SYS_MAX_NAND_DEVICE 1 280 281 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 282 283 #ifndef CONFIG_SPL_BUILD 284 #define CONFIG_FSL_QIXIS 285 #endif 286 #ifdef CONFIG_FSL_QIXIS 287 #define CONFIG_SYS_FPGA_BASE 0xffb00000 288 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 289 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 290 #define QIXIS_LBMAP_SWITCH 9 291 #define QIXIS_LBMAP_MASK 0x07 292 #define QIXIS_LBMAP_SHIFT 0 293 #define QIXIS_LBMAP_DFLTBANK 0x00 294 #define QIXIS_LBMAP_ALTBANK 0x04 295 #define QIXIS_RST_CTL_RESET 0x83 296 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 297 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 298 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 299 300 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 301 302 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 303 | CSPR_PORT_SIZE_8 \ 304 | CSPR_MSEL_GPCM \ 305 | CSPR_V) 306 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 307 #define CONFIG_SYS_CSOR2 0x0 308 /* CPLD Timing parameters for IFC CS3 */ 309 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 310 FTIM0_GPCM_TEADC(0x0e) | \ 311 FTIM0_GPCM_TEAHC(0x0e)) 312 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 313 FTIM1_GPCM_TRAD(0x1f)) 314 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 315 FTIM2_GPCM_TCH(0x8) | \ 316 FTIM2_GPCM_TWP(0x1f)) 317 #define CONFIG_SYS_CS2_FTIM3 0x0 318 #endif 319 320 /* Set up IFC registers for boot location NOR/NAND */ 321 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 322 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 323 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 324 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 325 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 326 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 327 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 328 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 329 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 330 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 331 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 332 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 333 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 334 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 335 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 336 #else 337 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 338 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 339 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 340 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 341 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 342 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 343 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 344 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 345 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 346 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 347 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 348 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 349 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 350 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 351 #endif 352 353 #define CONFIG_SYS_INIT_RAM_LOCK 354 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 355 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 356 357 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 358 - GENERATED_GBL_DATA_SIZE) 359 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 360 361 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 362 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 363 364 /* Serial Port */ 365 #undef CONFIG_SERIAL_SOFTWARE_FIFO 366 #define CONFIG_SYS_NS16550_SERIAL 367 #define CONFIG_SYS_NS16550_REG_SIZE 1 368 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 369 #ifdef CONFIG_SPL_BUILD 370 #define CONFIG_NS16550_MIN_FUNCTIONS 371 #endif 372 373 #define CONFIG_SYS_BAUDRATE_TABLE \ 374 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 375 376 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 377 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 378 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 379 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 380 381 #define CONFIG_SYS_I2C 382 #define CONFIG_SYS_I2C_FSL 383 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 384 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 385 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 386 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 387 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 388 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 389 390 /* I2C EEPROM */ 391 #define CONFIG_ID_EEPROM 392 #ifdef CONFIG_ID_EEPROM 393 #define CONFIG_SYS_I2C_EEPROM_NXID 394 #endif 395 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 396 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 397 #define CONFIG_SYS_EEPROM_BUS_NUM 0 398 399 /* enable read and write access to EEPROM */ 400 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 401 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 402 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 403 404 /* I2C FPGA */ 405 #define CONFIG_I2C_FPGA 406 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 407 408 #define CONFIG_RTC_DS3231 409 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 410 411 /* 412 * SPI interface will not be available in case of NAND boot SPI CS0 will be 413 * used for SLIC 414 */ 415 /* eSPI - Enhanced SPI */ 416 #ifdef CONFIG_FSL_ESPI 417 #define CONFIG_SF_DEFAULT_SPEED 10000000 418 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 419 #endif 420 421 #if defined(CONFIG_TSEC_ENET) 422 423 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 424 #define CONFIG_TSEC1 1 425 #define CONFIG_TSEC1_NAME "eTSEC1" 426 #define CONFIG_TSEC2 1 427 #define CONFIG_TSEC2_NAME "eTSEC2" 428 429 #define TSEC1_PHY_ADDR 0 430 #define TSEC2_PHY_ADDR 1 431 432 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 433 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 434 435 #define TSEC1_PHYIDX 0 436 #define TSEC2_PHYIDX 0 437 438 #define CONFIG_ETHPRIME "eTSEC1" 439 440 /* TBI PHY configuration for SGMII mode */ 441 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 442 TBICR_PHY_RESET \ 443 | TBICR_ANEG_ENABLE \ 444 | TBICR_FULL_DUPLEX \ 445 | TBICR_SPEED1_SET \ 446 ) 447 448 #endif /* CONFIG_TSEC_ENET */ 449 450 #ifdef CONFIG_MMC 451 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 452 #endif 453 454 #ifdef CONFIG_USB_EHCI_HCD 455 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 456 #define CONFIG_USB_EHCI_FSL 457 #define CONFIG_HAS_FSL_DR_USB 458 #endif 459 460 /* 461 * Environment 462 */ 463 #if defined(CONFIG_RAMBOOT_SDCARD) 464 #define CONFIG_FSL_FIXED_MMC_LOCATION 465 #define CONFIG_SYS_MMC_ENV_DEV 0 466 #define CONFIG_ENV_SIZE 0x2000 467 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 468 #define CONFIG_ENV_SPI_BUS 0 469 #define CONFIG_ENV_SPI_CS 0 470 #define CONFIG_ENV_SPI_MAX_HZ 10000000 471 #define CONFIG_ENV_SPI_MODE 0 472 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 473 #define CONFIG_ENV_SECT_SIZE 0x10000 474 #define CONFIG_ENV_SIZE 0x2000 475 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 476 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 477 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 478 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 479 #elif defined(CONFIG_SYS_RAMBOOT) 480 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 481 #define CONFIG_ENV_SIZE 0x2000 482 #else 483 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 484 #define CONFIG_ENV_SIZE 0x2000 485 #define CONFIG_ENV_SECT_SIZE 0x20000 486 #endif 487 488 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 489 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 490 491 /* 492 * Miscellaneous configurable options 493 */ 494 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 495 496 /* 497 * For booting Linux, the board info and command line data 498 * have to be in the first 64 MB of memory, since this is 499 * the maximum mapped by the Linux kernel during initialization. 500 */ 501 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 502 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 503 504 #if defined(CONFIG_CMD_KGDB) 505 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 506 #endif 507 508 /* 509 * Dynamic MTD Partition support with mtdparts 510 */ 511 #ifdef CONFIG_MTD_NOR_FLASH 512 #define CONFIG_FLASH_CFI_MTD 513 #endif 514 /* 515 * Environment Configuration 516 */ 517 518 #if defined(CONFIG_TSEC_ENET) 519 #define CONFIG_HAS_ETH0 520 #define CONFIG_HAS_ETH1 521 #endif 522 523 #define CONFIG_HOSTNAME "BSC9132qds" 524 #define CONFIG_ROOTPATH "/opt/nfsroot" 525 #define CONFIG_BOOTFILE "uImage" 526 #define CONFIG_UBOOTPATH "u-boot.bin" 527 528 #ifdef CONFIG_SDCARD 529 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 530 #else 531 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 532 #endif 533 534 #define CONFIG_EXTRA_ENV_SETTINGS \ 535 "netdev=eth0\0" \ 536 "uboot=" CONFIG_UBOOTPATH "\0" \ 537 "loadaddr=1000000\0" \ 538 "bootfile=uImage\0" \ 539 "consoledev=ttyS0\0" \ 540 "ramdiskaddr=2000000\0" \ 541 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 542 "fdtaddr=1e00000\0" \ 543 "fdtfile=bsc9132qds.dtb\0" \ 544 "bdev=sda1\0" \ 545 CONFIG_DEF_HWCONFIG\ 546 "othbootargs=mem=880M ramdisk_size=600000 " \ 547 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 548 "isolcpus=0\0" \ 549 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 550 "console=$consoledev,$baudrate $othbootargs; " \ 551 "usb start;" \ 552 "ext2load usb 0:4 $loadaddr $bootfile;" \ 553 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 554 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 555 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 556 "debug_halt_off=mw ff7e0e30 0xf0000000;" 557 558 #define CONFIG_NFSBOOTCOMMAND \ 559 "setenv bootargs root=/dev/nfs rw " \ 560 "nfsroot=$serverip:$rootpath " \ 561 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 562 "console=$consoledev,$baudrate $othbootargs;" \ 563 "tftp $loadaddr $bootfile;" \ 564 "tftp $fdtaddr $fdtfile;" \ 565 "bootm $loadaddr - $fdtaddr" 566 567 #define CONFIG_HDBOOT \ 568 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 569 "console=$consoledev,$baudrate $othbootargs;" \ 570 "usb start;" \ 571 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 572 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 573 "bootm $loadaddr - $fdtaddr" 574 575 #define CONFIG_RAMBOOTCOMMAND \ 576 "setenv bootargs root=/dev/ram rw " \ 577 "console=$consoledev,$baudrate $othbootargs; " \ 578 "tftp $ramdiskaddr $ramdiskfile;" \ 579 "tftp $loadaddr $bootfile;" \ 580 "tftp $fdtaddr $fdtfile;" \ 581 "bootm $loadaddr $ramdiskaddr $fdtaddr" 582 583 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 584 585 #include <asm/fsl_secure_boot.h> 586 587 #endif /* __CONFIG_H */ 588