1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9132 QDS board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 #define CONFIG_DISPLAY_BOARDINFO 16 17 #ifdef CONFIG_BSC9132QDS 18 #define CONFIG_BSC9132 19 #endif 20 21 #define CONFIG_MISC_INIT_R 22 23 #ifdef CONFIG_SDCARD 24 #define CONFIG_RAMBOOT_SDCARD 25 #define CONFIG_SYS_RAMBOOT 26 #define CONFIG_SYS_EXTRA_ENV_RELOC 27 #define CONFIG_SYS_TEXT_BASE 0x11000000 28 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 29 #endif 30 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 31 #ifdef CONFIG_SPIFLASH 32 #define CONFIG_RAMBOOT_SPIFLASH 33 #define CONFIG_SYS_RAMBOOT 34 #define CONFIG_SYS_EXTRA_ENV_RELOC 35 #define CONFIG_SYS_TEXT_BASE 0x11000000 36 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 37 #endif 38 #ifdef CONFIG_NAND_SECBOOT 39 #define CONFIG_RAMBOOT_NAND 40 #define CONFIG_SYS_RAMBOOT 41 #define CONFIG_SYS_EXTRA_ENV_RELOC 42 #define CONFIG_SYS_TEXT_BASE 0x11000000 43 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 44 #endif 45 46 #ifdef CONFIG_NAND 47 #define CONFIG_SPL_INIT_MINIMAL 48 #define CONFIG_SPL_SERIAL_SUPPORT 49 #define CONFIG_SPL_NAND_SUPPORT 50 #define CONFIG_SPL_NAND_BOOT 51 #define CONFIG_SPL_FLUSH_IMAGE 52 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 53 54 #define CONFIG_SYS_TEXT_BASE 0x00201000 55 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 56 #define CONFIG_SPL_MAX_SIZE 8192 57 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 58 #define CONFIG_SPL_RELOC_STACK 0x00100000 59 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 60 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 61 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 62 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 63 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 64 #endif 65 66 #ifndef CONFIG_SYS_TEXT_BASE 67 #define CONFIG_SYS_TEXT_BASE 0x8ff40000 68 #endif 69 70 #ifndef CONFIG_RESET_VECTOR_ADDRESS 71 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 72 #endif 73 74 #ifdef CONFIG_SPL_BUILD 75 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 76 #else 77 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 78 #endif 79 80 /* High Level Configuration Options */ 81 #define CONFIG_BOOKE /* BOOKE */ 82 #define CONFIG_E500 /* BOOKE e500 family */ 83 #define CONFIG_FSL_IFC /* Enable IFC Support */ 84 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 85 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 86 87 #define CONFIG_PCI /* Enable PCI/PCIE */ 88 #if defined(CONFIG_PCI) 89 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 90 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 91 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 92 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 93 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 94 95 #define CONFIG_CMD_PCI 96 97 98 /* 99 * PCI Windows 100 * Memory space is mapped 1-1, but I/O space must start from 0. 101 */ 102 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 103 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 104 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 105 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 106 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 107 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 108 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 109 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 110 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 111 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 112 113 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 114 115 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 116 #define CONFIG_DOS_PARTITION 117 #endif 118 119 #define CONFIG_FSL_LAW /* Use common FSL init code */ 120 #define CONFIG_ENV_OVERWRITE 121 #define CONFIG_TSEC_ENET /* ethernet */ 122 123 #if defined(CONFIG_SYS_CLK_100_DDR_100) 124 #define CONFIG_SYS_CLK_FREQ 100000000 125 #define CONFIG_DDR_CLK_FREQ 100000000 126 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 127 #define CONFIG_SYS_CLK_FREQ 100000000 128 #define CONFIG_DDR_CLK_FREQ 133000000 129 #endif 130 131 #define CONFIG_MP 132 133 #define CONFIG_HWCONFIG 134 /* 135 * These can be toggled for performance analysis, otherwise use default. 136 */ 137 #define CONFIG_L2_CACHE /* toggle L2 cache */ 138 #define CONFIG_BTB /* enable branch predition */ 139 140 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 141 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 142 143 /* DDR Setup */ 144 #define CONFIG_SYS_FSL_DDR3 145 #define CONFIG_SYS_SPD_BUS_NUM 0 146 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 147 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 148 #define CONFIG_FSL_DDR_INTERACTIVE 149 150 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 151 152 #define CONFIG_SYS_SDRAM_SIZE (1024) 153 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 154 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 155 156 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 157 158 /* DDR3 Controller Settings */ 159 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 160 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 161 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 162 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 163 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 164 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 165 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 166 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 167 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 168 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 169 170 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 171 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 172 #define CONFIG_SYS_DDR_RCW_1 0x00000000 173 #define CONFIG_SYS_DDR_RCW_2 0x00000000 174 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 175 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 176 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 177 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 178 179 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 180 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 181 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 182 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 183 184 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 185 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 186 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 187 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 188 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 189 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 190 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 191 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 192 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 193 194 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 195 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 196 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 197 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 198 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 199 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 200 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 201 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 202 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 203 204 /*FIXME: the following params are constant w.r.t diff freq 205 combinations. this should be removed later 206 */ 207 #if CONFIG_DDR_CLK_FREQ == 100000000 208 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 209 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 210 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 211 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 212 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 213 #elif CONFIG_DDR_CLK_FREQ == 133000000 214 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 215 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 216 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 217 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 218 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 219 #else 220 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 221 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 222 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 223 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 224 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 225 #endif 226 227 228 /* relocated CCSRBAR */ 229 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 230 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 231 232 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 233 234 /* DSP CCSRBAR */ 235 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 236 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 237 238 /* 239 * IFC Definitions 240 */ 241 /* NOR Flash on IFC */ 242 243 #ifdef CONFIG_SPL_BUILD 244 #define CONFIG_SYS_NO_FLASH 245 #endif 246 #define CONFIG_SYS_FLASH_BASE 0x88000000 247 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 248 249 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 250 251 #define CONFIG_SYS_NOR_CSPR 0x88000101 252 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 253 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 254 /* NOR Flash Timing Params */ 255 256 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 257 | FTIM0_NOR_TEADC(0x03) \ 258 | FTIM0_NOR_TAVDS(0x00) \ 259 | FTIM0_NOR_TEAHC(0x0f)) 260 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 261 | FTIM1_NOR_TRAD_NOR(0x09) \ 262 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 263 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 264 | FTIM2_NOR_TCH(0x4) \ 265 | FTIM2_NOR_TWPH(0x7) \ 266 | FTIM2_NOR_TWP(0x1e)) 267 #define CONFIG_SYS_NOR_FTIM3 0x0 268 269 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 270 #define CONFIG_SYS_FLASH_QUIET_TEST 271 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 272 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 273 274 #undef CONFIG_SYS_FLASH_CHECKSUM 275 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 276 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 277 278 /* CFI for NOR Flash */ 279 #define CONFIG_FLASH_CFI_DRIVER 280 #define CONFIG_SYS_FLASH_CFI 281 #define CONFIG_SYS_FLASH_EMPTY_INFO 282 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 283 284 /* NAND Flash on IFC */ 285 #define CONFIG_SYS_NAND_BASE 0xff800000 286 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 287 288 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 289 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 290 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 291 | CSPR_V) 292 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 293 294 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 295 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 296 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 297 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 298 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 299 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 300 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 301 302 /* NAND Flash Timing Params */ 303 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 304 | FTIM0_NAND_TWP(0x05) \ 305 | FTIM0_NAND_TWCHT(0x02) \ 306 | FTIM0_NAND_TWH(0x04)) 307 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 308 | FTIM1_NAND_TWBE(0x1e) \ 309 | FTIM1_NAND_TRR(0x07) \ 310 | FTIM1_NAND_TRP(0x05)) 311 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 312 | FTIM2_NAND_TREH(0x04) \ 313 | FTIM2_NAND_TWHRE(0x11)) 314 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 315 316 #define CONFIG_SYS_NAND_DDR_LAW 11 317 318 /* NAND */ 319 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 320 #define CONFIG_SYS_MAX_NAND_DEVICE 1 321 #define CONFIG_CMD_NAND 322 323 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 324 325 #ifndef CONFIG_SPL_BUILD 326 #define CONFIG_FSL_QIXIS 327 #endif 328 #ifdef CONFIG_FSL_QIXIS 329 #define CONFIG_SYS_FPGA_BASE 0xffb00000 330 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 331 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 332 #define QIXIS_LBMAP_SWITCH 9 333 #define QIXIS_LBMAP_MASK 0x07 334 #define QIXIS_LBMAP_SHIFT 0 335 #define QIXIS_LBMAP_DFLTBANK 0x00 336 #define QIXIS_LBMAP_ALTBANK 0x04 337 #define QIXIS_RST_CTL_RESET 0x83 338 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 339 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 340 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 341 342 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 343 344 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 345 | CSPR_PORT_SIZE_8 \ 346 | CSPR_MSEL_GPCM \ 347 | CSPR_V) 348 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 349 #define CONFIG_SYS_CSOR2 0x0 350 /* CPLD Timing parameters for IFC CS3 */ 351 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 352 FTIM0_GPCM_TEADC(0x0e) | \ 353 FTIM0_GPCM_TEAHC(0x0e)) 354 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 355 FTIM1_GPCM_TRAD(0x1f)) 356 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 357 FTIM2_GPCM_TCH(0x8) | \ 358 FTIM2_GPCM_TWP(0x1f)) 359 #define CONFIG_SYS_CS2_FTIM3 0x0 360 #endif 361 362 /* Set up IFC registers for boot location NOR/NAND */ 363 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 364 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 365 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 366 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 367 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 368 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 369 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 370 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 371 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 372 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 373 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 374 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 375 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 376 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 377 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 378 #else 379 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 380 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 381 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 382 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 383 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 384 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 385 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 386 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 387 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 388 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 389 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 390 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 391 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 392 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 393 #endif 394 395 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 396 #define CONFIG_BOARD_EARLY_INIT_R 397 398 #define CONFIG_SYS_INIT_RAM_LOCK 399 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 400 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 401 402 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 403 - GENERATED_GBL_DATA_SIZE) 404 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 405 406 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 407 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 408 409 /* Serial Port */ 410 #define CONFIG_CONS_INDEX 1 411 #undef CONFIG_SERIAL_SOFTWARE_FIFO 412 #define CONFIG_SYS_NS16550 413 #define CONFIG_SYS_NS16550_SERIAL 414 #define CONFIG_SYS_NS16550_REG_SIZE 1 415 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 416 #ifdef CONFIG_SPL_BUILD 417 #define CONFIG_NS16550_MIN_FUNCTIONS 418 #endif 419 420 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 421 422 #define CONFIG_SYS_BAUDRATE_TABLE \ 423 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 424 425 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 426 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 427 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 428 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 429 430 /* Use the HUSH parser */ 431 #define CONFIG_SYS_HUSH_PARSER /* hush parser */ 432 #ifdef CONFIG_SYS_HUSH_PARSER 433 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 434 #endif 435 436 /* 437 * Pass open firmware flat tree 438 */ 439 #define CONFIG_OF_LIBFDT 440 #define CONFIG_OF_BOARD_SETUP 441 #define CONFIG_OF_STDOUT_VIA_ALIAS 442 443 /* new uImage format support */ 444 #define CONFIG_FIT 445 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 446 447 #define CONFIG_SYS_I2C 448 #define CONFIG_SYS_I2C_FSL 449 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 450 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 451 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 452 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 453 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 454 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 455 456 /* I2C EEPROM */ 457 #define CONFIG_ID_EEPROM 458 #ifdef CONFIG_ID_EEPROM 459 #define CONFIG_SYS_I2C_EEPROM_NXID 460 #endif 461 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 462 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 463 #define CONFIG_SYS_EEPROM_BUS_NUM 0 464 465 /* enable read and write access to EEPROM */ 466 #define CONFIG_CMD_EEPROM 467 #define CONFIG_SYS_I2C_MULTI_EEPROMS 468 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 469 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 470 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 471 472 /* I2C FPGA */ 473 #define CONFIG_I2C_FPGA 474 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 475 476 #define CONFIG_RTC_DS3231 477 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 478 479 /* 480 * SPI interface will not be available in case of NAND boot SPI CS0 will be 481 * used for SLIC 482 */ 483 /* eSPI - Enhanced SPI */ 484 #define CONFIG_FSL_ESPI /* SPI */ 485 #ifdef CONFIG_FSL_ESPI 486 #define CONFIG_SPI_FLASH_SPANSION 487 #define CONFIG_CMD_SF 488 #define CONFIG_SF_DEFAULT_SPEED 10000000 489 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 490 #endif 491 492 #if defined(CONFIG_TSEC_ENET) 493 494 #define CONFIG_MII /* MII PHY management */ 495 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 496 #define CONFIG_TSEC1 1 497 #define CONFIG_TSEC1_NAME "eTSEC1" 498 #define CONFIG_TSEC2 1 499 #define CONFIG_TSEC2_NAME "eTSEC2" 500 501 #define TSEC1_PHY_ADDR 0 502 #define TSEC2_PHY_ADDR 1 503 504 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 505 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 506 507 #define TSEC1_PHYIDX 0 508 #define TSEC2_PHYIDX 0 509 510 #define CONFIG_ETHPRIME "eTSEC1" 511 512 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 513 514 /* TBI PHY configuration for SGMII mode */ 515 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 516 TBICR_PHY_RESET \ 517 | TBICR_ANEG_ENABLE \ 518 | TBICR_FULL_DUPLEX \ 519 | TBICR_SPEED1_SET \ 520 ) 521 522 #endif /* CONFIG_TSEC_ENET */ 523 524 #define CONFIG_MMC 525 #ifdef CONFIG_MMC 526 #define CONFIG_CMD_MMC 527 #define CONFIG_DOS_PARTITION 528 #define CONFIG_FSL_ESDHC 529 #define CONFIG_GENERIC_MMC 530 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 531 #endif 532 533 #define CONFIG_USB_EHCI /* USB */ 534 #ifdef CONFIG_USB_EHCI 535 #define CONFIG_CMD_USB 536 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 537 #define CONFIG_USB_EHCI_FSL 538 #define CONFIG_USB_STORAGE 539 #define CONFIG_HAS_FSL_DR_USB 540 #endif 541 542 /* 543 * Environment 544 */ 545 #if defined(CONFIG_RAMBOOT_SDCARD) 546 #define CONFIG_ENV_IS_IN_MMC 547 #define CONFIG_FSL_FIXED_MMC_LOCATION 548 #define CONFIG_SYS_MMC_ENV_DEV 0 549 #define CONFIG_ENV_SIZE 0x2000 550 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 551 #define CONFIG_ENV_IS_IN_SPI_FLASH 552 #define CONFIG_ENV_SPI_BUS 0 553 #define CONFIG_ENV_SPI_CS 0 554 #define CONFIG_ENV_SPI_MAX_HZ 10000000 555 #define CONFIG_ENV_SPI_MODE 0 556 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 557 #define CONFIG_ENV_SECT_SIZE 0x10000 558 #define CONFIG_ENV_SIZE 0x2000 559 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 560 #define CONFIG_ENV_IS_IN_NAND 561 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 562 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 563 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 564 #elif defined(CONFIG_SYS_RAMBOOT) 565 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 566 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 567 #define CONFIG_ENV_SIZE 0x2000 568 #else 569 #define CONFIG_ENV_IS_IN_FLASH 570 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 571 #define CONFIG_ENV_SIZE 0x2000 572 #define CONFIG_ENV_SECT_SIZE 0x20000 573 #endif 574 575 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 576 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 577 578 /* 579 * Command line configuration. 580 */ 581 #define CONFIG_CMD_DATE 582 #define CONFIG_CMD_DHCP 583 #define CONFIG_CMD_ELF 584 #define CONFIG_CMD_ERRATA 585 #define CONFIG_CMD_I2C 586 #define CONFIG_CMD_IRQ 587 #define CONFIG_CMD_MII 588 #define CONFIG_CMD_PING 589 #define CONFIG_CMD_REGINFO 590 591 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 592 #define CONFIG_CMD_EXT2 593 #define CONFIG_CMD_FAT 594 #define CONFIG_DOS_PARTITION 595 #endif 596 597 /* Hash command with SHA acceleration supported in hardware */ 598 #ifdef CONFIG_FSL_CAAM 599 #define CONFIG_CMD_HASH 600 #define CONFIG_SHA_HW_ACCEL 601 #endif 602 603 /* 604 * Miscellaneous configurable options 605 */ 606 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 607 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 608 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 609 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 610 611 #if defined(CONFIG_CMD_KGDB) 612 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 613 #else 614 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 615 #endif 616 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 617 /* Print Buffer Size */ 618 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 619 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 620 621 622 /* 623 * For booting Linux, the board info and command line data 624 * have to be in the first 64 MB of memory, since this is 625 * the maximum mapped by the Linux kernel during initialization. 626 */ 627 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 628 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 629 630 #if defined(CONFIG_CMD_KGDB) 631 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 632 #endif 633 634 /* 635 * Dynamic MTD Partition support with mtdparts 636 */ 637 #ifndef CONFIG_SYS_NO_FLASH 638 #define CONFIG_MTD_DEVICE 639 #define CONFIG_MTD_PARTITIONS 640 #define CONFIG_CMD_MTDPARTS 641 #define CONFIG_FLASH_CFI_MTD 642 #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," 643 #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ 644 "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ 645 "8m(kernel),512k(dtb),-(fs)" 646 #endif 647 /* 648 * Override partitions in device tree using info 649 * in "mtdparts" environment variable 650 */ 651 #ifdef CONFIG_CMD_MTDPARTS 652 #define CONFIG_FDT_FIXUP_PARTITIONS 653 #endif 654 655 /* 656 * Environment Configuration 657 */ 658 659 #if defined(CONFIG_TSEC_ENET) 660 #define CONFIG_HAS_ETH0 661 #define CONFIG_HAS_ETH1 662 #endif 663 664 #define CONFIG_HOSTNAME BSC9132qds 665 #define CONFIG_ROOTPATH "/opt/nfsroot" 666 #define CONFIG_BOOTFILE "uImage" 667 #define CONFIG_UBOOTPATH "u-boot.bin" 668 669 #define CONFIG_BAUDRATE 115200 670 #define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */ 671 672 #ifdef CONFIG_SDCARD 673 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 674 #else 675 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 676 #endif 677 678 #define CONFIG_EXTRA_ENV_SETTINGS \ 679 "netdev=eth0\0" \ 680 "uboot=" CONFIG_UBOOTPATH "\0" \ 681 "loadaddr=1000000\0" \ 682 "bootfile=uImage\0" \ 683 "consoledev=ttyS0\0" \ 684 "ramdiskaddr=2000000\0" \ 685 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 686 "fdtaddr=c00000\0" \ 687 "fdtfile=bsc9132qds.dtb\0" \ 688 "bdev=sda1\0" \ 689 CONFIG_DEF_HWCONFIG\ 690 "othbootargs=mem=880M ramdisk_size=600000 " \ 691 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 692 "isolcpus=0\0" \ 693 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 694 "console=$consoledev,$baudrate $othbootargs; " \ 695 "usb start;" \ 696 "ext2load usb 0:4 $loadaddr $bootfile;" \ 697 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 698 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 699 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 700 "debug_halt_off=mw ff7e0e30 0xf0000000;" 701 702 #define CONFIG_NFSBOOTCOMMAND \ 703 "setenv bootargs root=/dev/nfs rw " \ 704 "nfsroot=$serverip:$rootpath " \ 705 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 706 "console=$consoledev,$baudrate $othbootargs;" \ 707 "tftp $loadaddr $bootfile;" \ 708 "tftp $fdtaddr $fdtfile;" \ 709 "bootm $loadaddr - $fdtaddr" 710 711 #define CONFIG_HDBOOT \ 712 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 713 "console=$consoledev,$baudrate $othbootargs;" \ 714 "usb start;" \ 715 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 716 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 717 "bootm $loadaddr - $fdtaddr" 718 719 #define CONFIG_RAMBOOTCOMMAND \ 720 "setenv bootargs root=/dev/ram rw " \ 721 "console=$consoledev,$baudrate $othbootargs; " \ 722 "tftp $ramdiskaddr $ramdiskfile;" \ 723 "tftp $loadaddr $bootfile;" \ 724 "tftp $fdtaddr $fdtfile;" \ 725 "bootm $loadaddr $ramdiskaddr $fdtaddr" 726 727 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 728 729 #include <asm/fsl_secure_boot.h> 730 731 #ifdef CONFIG_SECURE_BOOT 732 #define CONFIG_CMD_BLOB 733 #endif 734 735 #endif /* __CONFIG_H */ 736