1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9132 QDS board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_BSC9132QDS 15 #define CONFIG_BSC9132 16 #endif 17 18 #define CONFIG_MISC_INIT_R 19 20 #ifdef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_SDCARD 22 #define CONFIG_SYS_RAMBOOT 23 #define CONFIG_SYS_EXTRA_ENV_RELOC 24 #define CONFIG_SYS_TEXT_BASE 0x11000000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 26 #endif 27 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 28 #ifdef CONFIG_SPIFLASH 29 #define CONFIG_RAMBOOT_SPIFLASH 30 #define CONFIG_SYS_RAMBOOT 31 #define CONFIG_SYS_EXTRA_ENV_RELOC 32 #define CONFIG_SYS_TEXT_BASE 0x11000000 33 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 34 #endif 35 #ifdef CONFIG_NAND_SECBOOT 36 #define CONFIG_RAMBOOT_NAND 37 #define CONFIG_SYS_RAMBOOT 38 #define CONFIG_SYS_EXTRA_ENV_RELOC 39 #define CONFIG_SYS_TEXT_BASE 0x11000000 40 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 41 #endif 42 43 #ifdef CONFIG_NAND 44 #define CONFIG_SPL_INIT_MINIMAL 45 #define CONFIG_SPL_NAND_BOOT 46 #define CONFIG_SPL_FLUSH_IMAGE 47 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 48 49 #define CONFIG_SYS_TEXT_BASE 0x00201000 50 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 51 #define CONFIG_SPL_MAX_SIZE 8192 52 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 53 #define CONFIG_SPL_RELOC_STACK 0x00100000 54 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 55 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 56 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 57 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 58 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 59 #endif 60 61 #ifndef CONFIG_SYS_TEXT_BASE 62 #define CONFIG_SYS_TEXT_BASE 0x8ff40000 63 #endif 64 65 #ifndef CONFIG_RESET_VECTOR_ADDRESS 66 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 67 #endif 68 69 #ifdef CONFIG_SPL_BUILD 70 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 71 #else 72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 73 #endif 74 75 /* High Level Configuration Options */ 76 #define CONFIG_BOOKE /* BOOKE */ 77 #define CONFIG_E500 /* BOOKE e500 family */ 78 #define CONFIG_FSL_IFC /* Enable IFC Support */ 79 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 80 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 81 82 #define CONFIG_PCI /* Enable PCI/PCIE */ 83 #if defined(CONFIG_PCI) 84 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 85 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 86 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 87 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 88 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 89 90 #define CONFIG_CMD_PCI 91 92 /* 93 * PCI Windows 94 * Memory space is mapped 1-1, but I/O space must start from 0. 95 */ 96 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 97 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 98 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 99 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 100 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 101 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 102 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 103 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 104 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 105 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 106 107 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 108 109 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 110 #define CONFIG_DOS_PARTITION 111 #endif 112 113 #define CONFIG_FSL_LAW /* Use common FSL init code */ 114 #define CONFIG_ENV_OVERWRITE 115 #define CONFIG_TSEC_ENET /* ethernet */ 116 117 #if defined(CONFIG_SYS_CLK_100_DDR_100) 118 #define CONFIG_SYS_CLK_FREQ 100000000 119 #define CONFIG_DDR_CLK_FREQ 100000000 120 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 121 #define CONFIG_SYS_CLK_FREQ 100000000 122 #define CONFIG_DDR_CLK_FREQ 133000000 123 #endif 124 125 #define CONFIG_MP 126 127 #define CONFIG_HWCONFIG 128 /* 129 * These can be toggled for performance analysis, otherwise use default. 130 */ 131 #define CONFIG_L2_CACHE /* toggle L2 cache */ 132 #define CONFIG_BTB /* enable branch predition */ 133 134 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 135 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 136 137 /* DDR Setup */ 138 #define CONFIG_SYS_FSL_DDR3 139 #define CONFIG_SYS_SPD_BUS_NUM 0 140 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 141 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 142 #define CONFIG_FSL_DDR_INTERACTIVE 143 144 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 145 146 #define CONFIG_SYS_SDRAM_SIZE (1024) 147 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 148 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 149 150 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 151 152 /* DDR3 Controller Settings */ 153 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 154 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 155 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 156 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 157 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 158 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 159 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 160 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 161 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 162 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 163 164 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 165 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 166 #define CONFIG_SYS_DDR_RCW_1 0x00000000 167 #define CONFIG_SYS_DDR_RCW_2 0x00000000 168 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 169 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 170 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 171 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 172 173 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 174 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 175 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 176 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 177 178 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 179 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 180 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 181 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 182 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 183 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 184 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 185 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 186 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 187 188 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 189 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 190 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 191 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 192 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 193 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 194 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 195 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 196 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 197 198 /*FIXME: the following params are constant w.r.t diff freq 199 combinations. this should be removed later 200 */ 201 #if CONFIG_DDR_CLK_FREQ == 100000000 202 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 203 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 204 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 205 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 206 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 207 #elif CONFIG_DDR_CLK_FREQ == 133000000 208 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 209 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 210 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 211 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 212 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 213 #else 214 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 215 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 216 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 217 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 218 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 219 #endif 220 221 /* relocated CCSRBAR */ 222 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 223 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 224 225 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 226 227 /* DSP CCSRBAR */ 228 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 229 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 230 231 /* 232 * IFC Definitions 233 */ 234 /* NOR Flash on IFC */ 235 236 #ifdef CONFIG_SPL_BUILD 237 #define CONFIG_SYS_NO_FLASH 238 #endif 239 #define CONFIG_SYS_FLASH_BASE 0x88000000 240 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 241 242 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 243 244 #define CONFIG_SYS_NOR_CSPR 0x88000101 245 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 246 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 247 /* NOR Flash Timing Params */ 248 249 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 250 | FTIM0_NOR_TEADC(0x03) \ 251 | FTIM0_NOR_TAVDS(0x00) \ 252 | FTIM0_NOR_TEAHC(0x0f)) 253 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 254 | FTIM1_NOR_TRAD_NOR(0x09) \ 255 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 256 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 257 | FTIM2_NOR_TCH(0x4) \ 258 | FTIM2_NOR_TWPH(0x7) \ 259 | FTIM2_NOR_TWP(0x1e)) 260 #define CONFIG_SYS_NOR_FTIM3 0x0 261 262 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 263 #define CONFIG_SYS_FLASH_QUIET_TEST 264 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 265 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 266 267 #undef CONFIG_SYS_FLASH_CHECKSUM 268 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 269 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 270 271 /* CFI for NOR Flash */ 272 #define CONFIG_FLASH_CFI_DRIVER 273 #define CONFIG_SYS_FLASH_CFI 274 #define CONFIG_SYS_FLASH_EMPTY_INFO 275 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 276 277 /* NAND Flash on IFC */ 278 #define CONFIG_SYS_NAND_BASE 0xff800000 279 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 280 281 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 282 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 283 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 284 | CSPR_V) 285 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 286 287 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 288 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 289 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 290 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 291 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 292 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 293 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 294 295 /* NAND Flash Timing Params */ 296 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 297 | FTIM0_NAND_TWP(0x05) \ 298 | FTIM0_NAND_TWCHT(0x02) \ 299 | FTIM0_NAND_TWH(0x04)) 300 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 301 | FTIM1_NAND_TWBE(0x1e) \ 302 | FTIM1_NAND_TRR(0x07) \ 303 | FTIM1_NAND_TRP(0x05)) 304 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 305 | FTIM2_NAND_TREH(0x04) \ 306 | FTIM2_NAND_TWHRE(0x11)) 307 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 308 309 #define CONFIG_SYS_NAND_DDR_LAW 11 310 311 /* NAND */ 312 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 313 #define CONFIG_SYS_MAX_NAND_DEVICE 1 314 #define CONFIG_CMD_NAND 315 316 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 317 318 #ifndef CONFIG_SPL_BUILD 319 #define CONFIG_FSL_QIXIS 320 #endif 321 #ifdef CONFIG_FSL_QIXIS 322 #define CONFIG_SYS_FPGA_BASE 0xffb00000 323 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 324 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 325 #define QIXIS_LBMAP_SWITCH 9 326 #define QIXIS_LBMAP_MASK 0x07 327 #define QIXIS_LBMAP_SHIFT 0 328 #define QIXIS_LBMAP_DFLTBANK 0x00 329 #define QIXIS_LBMAP_ALTBANK 0x04 330 #define QIXIS_RST_CTL_RESET 0x83 331 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 332 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 333 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 334 335 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 336 337 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 338 | CSPR_PORT_SIZE_8 \ 339 | CSPR_MSEL_GPCM \ 340 | CSPR_V) 341 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 342 #define CONFIG_SYS_CSOR2 0x0 343 /* CPLD Timing parameters for IFC CS3 */ 344 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 345 FTIM0_GPCM_TEADC(0x0e) | \ 346 FTIM0_GPCM_TEAHC(0x0e)) 347 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 348 FTIM1_GPCM_TRAD(0x1f)) 349 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 350 FTIM2_GPCM_TCH(0x8) | \ 351 FTIM2_GPCM_TWP(0x1f)) 352 #define CONFIG_SYS_CS2_FTIM3 0x0 353 #endif 354 355 /* Set up IFC registers for boot location NOR/NAND */ 356 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 357 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 358 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 359 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 360 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 361 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 362 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 363 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 364 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 365 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 366 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 367 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 368 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 369 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 370 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 371 #else 372 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 373 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 374 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 375 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 376 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 377 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 378 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 379 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 380 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 381 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 382 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 383 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 384 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 385 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 386 #endif 387 388 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 389 #define CONFIG_BOARD_EARLY_INIT_R 390 391 #define CONFIG_SYS_INIT_RAM_LOCK 392 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 393 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 394 395 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 396 - GENERATED_GBL_DATA_SIZE) 397 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 398 399 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 400 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 401 402 /* Serial Port */ 403 #define CONFIG_CONS_INDEX 1 404 #undef CONFIG_SERIAL_SOFTWARE_FIFO 405 #define CONFIG_SYS_NS16550_SERIAL 406 #define CONFIG_SYS_NS16550_REG_SIZE 1 407 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 408 #ifdef CONFIG_SPL_BUILD 409 #define CONFIG_NS16550_MIN_FUNCTIONS 410 #endif 411 412 #define CONFIG_SYS_BAUDRATE_TABLE \ 413 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 414 415 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 416 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 417 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 418 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 419 420 #define CONFIG_SYS_I2C 421 #define CONFIG_SYS_I2C_FSL 422 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 423 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 424 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 425 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 426 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 427 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 428 429 /* I2C EEPROM */ 430 #define CONFIG_ID_EEPROM 431 #ifdef CONFIG_ID_EEPROM 432 #define CONFIG_SYS_I2C_EEPROM_NXID 433 #endif 434 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 435 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 436 #define CONFIG_SYS_EEPROM_BUS_NUM 0 437 438 /* enable read and write access to EEPROM */ 439 #define CONFIG_CMD_EEPROM 440 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 441 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 442 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 443 444 /* I2C FPGA */ 445 #define CONFIG_I2C_FPGA 446 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 447 448 #define CONFIG_RTC_DS3231 449 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 450 451 /* 452 * SPI interface will not be available in case of NAND boot SPI CS0 will be 453 * used for SLIC 454 */ 455 /* eSPI - Enhanced SPI */ 456 #ifdef CONFIG_FSL_ESPI 457 #define CONFIG_SF_DEFAULT_SPEED 10000000 458 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 459 #endif 460 461 #if defined(CONFIG_TSEC_ENET) 462 463 #define CONFIG_MII /* MII PHY management */ 464 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 465 #define CONFIG_TSEC1 1 466 #define CONFIG_TSEC1_NAME "eTSEC1" 467 #define CONFIG_TSEC2 1 468 #define CONFIG_TSEC2_NAME "eTSEC2" 469 470 #define TSEC1_PHY_ADDR 0 471 #define TSEC2_PHY_ADDR 1 472 473 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 474 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 475 476 #define TSEC1_PHYIDX 0 477 #define TSEC2_PHYIDX 0 478 479 #define CONFIG_ETHPRIME "eTSEC1" 480 481 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 482 483 /* TBI PHY configuration for SGMII mode */ 484 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 485 TBICR_PHY_RESET \ 486 | TBICR_ANEG_ENABLE \ 487 | TBICR_FULL_DUPLEX \ 488 | TBICR_SPEED1_SET \ 489 ) 490 491 #endif /* CONFIG_TSEC_ENET */ 492 493 #define CONFIG_MMC 494 #ifdef CONFIG_MMC 495 #define CONFIG_DOS_PARTITION 496 #define CONFIG_FSL_ESDHC 497 #define CONFIG_GENERIC_MMC 498 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 499 #endif 500 501 #define CONFIG_USB_EHCI /* USB */ 502 #ifdef CONFIG_USB_EHCI 503 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 504 #define CONFIG_USB_EHCI_FSL 505 #define CONFIG_HAS_FSL_DR_USB 506 #endif 507 508 /* 509 * Environment 510 */ 511 #if defined(CONFIG_RAMBOOT_SDCARD) 512 #define CONFIG_ENV_IS_IN_MMC 513 #define CONFIG_FSL_FIXED_MMC_LOCATION 514 #define CONFIG_SYS_MMC_ENV_DEV 0 515 #define CONFIG_ENV_SIZE 0x2000 516 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 517 #define CONFIG_ENV_IS_IN_SPI_FLASH 518 #define CONFIG_ENV_SPI_BUS 0 519 #define CONFIG_ENV_SPI_CS 0 520 #define CONFIG_ENV_SPI_MAX_HZ 10000000 521 #define CONFIG_ENV_SPI_MODE 0 522 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 523 #define CONFIG_ENV_SECT_SIZE 0x10000 524 #define CONFIG_ENV_SIZE 0x2000 525 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 526 #define CONFIG_ENV_IS_IN_NAND 527 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 528 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 529 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 530 #elif defined(CONFIG_SYS_RAMBOOT) 531 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 532 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 533 #define CONFIG_ENV_SIZE 0x2000 534 #else 535 #define CONFIG_ENV_IS_IN_FLASH 536 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 537 #define CONFIG_ENV_SIZE 0x2000 538 #define CONFIG_ENV_SECT_SIZE 0x20000 539 #endif 540 541 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 542 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 543 544 /* 545 * Command line configuration. 546 */ 547 #define CONFIG_CMD_DATE 548 #define CONFIG_CMD_ERRATA 549 #define CONFIG_CMD_IRQ 550 #define CONFIG_CMD_REGINFO 551 552 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 553 #define CONFIG_DOS_PARTITION 554 #endif 555 556 /* Hash command with SHA acceleration supported in hardware */ 557 #ifdef CONFIG_FSL_CAAM 558 #define CONFIG_CMD_HASH 559 #define CONFIG_SHA_HW_ACCEL 560 #endif 561 562 /* 563 * Miscellaneous configurable options 564 */ 565 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 566 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 567 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 568 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 569 570 #if defined(CONFIG_CMD_KGDB) 571 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 572 #else 573 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 574 #endif 575 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 576 /* Print Buffer Size */ 577 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 578 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 579 580 /* 581 * For booting Linux, the board info and command line data 582 * have to be in the first 64 MB of memory, since this is 583 * the maximum mapped by the Linux kernel during initialization. 584 */ 585 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 586 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 587 588 #if defined(CONFIG_CMD_KGDB) 589 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 590 #endif 591 592 /* 593 * Dynamic MTD Partition support with mtdparts 594 */ 595 #ifndef CONFIG_SYS_NO_FLASH 596 #define CONFIG_MTD_DEVICE 597 #define CONFIG_MTD_PARTITIONS 598 #define CONFIG_CMD_MTDPARTS 599 #define CONFIG_FLASH_CFI_MTD 600 #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," 601 #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ 602 "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ 603 "8m(kernel),512k(dtb),-(fs)" 604 #endif 605 /* 606 * Environment Configuration 607 */ 608 609 #if defined(CONFIG_TSEC_ENET) 610 #define CONFIG_HAS_ETH0 611 #define CONFIG_HAS_ETH1 612 #endif 613 614 #define CONFIG_HOSTNAME BSC9132qds 615 #define CONFIG_ROOTPATH "/opt/nfsroot" 616 #define CONFIG_BOOTFILE "uImage" 617 #define CONFIG_UBOOTPATH "u-boot.bin" 618 619 #define CONFIG_BAUDRATE 115200 620 621 #ifdef CONFIG_SDCARD 622 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 623 #else 624 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 625 #endif 626 627 #define CONFIG_EXTRA_ENV_SETTINGS \ 628 "netdev=eth0\0" \ 629 "uboot=" CONFIG_UBOOTPATH "\0" \ 630 "loadaddr=1000000\0" \ 631 "bootfile=uImage\0" \ 632 "consoledev=ttyS0\0" \ 633 "ramdiskaddr=2000000\0" \ 634 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 635 "fdtaddr=1e00000\0" \ 636 "fdtfile=bsc9132qds.dtb\0" \ 637 "bdev=sda1\0" \ 638 CONFIG_DEF_HWCONFIG\ 639 "othbootargs=mem=880M ramdisk_size=600000 " \ 640 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 641 "isolcpus=0\0" \ 642 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 643 "console=$consoledev,$baudrate $othbootargs; " \ 644 "usb start;" \ 645 "ext2load usb 0:4 $loadaddr $bootfile;" \ 646 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 647 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 648 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 649 "debug_halt_off=mw ff7e0e30 0xf0000000;" 650 651 #define CONFIG_NFSBOOTCOMMAND \ 652 "setenv bootargs root=/dev/nfs rw " \ 653 "nfsroot=$serverip:$rootpath " \ 654 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 655 "console=$consoledev,$baudrate $othbootargs;" \ 656 "tftp $loadaddr $bootfile;" \ 657 "tftp $fdtaddr $fdtfile;" \ 658 "bootm $loadaddr - $fdtaddr" 659 660 #define CONFIG_HDBOOT \ 661 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 662 "console=$consoledev,$baudrate $othbootargs;" \ 663 "usb start;" \ 664 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 665 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 666 "bootm $loadaddr - $fdtaddr" 667 668 #define CONFIG_RAMBOOTCOMMAND \ 669 "setenv bootargs root=/dev/ram rw " \ 670 "console=$consoledev,$baudrate $othbootargs; " \ 671 "tftp $ramdiskaddr $ramdiskfile;" \ 672 "tftp $loadaddr $bootfile;" \ 673 "tftp $fdtaddr $fdtfile;" \ 674 "bootm $loadaddr $ramdiskaddr $fdtaddr" 675 676 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 677 678 #include <asm/fsl_secure_boot.h> 679 680 #endif /* __CONFIG_H */ 681