1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * BSC9131 RDB board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_NAND_FSL_IFC 14 15 #ifdef CONFIG_SPIFLASH 16 #define CONFIG_RAMBOOT_SPIFLASH 17 #define CONFIG_SYS_RAMBOOT 18 #define CONFIG_SYS_EXTRA_ENV_RELOC 19 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 20 #endif 21 22 #ifdef CONFIG_NAND 23 #define CONFIG_SPL_INIT_MINIMAL 24 #define CONFIG_SPL_NAND_BOOT 25 #define CONFIG_SPL_FLUSH_IMAGE 26 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 27 28 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 29 #define CONFIG_SPL_MAX_SIZE 8192 30 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 31 #define CONFIG_SPL_RELOC_STACK 0x00100000 32 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 33 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 34 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 35 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 36 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 37 #endif 38 39 #ifdef CONFIG_SPL_BUILD 40 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 41 #else 42 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 43 #endif 44 45 /* High Level Configuration Options */ 46 47 #define CONFIG_ENV_OVERWRITE 48 49 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ 50 #if defined(CONFIG_SYS_CLK_100) 51 #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */ 52 #else 53 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ 54 #endif 55 56 #define CONFIG_HWCONFIG 57 /* 58 * These can be toggled for performance analysis, otherwise use default. 59 */ 60 #define CONFIG_L2_CACHE /* toggle L2 cache */ 61 #define CONFIG_BTB /* enable branch predition */ 62 63 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 64 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 65 66 /* DDR Setup */ 67 #undef CONFIG_SYS_DDR_RAW_TIMING 68 #undef CONFIG_DDR_SPD 69 #define CONFIG_SYS_SPD_BUS_NUM 0 70 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ 71 72 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 73 74 #ifndef __ASSEMBLY__ 75 extern unsigned long get_sdram_size(void); 76 #endif 77 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 78 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 79 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 80 81 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 82 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 83 84 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 85 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 86 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 87 88 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 89 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 90 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 91 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 92 93 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 94 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 95 #define CONFIG_SYS_DDR_RCW_1 0x00000000 96 #define CONFIG_SYS_DDR_RCW_2 0x00000000 97 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 98 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 99 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 100 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 101 102 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 103 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 104 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 105 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf 106 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 107 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 108 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 109 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 110 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 111 112 /* 113 * Base addresses -- Note these are effective addresses where the 114 * actual resources get mapped (not physical addresses) 115 */ 116 /* relocated CCSRBAR */ 117 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 118 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 119 120 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ 121 /* CONFIG_SYS_IMMR */ 122 /* DSP CCSRBAR */ 123 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 124 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 125 126 /* 127 * Memory map 128 * 129 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable 130 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M 131 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M 132 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M 133 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K 134 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K 135 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K 136 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M 137 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M 138 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M 139 * 140 */ 141 142 /* 143 * IFC Definitions 144 */ 145 146 /* NAND Flash on IFC */ 147 #define CONFIG_SYS_NAND_BASE 0xff800000 148 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 149 150 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 151 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ 152 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 153 | CSPR_V) 154 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 155 156 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 157 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 158 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 159 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 160 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 161 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 162 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 163 164 /* NAND Flash Timing Params */ 165 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 166 | FTIM0_NAND_TWP(0x05) \ 167 | FTIM0_NAND_TWCHT(0x02) \ 168 | FTIM0_NAND_TWH(0x04)) 169 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ 170 | FTIM1_NAND_TWBE(0x1E) \ 171 | FTIM1_NAND_TRR(0x07) \ 172 | FTIM1_NAND_TRP(0x05)) 173 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 174 | FTIM2_NAND_TREH(0x04) \ 175 | FTIM2_NAND_TWHRE(0x11)) 176 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 177 178 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 179 #define CONFIG_SYS_MAX_NAND_DEVICE 1 180 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 181 182 #define CONFIG_SYS_NAND_DDR_LAW 11 183 184 /* Set up IFC registers for boot location NAND */ 185 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 186 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 187 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 188 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 189 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 190 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 191 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 192 193 #define CONFIG_SYS_INIT_RAM_LOCK 194 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 195 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */ 196 197 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 198 - GENERATED_GBL_DATA_SIZE) 199 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 200 201 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 202 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 203 204 /* Serial Port */ 205 #undef CONFIG_SERIAL_SOFTWARE_FIFO 206 #define CONFIG_SYS_NS16550_SERIAL 207 #define CONFIG_SYS_NS16550_REG_SIZE 1 208 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 209 #ifdef CONFIG_SPL_BUILD 210 #define CONFIG_NS16550_MIN_FUNCTIONS 211 #endif 212 213 #define CONFIG_SYS_BAUDRATE_TABLE \ 214 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 215 216 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 217 218 #define CONFIG_SYS_I2C 219 #define CONFIG_SYS_I2C_FSL 220 #define CONFIG_SYS_FSL_I2C_SPEED 400000 221 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 222 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 223 224 /* I2C EEPROM */ 225 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 226 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 227 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 228 229 /* eSPI - Enhanced SPI */ 230 #ifdef CONFIG_FSL_ESPI 231 #define CONFIG_SF_DEFAULT_SPEED 10000000 232 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 233 #endif 234 235 #if defined(CONFIG_TSEC_ENET) 236 237 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 238 #define CONFIG_TSEC1 1 239 #define CONFIG_TSEC1_NAME "eTSEC1" 240 #define CONFIG_TSEC2 1 241 #define CONFIG_TSEC2_NAME "eTSEC2" 242 243 #define TSEC1_PHY_ADDR 0 244 #define TSEC2_PHY_ADDR 3 245 246 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 247 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 248 249 #define TSEC1_PHYIDX 0 250 251 #define TSEC2_PHYIDX 0 252 253 #define CONFIG_ETHPRIME "eTSEC1" 254 255 #endif /* CONFIG_TSEC_ENET */ 256 257 /* 258 * Environment 259 */ 260 #if defined(CONFIG_RAMBOOT_SPIFLASH) 261 #define CONFIG_ENV_SPI_BUS 0 262 #define CONFIG_ENV_SPI_CS 0 263 #define CONFIG_ENV_SPI_MAX_HZ 10000000 264 #define CONFIG_ENV_SPI_MODE 0 265 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 266 #define CONFIG_ENV_SECT_SIZE 0x10000 267 #define CONFIG_ENV_SIZE 0x2000 268 #elif defined(CONFIG_NAND) 269 #define CONFIG_SYS_EXTRA_ENV_RELOC 270 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 271 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 272 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 273 #elif defined(CONFIG_SYS_RAMBOOT) 274 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 275 #define CONFIG_ENV_SIZE 0x2000 276 #endif 277 278 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 279 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 280 281 /* 282 * Miscellaneous configurable options 283 */ 284 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 285 286 #if defined(CONFIG_CMD_KGDB) 287 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 288 #else 289 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 290 #endif 291 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 292 293 /* 294 * For booting Linux, the board info and command line data 295 * have to be in the first 64 MB of memory, since this is 296 * the maximum mapped by the Linux kernel during initialization. 297 */ 298 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 299 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 300 301 #if defined(CONFIG_CMD_KGDB) 302 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 303 #endif 304 305 #ifdef CONFIG_USB_EHCI_HCD 306 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 307 #define CONFIG_USB_EHCI_FSL 308 #define CONFIG_HAS_FSL_DR_USB 309 #endif 310 311 /* 312 * Dynamic MTD Partition support with mtdparts 313 */ 314 315 /* 316 * Environment Configuration 317 */ 318 319 #if defined(CONFIG_TSEC_ENET) 320 #define CONFIG_HAS_ETH0 321 #endif 322 323 #define CONFIG_HOSTNAME "BSC9131rdb" 324 #define CONFIG_ROOTPATH "/opt/nfsroot" 325 #define CONFIG_BOOTFILE "uImage" 326 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 327 328 #define CONFIG_EXTRA_ENV_SETTINGS \ 329 "netdev=eth0\0" \ 330 "uboot=" CONFIG_UBOOTPATH "\0" \ 331 "loadaddr=1000000\0" \ 332 "bootfile=uImage\0" \ 333 "consoledev=ttyS0\0" \ 334 "ramdiskaddr=2000000\0" \ 335 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 336 "fdtaddr=1e00000\0" \ 337 "fdtfile=bsc9131rdb.dtb\0" \ 338 "bdev=sda1\0" \ 339 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 340 "bootm_size=0x37000000\0" \ 341 "othbootargs=ramdisk_size=600000 " \ 342 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \ 343 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 344 "console=$consoledev,$baudrate $othbootargs; " \ 345 "usb start;" \ 346 "ext2load usb 0:4 $loadaddr $bootfile;" \ 347 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 348 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 349 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 350 351 #define CONFIG_RAMBOOTCOMMAND \ 352 "setenv bootargs root=/dev/ram rw " \ 353 "console=$consoledev,$baudrate $othbootargs; " \ 354 "tftp $ramdiskaddr $ramdiskfile;" \ 355 "tftp $loadaddr $bootfile;" \ 356 "tftp $fdtaddr $fdtfile;" \ 357 "bootm $loadaddr $ramdiskaddr $fdtaddr" 358 359 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 360 361 #endif /* __CONFIG_H */ 362