1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9131 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_BSC9131RDB 15 #define CONFIG_BSC9131 16 #define CONFIG_NAND_FSL_IFC 17 #endif 18 19 #ifdef CONFIG_SPIFLASH 20 #define CONFIG_RAMBOOT_SPIFLASH 21 #define CONFIG_SYS_RAMBOOT 22 #define CONFIG_SYS_EXTRA_ENV_RELOC 23 #define CONFIG_SYS_TEXT_BASE 0x11000000 24 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 25 #endif 26 27 #ifdef CONFIG_NAND 28 #define CONFIG_SPL 29 #define CONFIG_SPL_INIT_MINIMAL 30 #define CONFIG_SPL_SERIAL_SUPPORT 31 #define CONFIG_SPL_NAND_SUPPORT 32 #define CONFIG_SPL_NAND_BOOT 33 #define CONFIG_SPL_FLUSH_IMAGE 34 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 35 36 #define CONFIG_SYS_TEXT_BASE 0x00201000 37 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 38 #define CONFIG_SPL_MAX_SIZE 8192 39 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 40 #define CONFIG_SPL_RELOC_STACK 0x00100000 41 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 42 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 43 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 44 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 45 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 46 #endif 47 48 #ifdef CONFIG_SPL_BUILD 49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 50 #else 51 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 52 #endif 53 54 55 /* High Level Configuration Options */ 56 #define CONFIG_BOOKE /* BOOKE */ 57 #define CONFIG_E500 /* BOOKE e500 family */ 58 #define CONFIG_FSL_IFC /* Enable IFC Support */ 59 60 #define CONFIG_FSL_LAW /* Use common FSL init code */ 61 #define CONFIG_TSEC_ENET 62 #define CONFIG_ENV_OVERWRITE 63 64 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ 65 #if defined(CONFIG_SYS_CLK_100) 66 #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */ 67 #else 68 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ 69 #endif 70 71 #define CONFIG_HWCONFIG 72 /* 73 * These can be toggled for performance analysis, otherwise use default. 74 */ 75 #define CONFIG_L2_CACHE /* toggle L2 cache */ 76 #define CONFIG_BTB /* enable branch predition */ 77 78 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 79 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 80 81 /* DDR Setup */ 82 #define CONFIG_SYS_FSL_DDR3 83 #undef CONFIG_SYS_DDR_RAW_TIMING 84 #undef CONFIG_DDR_SPD 85 #define CONFIG_SYS_SPD_BUS_NUM 0 86 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ 87 88 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 89 90 #ifndef __ASSEMBLY__ 91 extern unsigned long get_sdram_size(void); 92 #endif 93 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 94 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 95 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 96 97 #define CONFIG_NUM_DDR_CONTROLLERS 1 98 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 99 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 100 101 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 102 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 103 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 104 105 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 106 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 107 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 108 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 109 110 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 111 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 112 #define CONFIG_SYS_DDR_RCW_1 0x00000000 113 #define CONFIG_SYS_DDR_RCW_2 0x00000000 114 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 115 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 116 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 117 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 118 119 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 120 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 121 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 122 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf 123 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 124 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 125 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 126 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 127 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 128 129 /* 130 * Base addresses -- Note these are effective addresses where the 131 * actual resources get mapped (not physical addresses) 132 */ 133 /* relocated CCSRBAR */ 134 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 135 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 136 137 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ 138 /* CONFIG_SYS_IMMR */ 139 /* DSP CCSRBAR */ 140 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 141 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 142 143 /* 144 * Memory map 145 * 146 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable 147 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M 148 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M 149 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M 150 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K 151 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K 152 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K 153 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M 154 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M 155 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M 156 * 157 */ 158 159 /* 160 * IFC Definitions 161 */ 162 #define CONFIG_SYS_NO_FLASH 163 164 /* NAND Flash on IFC */ 165 #define CONFIG_SYS_NAND_BASE 0xff800000 166 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 167 168 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 169 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ 170 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 171 | CSPR_V) 172 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 173 174 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 175 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 176 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 177 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 178 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 179 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 180 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 181 182 /* NAND Flash Timing Params */ 183 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 184 | FTIM0_NAND_TWP(0x05) \ 185 | FTIM0_NAND_TWCHT(0x02) \ 186 | FTIM0_NAND_TWH(0x04)) 187 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ 188 | FTIM1_NAND_TWBE(0x1E) \ 189 | FTIM1_NAND_TRR(0x07) \ 190 | FTIM1_NAND_TRP(0x05)) 191 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 192 | FTIM2_NAND_TREH(0x04) \ 193 | FTIM2_NAND_TWHRE(0x11)) 194 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 195 196 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 197 #define CONFIG_SYS_MAX_NAND_DEVICE 1 198 #define CONFIG_MTD_NAND_VERIFY_WRITE 199 #define CONFIG_CMD_NAND 200 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 201 202 #define CONFIG_SYS_NAND_DDR_LAW 11 203 204 /* Set up IFC registers for boot location NAND */ 205 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 206 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 207 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 208 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 209 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 210 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 211 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 212 213 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 214 215 #define CONFIG_SYS_INIT_RAM_LOCK 216 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 217 #define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */ 218 219 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 220 - GENERATED_GBL_DATA_SIZE) 221 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 222 223 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 224 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 225 226 /* Serial Port */ 227 #define CONFIG_CONS_INDEX 1 228 #undef CONFIG_SERIAL_SOFTWARE_FIFO 229 #define CONFIG_SYS_NS16550 230 #define CONFIG_SYS_NS16550_SERIAL 231 #define CONFIG_SYS_NS16550_REG_SIZE 1 232 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 233 #ifdef CONFIG_SPL_BUILD 234 #define CONFIG_NS16550_MIN_FUNCTIONS 235 #endif 236 237 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 238 239 #define CONFIG_SYS_BAUDRATE_TABLE \ 240 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 241 242 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 243 244 /* Use the HUSH parser */ 245 #define CONFIG_SYS_HUSH_PARSER 246 #ifdef CONFIG_SYS_HUSH_PARSER 247 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 248 #endif 249 250 /* 251 * Pass open firmware flat tree 252 */ 253 #define CONFIG_OF_LIBFDT 254 #define CONFIG_OF_BOARD_SETUP 255 #define CONFIG_OF_STDOUT_VIA_ALIAS 256 257 /* new uImage format support */ 258 #define CONFIG_FIT 259 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 260 261 #define CONFIG_SYS_I2C 262 #define CONFIG_SYS_I2C_FSL 263 #define CONFIG_SYS_FSL_I2C_SPEED 400000 264 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 265 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 266 267 /* I2C EEPROM */ 268 #define CONFIG_CMD_EEPROM 269 #define CONFIG_SYS_I2C_MULTI_EEPROMS 270 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 271 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 272 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 273 274 #define CONFIG_CMD_I2C 275 276 277 #define CONFIG_FSL_ESPI 278 /* eSPI - Enhanced SPI */ 279 #ifdef CONFIG_FSL_ESPI 280 #define CONFIG_SPI_FLASH 281 #define CONFIG_SPI_FLASH_SPANSION 282 #define CONFIG_CMD_SF 283 #define CONFIG_SF_DEFAULT_SPEED 10000000 284 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 285 #endif 286 287 #if defined(CONFIG_TSEC_ENET) 288 289 #define CONFIG_MII /* MII PHY management */ 290 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 291 #define CONFIG_TSEC1 1 292 #define CONFIG_TSEC1_NAME "eTSEC1" 293 #define CONFIG_TSEC2 1 294 #define CONFIG_TSEC2_NAME "eTSEC2" 295 296 #define TSEC1_PHY_ADDR 0 297 #define TSEC2_PHY_ADDR 3 298 299 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 300 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 301 302 #define TSEC1_PHYIDX 0 303 304 #define TSEC2_PHYIDX 0 305 306 #define CONFIG_ETHPRIME "eTSEC1" 307 308 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 309 310 #endif /* CONFIG_TSEC_ENET */ 311 312 /* 313 * Environment 314 */ 315 #if defined(CONFIG_RAMBOOT_SPIFLASH) 316 #define CONFIG_ENV_IS_IN_SPI_FLASH 317 #define CONFIG_ENV_SPI_BUS 0 318 #define CONFIG_ENV_SPI_CS 0 319 #define CONFIG_ENV_SPI_MAX_HZ 10000000 320 #define CONFIG_ENV_SPI_MODE 0 321 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 322 #define CONFIG_ENV_SECT_SIZE 0x10000 323 #define CONFIG_ENV_SIZE 0x2000 324 #elif defined(CONFIG_NAND) 325 #define CONFIG_ENV_IS_IN_NAND 326 #define CONFIG_SYS_EXTRA_ENV_RELOC 327 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 328 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 329 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 330 #elif defined(CONFIG_SYS_RAMBOOT) 331 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 332 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 333 #define CONFIG_ENV_SIZE 0x2000 334 #endif 335 336 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 337 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 338 339 /* 340 * Command line configuration. 341 */ 342 #include <config_cmd_default.h> 343 344 #define CONFIG_CMD_DHCP 345 #define CONFIG_CMD_ERRATA 346 #define CONFIG_CMD_ELF 347 #define CONFIG_CMD_EXT2 348 #define CONFIG_CMD_FAT 349 #define CONFIG_CMD_IRQ 350 #define CONFIG_CMD_MII 351 #define CONFIG_DOS_PARTITION 352 #define CONFIG_CMD_PING 353 #define CONFIG_CMD_REGINFO 354 #define CONFIG_CMD_SETEXPR 355 356 /* 357 * Miscellaneous configurable options 358 */ 359 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 360 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 361 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 362 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 363 364 #if defined(CONFIG_CMD_KGDB) 365 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 366 #else 367 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 368 #endif 369 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 370 /* Print Buffer Size */ 371 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 372 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 373 374 /* 375 * For booting Linux, the board info and command line data 376 * have to be in the first 64 MB of memory, since this is 377 * the maximum mapped by the Linux kernel during initialization. 378 */ 379 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 380 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 381 382 #if defined(CONFIG_CMD_KGDB) 383 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 384 #endif 385 386 #define CONFIG_USB_EHCI 387 388 #ifdef CONFIG_USB_EHCI 389 #define CONFIG_CMD_USB 390 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 391 #define CONFIG_USB_EHCI_FSL 392 #define CONFIG_USB_STORAGE 393 #define CONFIG_HAS_FSL_DR_USB 394 #endif 395 396 /* 397 * Environment Configuration 398 */ 399 400 #if defined(CONFIG_TSEC_ENET) 401 #define CONFIG_HAS_ETH0 402 #endif 403 404 #define CONFIG_HOSTNAME BSC9131rdb 405 #define CONFIG_ROOTPATH "/opt/nfsroot" 406 #define CONFIG_BOOTFILE "uImage" 407 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 408 409 #define CONFIG_BAUDRATE 115200 410 411 #define CONFIG_EXTRA_ENV_SETTINGS \ 412 "netdev=eth0\0" \ 413 "uboot=" CONFIG_UBOOTPATH "\0" \ 414 "loadaddr=1000000\0" \ 415 "bootfile=uImage\0" \ 416 "consoledev=ttyS0\0" \ 417 "ramdiskaddr=2000000\0" \ 418 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 419 "fdtaddr=c00000\0" \ 420 "fdtfile=bsc9131rdb.dtb\0" \ 421 "bdev=sda1\0" \ 422 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 423 "bootm_size=0x37000000\0" \ 424 "othbootargs=ramdisk_size=600000 " \ 425 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \ 426 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 427 "console=$consoledev,$baudrate $othbootargs; " \ 428 "usb start;" \ 429 "ext2load usb 0:4 $loadaddr $bootfile;" \ 430 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 431 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 432 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 433 434 #define CONFIG_RAMBOOTCOMMAND \ 435 "setenv bootargs root=/dev/ram rw " \ 436 "console=$consoledev,$baudrate $othbootargs; " \ 437 "tftp $ramdiskaddr $ramdiskfile;" \ 438 "tftp $loadaddr $bootfile;" \ 439 "tftp $fdtaddr $fdtfile;" \ 440 "bootm $loadaddr $ramdiskaddr $fdtaddr" 441 442 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 443 444 #endif /* __CONFIG_H */ 445