xref: /openbmc/u-boot/include/configs/BSC9131RDB.h (revision aa5e3e22)
1 /*
2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 /*
8  * BSC9131 RDB board configuration file
9  */
10 
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 #define CONFIG_NAND_FSL_IFC
15 
16 #ifdef CONFIG_SPIFLASH
17 #define CONFIG_RAMBOOT_SPIFLASH
18 #define CONFIG_SYS_RAMBOOT
19 #define CONFIG_SYS_EXTRA_ENV_RELOC
20 #define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
21 #endif
22 
23 #ifdef CONFIG_NAND
24 #define CONFIG_SPL_INIT_MINIMAL
25 #define CONFIG_SPL_NAND_BOOT
26 #define CONFIG_SPL_FLUSH_IMAGE
27 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
28 
29 #define CONFIG_SPL_TEXT_BASE		0xFFFFE000
30 #define CONFIG_SPL_MAX_SIZE		8192
31 #define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
32 #define CONFIG_SPL_RELOC_STACK		0x00100000
33 #define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
34 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
35 #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
36 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0
37 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
38 #endif
39 
40 #ifdef CONFIG_SPL_BUILD
41 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
42 #else
43 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
44 #endif
45 
46 /* High Level Configuration Options */
47 
48 #define CONFIG_TSEC_ENET
49 #define CONFIG_ENV_OVERWRITE
50 
51 #define CONFIG_DDR_CLK_FREQ	66666666 /* DDRCLK on 9131 RDB */
52 #if defined(CONFIG_SYS_CLK_100)
53 #define CONFIG_SYS_CLK_FREQ    100000000 /* SYSCLK for 9131 RDB */
54 #else
55 #define CONFIG_SYS_CLK_FREQ	66666666 /* SYSCLK for 9131 RDB */
56 #endif
57 
58 #define CONFIG_HWCONFIG
59 /*
60  * These can be toggled for performance analysis, otherwise use default.
61  */
62 #define CONFIG_L2_CACHE			/* toggle L2 cache */
63 #define CONFIG_BTB			/* enable branch predition */
64 
65 #define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
66 #define CONFIG_SYS_MEMTEST_END		0x01ffffff
67 
68 /* DDR Setup */
69 #undef CONFIG_SYS_DDR_RAW_TIMING
70 #undef CONFIG_DDR_SPD
71 #define CONFIG_SYS_SPD_BUS_NUM		0
72 #define SPD_EEPROM_ADDRESS		0x52 /* I2C access */
73 
74 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
75 
76 #ifndef __ASSEMBLY__
77 extern unsigned long get_sdram_size(void);
78 #endif
79 #define CONFIG_SYS_SDRAM_SIZE		get_sdram_size() /* DDR size */
80 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
81 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
82 
83 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
84 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
85 
86 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
87 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
88 #define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
89 
90 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
91 #define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
92 #define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
93 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
94 
95 #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
96 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
97 #define CONFIG_SYS_DDR_RCW_1		0x00000000
98 #define CONFIG_SYS_DDR_RCW_2		0x00000000
99 #define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
100 #define CONFIG_SYS_DDR_CONTROL_2	0x24401000
101 #define CONFIG_SYS_DDR_TIMING_4		0x00000001
102 #define CONFIG_SYS_DDR_TIMING_5		0x02401400
103 
104 #define CONFIG_SYS_DDR_TIMING_3_800		0x00030000
105 #define CONFIG_SYS_DDR_TIMING_0_800		0x00110104
106 #define CONFIG_SYS_DDR_TIMING_1_800		0x6f6b8644
107 #define CONFIG_SYS_DDR_TIMING_2_800		0x0fa888cf
108 #define CONFIG_SYS_DDR_CLK_CTRL_800		0x03000000
109 #define CONFIG_SYS_DDR_MODE_1_800		0x00441420
110 #define CONFIG_SYS_DDR_MODE_2_800		0x8000c000
111 #define CONFIG_SYS_DDR_INTERVAL_800		0x0c300100
112 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800	0x8675f608
113 
114 /*
115  * Base addresses -- Note these are effective addresses where the
116  * actual resources get mapped (not physical addresses)
117  */
118 /* relocated CCSRBAR */
119 #define CONFIG_SYS_CCSRBAR	CONFIG_SYS_CCSRBAR_DEFAULT
120 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR_DEFAULT
121 
122 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses */
123 							/* CONFIG_SYS_IMMR */
124 /* DSP CCSRBAR */
125 #define CONFIG_SYS_FSL_DSP_CCSRBAR	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
126 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
127 
128 /*
129  * Memory map
130  *
131  * 0x0000_0000	0x3FFF_FFFF	DDR			1G cacheable
132  * 0x8800_0000	0x8810_0000	IFC internal SRAM		1M
133  * 0xB000_0000	0xB0FF_FFFF	DSP core M2 memory	16M
134  * 0xC100_0000	0xC13F_FFFF	MAPLE-2F		4M
135  * 0xC1F0_0000	0xC1F3_FFFF	PA L2 SRAM Region 0	256K
136  * 0xC1F8_0000	0xC1F9_FFFF	PA L2 SRAM Region 1	128K
137  * 0xFED0_0000	0xFED0_3FFF	SEC Secured RAM		16K
138  * 0xFF60_0000	0xFF6F_FFFF	DSP CCSR		1M
139  * 0xFF70_0000	0xFF7F_FFFF	PA CCSR			1M
140  * 0xFF80_0000	0xFFFF_FFFF	Boot Page & NAND flash buffer	8M
141  *
142  */
143 
144 /*
145  * IFC Definitions
146  */
147 
148 /* NAND Flash on IFC */
149 #define CONFIG_SYS_NAND_BASE		0xff800000
150 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
151 
152 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
153 				| CSPR_PORT_SIZE_8	/* Port Size = 8 bit*/ \
154 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
155 				| CSPR_V)
156 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
157 
158 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
159 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
160 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
161 				| CSOR_NAND_RAL_2	/* RAL = 2Byes */ \
162 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
163 				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
164 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
165 
166 /* NAND Flash Timing Params */
167 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x03)  \
168 					| FTIM0_NAND_TWP(0x05)   \
169 					| FTIM0_NAND_TWCHT(0x02) \
170 					| FTIM0_NAND_TWH(0x04))
171 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1C) \
172 					| FTIM1_NAND_TWBE(0x1E) \
173 					| FTIM1_NAND_TRR(0x07)  \
174 					| FTIM1_NAND_TRP(0x05))
175 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x08)  \
176 					| FTIM2_NAND_TREH(0x04) \
177 					| FTIM2_NAND_TWHRE(0x11))
178 #define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
179 
180 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
181 #define CONFIG_SYS_MAX_NAND_DEVICE	1
182 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
183 
184 #define CONFIG_SYS_NAND_DDR_LAW		11
185 
186 /* Set up IFC registers for boot location NAND */
187 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
188 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
189 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
190 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
191 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
192 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
193 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
194 
195 #define CONFIG_SYS_INIT_RAM_LOCK
196 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* stack in RAM */
197 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000/* End of used area in RAM */
198 
199 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
200 						- GENERATED_GBL_DATA_SIZE)
201 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
202 
203 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
204 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
205 
206 /* Serial Port */
207 #define CONFIG_CONS_INDEX	1
208 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
209 #define CONFIG_SYS_NS16550_SERIAL
210 #define CONFIG_SYS_NS16550_REG_SIZE	1
211 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
212 #ifdef CONFIG_SPL_BUILD
213 #define CONFIG_NS16550_MIN_FUNCTIONS
214 #endif
215 
216 #define CONFIG_SYS_BAUDRATE_TABLE	\
217 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
218 
219 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
220 
221 #define CONFIG_SYS_I2C
222 #define CONFIG_SYS_I2C_FSL
223 #define CONFIG_SYS_FSL_I2C_SPEED	400000
224 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
225 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
226 
227 /* I2C EEPROM */
228 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
231 
232 /* eSPI - Enhanced SPI */
233 #ifdef CONFIG_FSL_ESPI
234 #define CONFIG_SF_DEFAULT_SPEED		10000000
235 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
236 #endif
237 
238 #if defined(CONFIG_TSEC_ENET)
239 
240 #define CONFIG_MII			/* MII PHY management */
241 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
242 #define CONFIG_TSEC1	1
243 #define CONFIG_TSEC1_NAME	"eTSEC1"
244 #define CONFIG_TSEC2	1
245 #define CONFIG_TSEC2_NAME	"eTSEC2"
246 
247 #define TSEC1_PHY_ADDR		0
248 #define TSEC2_PHY_ADDR		3
249 
250 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
251 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
252 
253 #define TSEC1_PHYIDX		0
254 
255 #define TSEC2_PHYIDX		0
256 
257 #define CONFIG_ETHPRIME		"eTSEC1"
258 
259 #endif	/* CONFIG_TSEC_ENET */
260 
261 /*
262  * Environment
263  */
264 #if defined(CONFIG_RAMBOOT_SPIFLASH)
265 #define CONFIG_ENV_SPI_BUS	0
266 #define CONFIG_ENV_SPI_CS	0
267 #define CONFIG_ENV_SPI_MAX_HZ	10000000
268 #define CONFIG_ENV_SPI_MODE	0
269 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
270 #define CONFIG_ENV_SECT_SIZE	0x10000
271 #define CONFIG_ENV_SIZE		0x2000
272 #elif defined(CONFIG_NAND)
273 #define CONFIG_SYS_EXTRA_ENV_RELOC
274 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
275 #define CONFIG_ENV_OFFSET	((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
276 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
277 #elif defined(CONFIG_SYS_RAMBOOT)
278 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
279 #define CONFIG_ENV_SIZE		0x2000
280 #endif
281 
282 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
283 #define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate change */
284 
285 /*
286  * Miscellaneous configurable options
287  */
288 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
289 
290 #if defined(CONFIG_CMD_KGDB)
291 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
292 #else
293 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
294 #endif
295 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
296 
297 /*
298  * For booting Linux, the board info and command line data
299  * have to be in the first 64 MB of memory, since this is
300  * the maximum mapped by the Linux kernel during initialization.
301  */
302 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
303 #define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
304 
305 #if defined(CONFIG_CMD_KGDB)
306 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
307 #endif
308 
309 #ifdef CONFIG_USB_EHCI_HCD
310 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
311 #define CONFIG_USB_EHCI_FSL
312 #define CONFIG_HAS_FSL_DR_USB
313 #endif
314 
315 /*
316  * Dynamic MTD Partition support with mtdparts
317  */
318 #define CONFIG_MTD_DEVICE
319 #define CONFIG_MTD_PARTITIONS
320 
321 /*
322  * Environment Configuration
323  */
324 
325 #if defined(CONFIG_TSEC_ENET)
326 #define CONFIG_HAS_ETH0
327 #endif
328 
329 #define CONFIG_HOSTNAME		BSC9131rdb
330 #define CONFIG_ROOTPATH		"/opt/nfsroot"
331 #define CONFIG_BOOTFILE		"uImage"
332 #define CONFIG_UBOOTPATH	"u-boot.bin" /* U-Boot image on TFTP server */
333 
334 #define	CONFIG_EXTRA_ENV_SETTINGS				\
335 	"netdev=eth0\0"						\
336 	"uboot=" CONFIG_UBOOTPATH "\0"				\
337 	"loadaddr=1000000\0"			\
338 	"bootfile=uImage\0"	\
339 	"consoledev=ttyS0\0"				\
340 	"ramdiskaddr=2000000\0"			\
341 	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
342 	"fdtaddr=1e00000\0"				\
343 	"fdtfile=bsc9131rdb.dtb\0"		\
344 	"bdev=sda1\0"	\
345 	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"	\
346 	"bootm_size=0x37000000\0"	\
347 	"othbootargs=ramdisk_size=600000 " \
348 	"default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
349 	"usbext2boot=setenv bootargs root=/dev/ram rw "	\
350 	"console=$consoledev,$baudrate $othbootargs; "	\
351 	"usb start;"			\
352 	"ext2load usb 0:4 $loadaddr $bootfile;"		\
353 	"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
354 	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
355 	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"	\
356 
357 #define CONFIG_RAMBOOTCOMMAND		\
358 	"setenv bootargs root=/dev/ram rw "	\
359 	"console=$consoledev,$baudrate $othbootargs; "	\
360 	"tftp $ramdiskaddr $ramdiskfile;"	\
361 	"tftp $loadaddr $bootfile;"		\
362 	"tftp $fdtaddr $fdtfile;"		\
363 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
364 
365 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
366 
367 #endif	/* __CONFIG_H */
368