1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * BSC9131 RDB board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_NAND_FSL_IFC 14 15 #ifdef CONFIG_SPIFLASH 16 #define CONFIG_RAMBOOT_SPIFLASH 17 #define CONFIG_SYS_RAMBOOT 18 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 19 #endif 20 21 #ifdef CONFIG_NAND 22 #define CONFIG_SPL_INIT_MINIMAL 23 #define CONFIG_SPL_NAND_BOOT 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 27 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 28 #define CONFIG_SPL_MAX_SIZE 8192 29 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 30 #define CONFIG_SPL_RELOC_STACK 0x00100000 31 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 32 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 33 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 34 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 35 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 36 #endif 37 38 #ifdef CONFIG_SPL_BUILD 39 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 40 #else 41 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 42 #endif 43 44 /* High Level Configuration Options */ 45 46 #define CONFIG_ENV_OVERWRITE 47 48 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ 49 #if defined(CONFIG_SYS_CLK_100) 50 #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */ 51 #else 52 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ 53 #endif 54 55 #define CONFIG_HWCONFIG 56 /* 57 * These can be toggled for performance analysis, otherwise use default. 58 */ 59 #define CONFIG_L2_CACHE /* toggle L2 cache */ 60 #define CONFIG_BTB /* enable branch predition */ 61 62 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 63 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 64 65 /* DDR Setup */ 66 #undef CONFIG_SYS_DDR_RAW_TIMING 67 #undef CONFIG_DDR_SPD 68 #define CONFIG_SYS_SPD_BUS_NUM 0 69 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ 70 71 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 72 73 #ifndef __ASSEMBLY__ 74 extern unsigned long get_sdram_size(void); 75 #endif 76 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 77 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 78 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 79 80 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 81 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 82 83 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 84 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 85 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 86 87 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 88 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 89 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 90 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 91 92 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 93 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 94 #define CONFIG_SYS_DDR_RCW_1 0x00000000 95 #define CONFIG_SYS_DDR_RCW_2 0x00000000 96 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 97 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 98 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 99 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 100 101 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 102 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 103 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 104 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf 105 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 106 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 107 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 108 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 109 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 110 111 /* 112 * Base addresses -- Note these are effective addresses where the 113 * actual resources get mapped (not physical addresses) 114 */ 115 /* relocated CCSRBAR */ 116 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 117 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 118 119 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ 120 /* CONFIG_SYS_IMMR */ 121 /* DSP CCSRBAR */ 122 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 123 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 124 125 /* 126 * Memory map 127 * 128 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable 129 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M 130 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M 131 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M 132 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K 133 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K 134 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K 135 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M 136 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M 137 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M 138 * 139 */ 140 141 /* 142 * IFC Definitions 143 */ 144 145 /* NAND Flash on IFC */ 146 #define CONFIG_SYS_NAND_BASE 0xff800000 147 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 148 149 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 150 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ 151 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 152 | CSPR_V) 153 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 154 155 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 156 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 157 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 158 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 159 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 160 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 161 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 162 163 /* NAND Flash Timing Params */ 164 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 165 | FTIM0_NAND_TWP(0x05) \ 166 | FTIM0_NAND_TWCHT(0x02) \ 167 | FTIM0_NAND_TWH(0x04)) 168 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ 169 | FTIM1_NAND_TWBE(0x1E) \ 170 | FTIM1_NAND_TRR(0x07) \ 171 | FTIM1_NAND_TRP(0x05)) 172 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 173 | FTIM2_NAND_TREH(0x04) \ 174 | FTIM2_NAND_TWHRE(0x11)) 175 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 176 177 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 178 #define CONFIG_SYS_MAX_NAND_DEVICE 1 179 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 180 181 #define CONFIG_SYS_NAND_DDR_LAW 11 182 183 /* Set up IFC registers for boot location NAND */ 184 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 185 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 186 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 187 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 188 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 189 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 190 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 191 192 #define CONFIG_SYS_INIT_RAM_LOCK 193 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 194 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */ 195 196 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 197 - GENERATED_GBL_DATA_SIZE) 198 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 199 200 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 201 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 202 203 /* Serial Port */ 204 #undef CONFIG_SERIAL_SOFTWARE_FIFO 205 #define CONFIG_SYS_NS16550_SERIAL 206 #define CONFIG_SYS_NS16550_REG_SIZE 1 207 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 208 #ifdef CONFIG_SPL_BUILD 209 #define CONFIG_NS16550_MIN_FUNCTIONS 210 #endif 211 212 #define CONFIG_SYS_BAUDRATE_TABLE \ 213 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 214 215 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 216 217 #define CONFIG_SYS_I2C 218 #define CONFIG_SYS_I2C_FSL 219 #define CONFIG_SYS_FSL_I2C_SPEED 400000 220 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 221 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 222 223 /* I2C EEPROM */ 224 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 225 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 226 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 227 228 /* eSPI - Enhanced SPI */ 229 #ifdef CONFIG_FSL_ESPI 230 #define CONFIG_SF_DEFAULT_SPEED 10000000 231 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 232 #endif 233 234 #if defined(CONFIG_TSEC_ENET) 235 236 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 237 #define CONFIG_TSEC1 1 238 #define CONFIG_TSEC1_NAME "eTSEC1" 239 #define CONFIG_TSEC2 1 240 #define CONFIG_TSEC2_NAME "eTSEC2" 241 242 #define TSEC1_PHY_ADDR 0 243 #define TSEC2_PHY_ADDR 3 244 245 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 246 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 247 248 #define TSEC1_PHYIDX 0 249 250 #define TSEC2_PHYIDX 0 251 252 #define CONFIG_ETHPRIME "eTSEC1" 253 254 #endif /* CONFIG_TSEC_ENET */ 255 256 /* 257 * Environment 258 */ 259 #if defined(CONFIG_RAMBOOT_SPIFLASH) 260 #define CONFIG_ENV_SPI_BUS 0 261 #define CONFIG_ENV_SPI_CS 0 262 #define CONFIG_ENV_SPI_MAX_HZ 10000000 263 #define CONFIG_ENV_SPI_MODE 0 264 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 265 #define CONFIG_ENV_SECT_SIZE 0x10000 266 #define CONFIG_ENV_SIZE 0x2000 267 #elif defined(CONFIG_NAND) 268 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 269 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 270 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 271 #elif defined(CONFIG_SYS_RAMBOOT) 272 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 273 #define CONFIG_ENV_SIZE 0x2000 274 #endif 275 276 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 277 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 278 279 /* 280 * Miscellaneous configurable options 281 */ 282 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 283 284 #if defined(CONFIG_CMD_KGDB) 285 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 286 #else 287 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 288 #endif 289 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 290 291 /* 292 * For booting Linux, the board info and command line data 293 * have to be in the first 64 MB of memory, since this is 294 * the maximum mapped by the Linux kernel during initialization. 295 */ 296 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 297 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 298 299 #if defined(CONFIG_CMD_KGDB) 300 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 301 #endif 302 303 #ifdef CONFIG_USB_EHCI_HCD 304 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 305 #define CONFIG_USB_EHCI_FSL 306 #define CONFIG_HAS_FSL_DR_USB 307 #endif 308 309 /* 310 * Dynamic MTD Partition support with mtdparts 311 */ 312 313 /* 314 * Environment Configuration 315 */ 316 317 #if defined(CONFIG_TSEC_ENET) 318 #define CONFIG_HAS_ETH0 319 #endif 320 321 #define CONFIG_HOSTNAME "BSC9131rdb" 322 #define CONFIG_ROOTPATH "/opt/nfsroot" 323 #define CONFIG_BOOTFILE "uImage" 324 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 325 326 #define CONFIG_EXTRA_ENV_SETTINGS \ 327 "netdev=eth0\0" \ 328 "uboot=" CONFIG_UBOOTPATH "\0" \ 329 "loadaddr=1000000\0" \ 330 "bootfile=uImage\0" \ 331 "consoledev=ttyS0\0" \ 332 "ramdiskaddr=2000000\0" \ 333 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 334 "fdtaddr=1e00000\0" \ 335 "fdtfile=bsc9131rdb.dtb\0" \ 336 "bdev=sda1\0" \ 337 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 338 "bootm_size=0x37000000\0" \ 339 "othbootargs=ramdisk_size=600000 " \ 340 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \ 341 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 342 "console=$consoledev,$baudrate $othbootargs; " \ 343 "usb start;" \ 344 "ext2load usb 0:4 $loadaddr $bootfile;" \ 345 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 346 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 347 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 348 349 #define CONFIG_RAMBOOTCOMMAND \ 350 "setenv bootargs root=/dev/ram rw " \ 351 "console=$consoledev,$baudrate $othbootargs; " \ 352 "tftp $ramdiskaddr $ramdiskfile;" \ 353 "tftp $loadaddr $bootfile;" \ 354 "tftp $fdtaddr $fdtfile;" \ 355 "bootm $loadaddr $ramdiskaddr $fdtaddr" 356 357 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 358 359 #endif /* __CONFIG_H */ 360