1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9131 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_NAND_FSL_IFC 15 16 #ifdef CONFIG_SPIFLASH 17 #define CONFIG_RAMBOOT_SPIFLASH 18 #define CONFIG_SYS_RAMBOOT 19 #define CONFIG_SYS_EXTRA_ENV_RELOC 20 #define CONFIG_SYS_TEXT_BASE 0x11000000 21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 22 #endif 23 24 #ifdef CONFIG_NAND 25 #define CONFIG_SPL_INIT_MINIMAL 26 #define CONFIG_SPL_NAND_BOOT 27 #define CONFIG_SPL_FLUSH_IMAGE 28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 29 30 #define CONFIG_SYS_TEXT_BASE 0x00201000 31 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 32 #define CONFIG_SPL_MAX_SIZE 8192 33 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 34 #define CONFIG_SPL_RELOC_STACK 0x00100000 35 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 36 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 37 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 38 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 39 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 40 #endif 41 42 #ifdef CONFIG_SPL_BUILD 43 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 44 #else 45 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 46 #endif 47 48 /* High Level Configuration Options */ 49 #define CONFIG_BOOKE /* BOOKE */ 50 #define CONFIG_E500 /* BOOKE e500 family */ 51 #define CONFIG_FSL_IFC /* Enable IFC Support */ 52 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 53 54 #define CONFIG_TSEC_ENET 55 #define CONFIG_ENV_OVERWRITE 56 57 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ 58 #if defined(CONFIG_SYS_CLK_100) 59 #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */ 60 #else 61 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ 62 #endif 63 64 #define CONFIG_HWCONFIG 65 /* 66 * These can be toggled for performance analysis, otherwise use default. 67 */ 68 #define CONFIG_L2_CACHE /* toggle L2 cache */ 69 #define CONFIG_BTB /* enable branch predition */ 70 71 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 72 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 73 74 /* DDR Setup */ 75 #define CONFIG_SYS_FSL_DDR3 76 #undef CONFIG_SYS_DDR_RAW_TIMING 77 #undef CONFIG_DDR_SPD 78 #define CONFIG_SYS_SPD_BUS_NUM 0 79 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ 80 81 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 82 83 #ifndef __ASSEMBLY__ 84 extern unsigned long get_sdram_size(void); 85 #endif 86 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 87 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 88 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 89 90 #define CONFIG_NUM_DDR_CONTROLLERS 1 91 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 92 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 93 94 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 95 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 96 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 97 98 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 99 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 100 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 101 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 102 103 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 104 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 105 #define CONFIG_SYS_DDR_RCW_1 0x00000000 106 #define CONFIG_SYS_DDR_RCW_2 0x00000000 107 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 108 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 109 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 110 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 111 112 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 113 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 114 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 115 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf 116 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 117 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 118 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 119 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 120 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 121 122 /* 123 * Base addresses -- Note these are effective addresses where the 124 * actual resources get mapped (not physical addresses) 125 */ 126 /* relocated CCSRBAR */ 127 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 128 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 129 130 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ 131 /* CONFIG_SYS_IMMR */ 132 /* DSP CCSRBAR */ 133 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 134 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 135 136 /* 137 * Memory map 138 * 139 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable 140 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M 141 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M 142 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M 143 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K 144 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K 145 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K 146 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M 147 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M 148 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M 149 * 150 */ 151 152 /* 153 * IFC Definitions 154 */ 155 #define CONFIG_SYS_NO_FLASH 156 157 /* NAND Flash on IFC */ 158 #define CONFIG_SYS_NAND_BASE 0xff800000 159 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 160 161 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 162 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ 163 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 164 | CSPR_V) 165 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 166 167 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 168 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 169 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 170 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 171 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 172 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 173 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 174 175 /* NAND Flash Timing Params */ 176 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 177 | FTIM0_NAND_TWP(0x05) \ 178 | FTIM0_NAND_TWCHT(0x02) \ 179 | FTIM0_NAND_TWH(0x04)) 180 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ 181 | FTIM1_NAND_TWBE(0x1E) \ 182 | FTIM1_NAND_TRR(0x07) \ 183 | FTIM1_NAND_TRP(0x05)) 184 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 185 | FTIM2_NAND_TREH(0x04) \ 186 | FTIM2_NAND_TWHRE(0x11)) 187 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 188 189 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 190 #define CONFIG_SYS_MAX_NAND_DEVICE 1 191 #define CONFIG_CMD_NAND 192 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 193 194 #define CONFIG_SYS_NAND_DDR_LAW 11 195 196 /* Set up IFC registers for boot location NAND */ 197 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 198 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 199 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 200 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 201 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 202 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 203 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 204 205 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 206 207 #define CONFIG_SYS_INIT_RAM_LOCK 208 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 209 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */ 210 211 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 212 - GENERATED_GBL_DATA_SIZE) 213 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 214 215 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 216 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 217 218 /* Serial Port */ 219 #define CONFIG_CONS_INDEX 1 220 #undef CONFIG_SERIAL_SOFTWARE_FIFO 221 #define CONFIG_SYS_NS16550_SERIAL 222 #define CONFIG_SYS_NS16550_REG_SIZE 1 223 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 224 #ifdef CONFIG_SPL_BUILD 225 #define CONFIG_NS16550_MIN_FUNCTIONS 226 #endif 227 228 #define CONFIG_SYS_BAUDRATE_TABLE \ 229 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 230 231 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 232 233 #define CONFIG_SYS_I2C 234 #define CONFIG_SYS_I2C_FSL 235 #define CONFIG_SYS_FSL_I2C_SPEED 400000 236 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 237 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 238 239 /* I2C EEPROM */ 240 #define CONFIG_CMD_EEPROM 241 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 242 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 243 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 244 245 /* eSPI - Enhanced SPI */ 246 #ifdef CONFIG_FSL_ESPI 247 #define CONFIG_SF_DEFAULT_SPEED 10000000 248 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 249 #endif 250 251 #if defined(CONFIG_TSEC_ENET) 252 253 #define CONFIG_MII /* MII PHY management */ 254 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 255 #define CONFIG_TSEC1 1 256 #define CONFIG_TSEC1_NAME "eTSEC1" 257 #define CONFIG_TSEC2 1 258 #define CONFIG_TSEC2_NAME "eTSEC2" 259 260 #define TSEC1_PHY_ADDR 0 261 #define TSEC2_PHY_ADDR 3 262 263 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 264 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 265 266 #define TSEC1_PHYIDX 0 267 268 #define TSEC2_PHYIDX 0 269 270 #define CONFIG_ETHPRIME "eTSEC1" 271 272 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 273 274 #endif /* CONFIG_TSEC_ENET */ 275 276 /* 277 * Environment 278 */ 279 #if defined(CONFIG_RAMBOOT_SPIFLASH) 280 #define CONFIG_ENV_IS_IN_SPI_FLASH 281 #define CONFIG_ENV_SPI_BUS 0 282 #define CONFIG_ENV_SPI_CS 0 283 #define CONFIG_ENV_SPI_MAX_HZ 10000000 284 #define CONFIG_ENV_SPI_MODE 0 285 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 286 #define CONFIG_ENV_SECT_SIZE 0x10000 287 #define CONFIG_ENV_SIZE 0x2000 288 #elif defined(CONFIG_NAND) 289 #define CONFIG_ENV_IS_IN_NAND 290 #define CONFIG_SYS_EXTRA_ENV_RELOC 291 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 292 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 293 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 294 #elif defined(CONFIG_SYS_RAMBOOT) 295 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 296 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 297 #define CONFIG_ENV_SIZE 0x2000 298 #endif 299 300 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 301 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 302 303 /* 304 * Command line configuration. 305 */ 306 #define CONFIG_CMD_ERRATA 307 #define CONFIG_CMD_IRQ 308 #define CONFIG_DOS_PARTITION 309 #define CONFIG_CMD_REGINFO 310 311 /* 312 * Miscellaneous configurable options 313 */ 314 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 315 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 316 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 317 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 318 319 #if defined(CONFIG_CMD_KGDB) 320 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 321 #else 322 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 323 #endif 324 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 325 /* Print Buffer Size */ 326 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 327 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 328 329 /* 330 * For booting Linux, the board info and command line data 331 * have to be in the first 64 MB of memory, since this is 332 * the maximum mapped by the Linux kernel during initialization. 333 */ 334 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 335 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 336 337 #if defined(CONFIG_CMD_KGDB) 338 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 339 #endif 340 341 /* Hash command with SHA acceleration supported in hardware */ 342 #ifdef CONFIG_FSL_CAAM 343 #define CONFIG_CMD_HASH 344 #define CONFIG_SHA_HW_ACCEL 345 #endif 346 347 #define CONFIG_USB_EHCI 348 349 #ifdef CONFIG_USB_EHCI 350 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 351 #define CONFIG_USB_EHCI_FSL 352 #define CONFIG_HAS_FSL_DR_USB 353 #endif 354 355 /* 356 * Dynamic MTD Partition support with mtdparts 357 */ 358 #define CONFIG_MTD_DEVICE 359 #define CONFIG_MTD_PARTITIONS 360 #define CONFIG_CMD_MTDPARTS 361 #define MTDIDS_DEFAULT "nand0=ff800000.flash," 362 #define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \ 363 "8m(kernel),512k(dtb),-(fs)" 364 365 /* 366 * Environment Configuration 367 */ 368 369 #if defined(CONFIG_TSEC_ENET) 370 #define CONFIG_HAS_ETH0 371 #endif 372 373 #define CONFIG_HOSTNAME BSC9131rdb 374 #define CONFIG_ROOTPATH "/opt/nfsroot" 375 #define CONFIG_BOOTFILE "uImage" 376 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 377 378 #define CONFIG_BAUDRATE 115200 379 380 #define CONFIG_EXTRA_ENV_SETTINGS \ 381 "netdev=eth0\0" \ 382 "uboot=" CONFIG_UBOOTPATH "\0" \ 383 "loadaddr=1000000\0" \ 384 "bootfile=uImage\0" \ 385 "consoledev=ttyS0\0" \ 386 "ramdiskaddr=2000000\0" \ 387 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 388 "fdtaddr=1e00000\0" \ 389 "fdtfile=bsc9131rdb.dtb\0" \ 390 "bdev=sda1\0" \ 391 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 392 "bootm_size=0x37000000\0" \ 393 "othbootargs=ramdisk_size=600000 " \ 394 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \ 395 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 396 "console=$consoledev,$baudrate $othbootargs; " \ 397 "usb start;" \ 398 "ext2load usb 0:4 $loadaddr $bootfile;" \ 399 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 400 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 401 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 402 403 #define CONFIG_RAMBOOTCOMMAND \ 404 "setenv bootargs root=/dev/ram rw " \ 405 "console=$consoledev,$baudrate $othbootargs; " \ 406 "tftp $ramdiskaddr $ramdiskfile;" \ 407 "tftp $loadaddr $bootfile;" \ 408 "tftp $fdtaddr $fdtfile;" \ 409 "bootm $loadaddr $ramdiskaddr $fdtaddr" 410 411 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 412 413 #endif /* __CONFIG_H */ 414