1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9131 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_BSC9131RDB 15 #define CONFIG_BSC9131 16 #define CONFIG_NAND_FSL_IFC 17 #endif 18 19 #ifdef CONFIG_SPIFLASH 20 #define CONFIG_RAMBOOT_SPIFLASH 21 #define CONFIG_SYS_RAMBOOT 22 #define CONFIG_SYS_EXTRA_ENV_RELOC 23 #define CONFIG_SYS_TEXT_BASE 0x11000000 24 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 25 #endif 26 27 #ifdef CONFIG_NAND 28 #define CONFIG_SPL_INIT_MINIMAL 29 #define CONFIG_SPL_NAND_BOOT 30 #define CONFIG_SPL_FLUSH_IMAGE 31 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 32 33 #define CONFIG_SYS_TEXT_BASE 0x00201000 34 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 35 #define CONFIG_SPL_MAX_SIZE 8192 36 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 37 #define CONFIG_SPL_RELOC_STACK 0x00100000 38 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 39 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 40 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 41 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 42 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 43 #endif 44 45 #ifdef CONFIG_SPL_BUILD 46 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 47 #else 48 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 49 #endif 50 51 /* High Level Configuration Options */ 52 #define CONFIG_BOOKE /* BOOKE */ 53 #define CONFIG_E500 /* BOOKE e500 family */ 54 #define CONFIG_FSL_IFC /* Enable IFC Support */ 55 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 56 57 #define CONFIG_FSL_LAW /* Use common FSL init code */ 58 #define CONFIG_TSEC_ENET 59 #define CONFIG_ENV_OVERWRITE 60 61 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ 62 #if defined(CONFIG_SYS_CLK_100) 63 #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */ 64 #else 65 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ 66 #endif 67 68 #define CONFIG_HWCONFIG 69 /* 70 * These can be toggled for performance analysis, otherwise use default. 71 */ 72 #define CONFIG_L2_CACHE /* toggle L2 cache */ 73 #define CONFIG_BTB /* enable branch predition */ 74 75 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 76 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 77 78 /* DDR Setup */ 79 #define CONFIG_SYS_FSL_DDR3 80 #undef CONFIG_SYS_DDR_RAW_TIMING 81 #undef CONFIG_DDR_SPD 82 #define CONFIG_SYS_SPD_BUS_NUM 0 83 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ 84 85 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 86 87 #ifndef __ASSEMBLY__ 88 extern unsigned long get_sdram_size(void); 89 #endif 90 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 91 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 92 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 93 94 #define CONFIG_NUM_DDR_CONTROLLERS 1 95 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 96 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 97 98 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 99 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 100 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 101 102 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 103 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 104 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 105 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 106 107 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 108 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 109 #define CONFIG_SYS_DDR_RCW_1 0x00000000 110 #define CONFIG_SYS_DDR_RCW_2 0x00000000 111 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 112 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 113 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 114 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 115 116 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 117 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 118 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 119 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf 120 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 121 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 122 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 123 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 124 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 125 126 /* 127 * Base addresses -- Note these are effective addresses where the 128 * actual resources get mapped (not physical addresses) 129 */ 130 /* relocated CCSRBAR */ 131 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 132 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 133 134 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ 135 /* CONFIG_SYS_IMMR */ 136 /* DSP CCSRBAR */ 137 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 138 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 139 140 /* 141 * Memory map 142 * 143 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable 144 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M 145 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M 146 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M 147 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K 148 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K 149 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K 150 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M 151 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M 152 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M 153 * 154 */ 155 156 /* 157 * IFC Definitions 158 */ 159 #define CONFIG_SYS_NO_FLASH 160 161 /* NAND Flash on IFC */ 162 #define CONFIG_SYS_NAND_BASE 0xff800000 163 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 164 165 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 166 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ 167 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 168 | CSPR_V) 169 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 170 171 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 172 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 173 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 174 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 175 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 176 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 177 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 178 179 /* NAND Flash Timing Params */ 180 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 181 | FTIM0_NAND_TWP(0x05) \ 182 | FTIM0_NAND_TWCHT(0x02) \ 183 | FTIM0_NAND_TWH(0x04)) 184 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ 185 | FTIM1_NAND_TWBE(0x1E) \ 186 | FTIM1_NAND_TRR(0x07) \ 187 | FTIM1_NAND_TRP(0x05)) 188 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 189 | FTIM2_NAND_TREH(0x04) \ 190 | FTIM2_NAND_TWHRE(0x11)) 191 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 192 193 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 194 #define CONFIG_SYS_MAX_NAND_DEVICE 1 195 #define CONFIG_CMD_NAND 196 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 197 198 #define CONFIG_SYS_NAND_DDR_LAW 11 199 200 /* Set up IFC registers for boot location NAND */ 201 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 202 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 203 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 204 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 205 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 206 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 207 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 208 209 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 210 211 #define CONFIG_SYS_INIT_RAM_LOCK 212 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 213 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */ 214 215 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 216 - GENERATED_GBL_DATA_SIZE) 217 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 218 219 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 220 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 221 222 /* Serial Port */ 223 #define CONFIG_CONS_INDEX 1 224 #undef CONFIG_SERIAL_SOFTWARE_FIFO 225 #define CONFIG_SYS_NS16550_SERIAL 226 #define CONFIG_SYS_NS16550_REG_SIZE 1 227 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 228 #ifdef CONFIG_SPL_BUILD 229 #define CONFIG_NS16550_MIN_FUNCTIONS 230 #endif 231 232 #define CONFIG_SYS_BAUDRATE_TABLE \ 233 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 234 235 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 236 237 #define CONFIG_SYS_I2C 238 #define CONFIG_SYS_I2C_FSL 239 #define CONFIG_SYS_FSL_I2C_SPEED 400000 240 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 241 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 242 243 /* I2C EEPROM */ 244 #define CONFIG_CMD_EEPROM 245 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 246 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 247 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 248 249 /* eSPI - Enhanced SPI */ 250 #ifdef CONFIG_FSL_ESPI 251 #define CONFIG_SF_DEFAULT_SPEED 10000000 252 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 253 #endif 254 255 #if defined(CONFIG_TSEC_ENET) 256 257 #define CONFIG_MII /* MII PHY management */ 258 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 259 #define CONFIG_TSEC1 1 260 #define CONFIG_TSEC1_NAME "eTSEC1" 261 #define CONFIG_TSEC2 1 262 #define CONFIG_TSEC2_NAME "eTSEC2" 263 264 #define TSEC1_PHY_ADDR 0 265 #define TSEC2_PHY_ADDR 3 266 267 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 268 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 269 270 #define TSEC1_PHYIDX 0 271 272 #define TSEC2_PHYIDX 0 273 274 #define CONFIG_ETHPRIME "eTSEC1" 275 276 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 277 278 #endif /* CONFIG_TSEC_ENET */ 279 280 /* 281 * Environment 282 */ 283 #if defined(CONFIG_RAMBOOT_SPIFLASH) 284 #define CONFIG_ENV_IS_IN_SPI_FLASH 285 #define CONFIG_ENV_SPI_BUS 0 286 #define CONFIG_ENV_SPI_CS 0 287 #define CONFIG_ENV_SPI_MAX_HZ 10000000 288 #define CONFIG_ENV_SPI_MODE 0 289 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 290 #define CONFIG_ENV_SECT_SIZE 0x10000 291 #define CONFIG_ENV_SIZE 0x2000 292 #elif defined(CONFIG_NAND) 293 #define CONFIG_ENV_IS_IN_NAND 294 #define CONFIG_SYS_EXTRA_ENV_RELOC 295 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 296 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 297 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 298 #elif defined(CONFIG_SYS_RAMBOOT) 299 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 300 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 301 #define CONFIG_ENV_SIZE 0x2000 302 #endif 303 304 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 305 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 306 307 /* 308 * Command line configuration. 309 */ 310 #define CONFIG_CMD_ERRATA 311 #define CONFIG_CMD_IRQ 312 #define CONFIG_DOS_PARTITION 313 #define CONFIG_CMD_REGINFO 314 315 /* 316 * Miscellaneous configurable options 317 */ 318 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 319 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 320 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 321 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 322 323 #if defined(CONFIG_CMD_KGDB) 324 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 325 #else 326 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 327 #endif 328 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 329 /* Print Buffer Size */ 330 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 331 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 332 333 /* 334 * For booting Linux, the board info and command line data 335 * have to be in the first 64 MB of memory, since this is 336 * the maximum mapped by the Linux kernel during initialization. 337 */ 338 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 339 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 340 341 #if defined(CONFIG_CMD_KGDB) 342 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 343 #endif 344 345 /* Hash command with SHA acceleration supported in hardware */ 346 #ifdef CONFIG_FSL_CAAM 347 #define CONFIG_CMD_HASH 348 #define CONFIG_SHA_HW_ACCEL 349 #endif 350 351 #define CONFIG_USB_EHCI 352 353 #ifdef CONFIG_USB_EHCI 354 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 355 #define CONFIG_USB_EHCI_FSL 356 #define CONFIG_HAS_FSL_DR_USB 357 #endif 358 359 /* 360 * Dynamic MTD Partition support with mtdparts 361 */ 362 #define CONFIG_MTD_DEVICE 363 #define CONFIG_MTD_PARTITIONS 364 #define CONFIG_CMD_MTDPARTS 365 #define MTDIDS_DEFAULT "nand0=ff800000.flash," 366 #define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \ 367 "8m(kernel),512k(dtb),-(fs)" 368 369 /* 370 * Environment Configuration 371 */ 372 373 #if defined(CONFIG_TSEC_ENET) 374 #define CONFIG_HAS_ETH0 375 #endif 376 377 #define CONFIG_HOSTNAME BSC9131rdb 378 #define CONFIG_ROOTPATH "/opt/nfsroot" 379 #define CONFIG_BOOTFILE "uImage" 380 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 381 382 #define CONFIG_BAUDRATE 115200 383 384 #define CONFIG_EXTRA_ENV_SETTINGS \ 385 "netdev=eth0\0" \ 386 "uboot=" CONFIG_UBOOTPATH "\0" \ 387 "loadaddr=1000000\0" \ 388 "bootfile=uImage\0" \ 389 "consoledev=ttyS0\0" \ 390 "ramdiskaddr=2000000\0" \ 391 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 392 "fdtaddr=1e00000\0" \ 393 "fdtfile=bsc9131rdb.dtb\0" \ 394 "bdev=sda1\0" \ 395 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 396 "bootm_size=0x37000000\0" \ 397 "othbootargs=ramdisk_size=600000 " \ 398 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \ 399 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 400 "console=$consoledev,$baudrate $othbootargs; " \ 401 "usb start;" \ 402 "ext2load usb 0:4 $loadaddr $bootfile;" \ 403 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 404 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 405 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 406 407 #define CONFIG_RAMBOOTCOMMAND \ 408 "setenv bootargs root=/dev/ram rw " \ 409 "console=$consoledev,$baudrate $othbootargs; " \ 410 "tftp $ramdiskaddr $ramdiskfile;" \ 411 "tftp $loadaddr $bootfile;" \ 412 "tftp $fdtaddr $fdtfile;" \ 413 "bootm $loadaddr $ramdiskaddr $fdtaddr" 414 415 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 416 417 #endif /* __CONFIG_H */ 418