1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9131 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_BSC9131RDB 15 #define CONFIG_BSC9131 16 #define CONFIG_NAND_FSL_IFC 17 #endif 18 19 #ifdef CONFIG_SPIFLASH 20 #define CONFIG_RAMBOOT_SPIFLASH 21 #define CONFIG_SYS_RAMBOOT 22 #define CONFIG_SYS_EXTRA_ENV_RELOC 23 #define CONFIG_SYS_TEXT_BASE 0x11000000 24 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 25 #endif 26 27 #ifdef CONFIG_NAND 28 #define CONFIG_SPL_INIT_MINIMAL 29 #define CONFIG_SPL_SERIAL_SUPPORT 30 #define CONFIG_SPL_NAND_SUPPORT 31 #define CONFIG_SPL_NAND_BOOT 32 #define CONFIG_SPL_FLUSH_IMAGE 33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 34 35 #define CONFIG_SYS_TEXT_BASE 0x00201000 36 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 37 #define CONFIG_SPL_MAX_SIZE 8192 38 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 39 #define CONFIG_SPL_RELOC_STACK 0x00100000 40 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 41 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 42 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 43 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 44 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 45 #endif 46 47 #ifdef CONFIG_SPL_BUILD 48 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 49 #else 50 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 51 #endif 52 53 54 /* High Level Configuration Options */ 55 #define CONFIG_BOOKE /* BOOKE */ 56 #define CONFIG_E500 /* BOOKE e500 family */ 57 #define CONFIG_FSL_IFC /* Enable IFC Support */ 58 59 #define CONFIG_FSL_LAW /* Use common FSL init code */ 60 #define CONFIG_TSEC_ENET 61 #define CONFIG_ENV_OVERWRITE 62 63 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ 64 #if defined(CONFIG_SYS_CLK_100) 65 #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */ 66 #else 67 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ 68 #endif 69 70 #define CONFIG_HWCONFIG 71 /* 72 * These can be toggled for performance analysis, otherwise use default. 73 */ 74 #define CONFIG_L2_CACHE /* toggle L2 cache */ 75 #define CONFIG_BTB /* enable branch predition */ 76 77 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 78 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 79 80 /* DDR Setup */ 81 #define CONFIG_SYS_FSL_DDR3 82 #undef CONFIG_SYS_DDR_RAW_TIMING 83 #undef CONFIG_DDR_SPD 84 #define CONFIG_SYS_SPD_BUS_NUM 0 85 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ 86 87 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 88 89 #ifndef __ASSEMBLY__ 90 extern unsigned long get_sdram_size(void); 91 #endif 92 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 93 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 94 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 95 96 #define CONFIG_NUM_DDR_CONTROLLERS 1 97 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 98 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 99 100 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 101 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 102 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 103 104 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 105 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 106 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 107 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 108 109 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 110 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 111 #define CONFIG_SYS_DDR_RCW_1 0x00000000 112 #define CONFIG_SYS_DDR_RCW_2 0x00000000 113 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 114 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 115 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 116 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 117 118 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 119 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 120 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 121 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf 122 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 123 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 124 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 125 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 126 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 127 128 /* 129 * Base addresses -- Note these are effective addresses where the 130 * actual resources get mapped (not physical addresses) 131 */ 132 /* relocated CCSRBAR */ 133 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 134 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 135 136 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ 137 /* CONFIG_SYS_IMMR */ 138 /* DSP CCSRBAR */ 139 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 140 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 141 142 /* 143 * Memory map 144 * 145 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable 146 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M 147 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M 148 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M 149 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K 150 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K 151 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K 152 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M 153 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M 154 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M 155 * 156 */ 157 158 /* 159 * IFC Definitions 160 */ 161 #define CONFIG_SYS_NO_FLASH 162 163 /* NAND Flash on IFC */ 164 #define CONFIG_SYS_NAND_BASE 0xff800000 165 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 166 167 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 168 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ 169 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 170 | CSPR_V) 171 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 172 173 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 174 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 175 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 176 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 177 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 178 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 179 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 180 181 /* NAND Flash Timing Params */ 182 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 183 | FTIM0_NAND_TWP(0x05) \ 184 | FTIM0_NAND_TWCHT(0x02) \ 185 | FTIM0_NAND_TWH(0x04)) 186 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ 187 | FTIM1_NAND_TWBE(0x1E) \ 188 | FTIM1_NAND_TRR(0x07) \ 189 | FTIM1_NAND_TRP(0x05)) 190 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 191 | FTIM2_NAND_TREH(0x04) \ 192 | FTIM2_NAND_TWHRE(0x11)) 193 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 194 195 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 196 #define CONFIG_SYS_MAX_NAND_DEVICE 1 197 #define CONFIG_MTD_NAND_VERIFY_WRITE 198 #define CONFIG_CMD_NAND 199 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 200 201 #define CONFIG_SYS_NAND_DDR_LAW 11 202 203 /* Set up IFC registers for boot location NAND */ 204 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 205 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 206 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 207 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 208 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 209 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 210 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 211 212 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 213 214 #define CONFIG_SYS_INIT_RAM_LOCK 215 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 216 #define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */ 217 218 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 219 - GENERATED_GBL_DATA_SIZE) 220 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 221 222 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 223 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 224 225 /* Serial Port */ 226 #define CONFIG_CONS_INDEX 1 227 #undef CONFIG_SERIAL_SOFTWARE_FIFO 228 #define CONFIG_SYS_NS16550 229 #define CONFIG_SYS_NS16550_SERIAL 230 #define CONFIG_SYS_NS16550_REG_SIZE 1 231 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 232 #ifdef CONFIG_SPL_BUILD 233 #define CONFIG_NS16550_MIN_FUNCTIONS 234 #endif 235 236 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 237 238 #define CONFIG_SYS_BAUDRATE_TABLE \ 239 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 240 241 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 242 243 /* Use the HUSH parser */ 244 #define CONFIG_SYS_HUSH_PARSER 245 #ifdef CONFIG_SYS_HUSH_PARSER 246 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 247 #endif 248 249 /* 250 * Pass open firmware flat tree 251 */ 252 #define CONFIG_OF_LIBFDT 253 #define CONFIG_OF_BOARD_SETUP 254 #define CONFIG_OF_STDOUT_VIA_ALIAS 255 256 /* new uImage format support */ 257 #define CONFIG_FIT 258 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 259 260 #define CONFIG_SYS_I2C 261 #define CONFIG_SYS_I2C_FSL 262 #define CONFIG_SYS_FSL_I2C_SPEED 400000 263 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 264 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 265 266 /* I2C EEPROM */ 267 #define CONFIG_CMD_EEPROM 268 #define CONFIG_SYS_I2C_MULTI_EEPROMS 269 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 270 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 271 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 272 273 #define CONFIG_CMD_I2C 274 275 276 #define CONFIG_FSL_ESPI 277 /* eSPI - Enhanced SPI */ 278 #ifdef CONFIG_FSL_ESPI 279 #define CONFIG_SPI_FLASH 280 #define CONFIG_SPI_FLASH_SPANSION 281 #define CONFIG_CMD_SF 282 #define CONFIG_SF_DEFAULT_SPEED 10000000 283 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 284 #endif 285 286 #if defined(CONFIG_TSEC_ENET) 287 288 #define CONFIG_MII /* MII PHY management */ 289 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 290 #define CONFIG_TSEC1 1 291 #define CONFIG_TSEC1_NAME "eTSEC1" 292 #define CONFIG_TSEC2 1 293 #define CONFIG_TSEC2_NAME "eTSEC2" 294 295 #define TSEC1_PHY_ADDR 0 296 #define TSEC2_PHY_ADDR 3 297 298 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 299 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 300 301 #define TSEC1_PHYIDX 0 302 303 #define TSEC2_PHYIDX 0 304 305 #define CONFIG_ETHPRIME "eTSEC1" 306 307 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 308 309 #endif /* CONFIG_TSEC_ENET */ 310 311 /* 312 * Environment 313 */ 314 #if defined(CONFIG_RAMBOOT_SPIFLASH) 315 #define CONFIG_ENV_IS_IN_SPI_FLASH 316 #define CONFIG_ENV_SPI_BUS 0 317 #define CONFIG_ENV_SPI_CS 0 318 #define CONFIG_ENV_SPI_MAX_HZ 10000000 319 #define CONFIG_ENV_SPI_MODE 0 320 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 321 #define CONFIG_ENV_SECT_SIZE 0x10000 322 #define CONFIG_ENV_SIZE 0x2000 323 #elif defined(CONFIG_NAND) 324 #define CONFIG_ENV_IS_IN_NAND 325 #define CONFIG_SYS_EXTRA_ENV_RELOC 326 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 327 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 328 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 329 #elif defined(CONFIG_SYS_RAMBOOT) 330 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 331 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 332 #define CONFIG_ENV_SIZE 0x2000 333 #endif 334 335 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 336 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 337 338 /* 339 * Command line configuration. 340 */ 341 #include <config_cmd_default.h> 342 343 #define CONFIG_CMD_DHCP 344 #define CONFIG_CMD_ERRATA 345 #define CONFIG_CMD_ELF 346 #define CONFIG_CMD_EXT2 347 #define CONFIG_CMD_FAT 348 #define CONFIG_CMD_IRQ 349 #define CONFIG_CMD_MII 350 #define CONFIG_DOS_PARTITION 351 #define CONFIG_CMD_PING 352 #define CONFIG_CMD_REGINFO 353 #define CONFIG_CMD_SETEXPR 354 355 /* 356 * Miscellaneous configurable options 357 */ 358 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 359 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 360 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 361 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 362 363 #if defined(CONFIG_CMD_KGDB) 364 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 365 #else 366 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 367 #endif 368 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 369 /* Print Buffer Size */ 370 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 371 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 372 373 /* 374 * For booting Linux, the board info and command line data 375 * have to be in the first 64 MB of memory, since this is 376 * the maximum mapped by the Linux kernel during initialization. 377 */ 378 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 379 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 380 381 #if defined(CONFIG_CMD_KGDB) 382 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 383 #endif 384 385 #define CONFIG_USB_EHCI 386 387 #ifdef CONFIG_USB_EHCI 388 #define CONFIG_CMD_USB 389 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 390 #define CONFIG_USB_EHCI_FSL 391 #define CONFIG_USB_STORAGE 392 #define CONFIG_HAS_FSL_DR_USB 393 #endif 394 395 /* 396 * Environment Configuration 397 */ 398 399 #if defined(CONFIG_TSEC_ENET) 400 #define CONFIG_HAS_ETH0 401 #endif 402 403 #define CONFIG_HOSTNAME BSC9131rdb 404 #define CONFIG_ROOTPATH "/opt/nfsroot" 405 #define CONFIG_BOOTFILE "uImage" 406 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 407 408 #define CONFIG_BAUDRATE 115200 409 410 #define CONFIG_EXTRA_ENV_SETTINGS \ 411 "netdev=eth0\0" \ 412 "uboot=" CONFIG_UBOOTPATH "\0" \ 413 "loadaddr=1000000\0" \ 414 "bootfile=uImage\0" \ 415 "consoledev=ttyS0\0" \ 416 "ramdiskaddr=2000000\0" \ 417 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 418 "fdtaddr=c00000\0" \ 419 "fdtfile=bsc9131rdb.dtb\0" \ 420 "bdev=sda1\0" \ 421 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 422 "bootm_size=0x37000000\0" \ 423 "othbootargs=ramdisk_size=600000 " \ 424 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \ 425 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 426 "console=$consoledev,$baudrate $othbootargs; " \ 427 "usb start;" \ 428 "ext2load usb 0:4 $loadaddr $bootfile;" \ 429 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 430 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 431 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 432 433 #define CONFIG_RAMBOOTCOMMAND \ 434 "setenv bootargs root=/dev/ram rw " \ 435 "console=$consoledev,$baudrate $othbootargs; " \ 436 "tftp $ramdiskaddr $ramdiskfile;" \ 437 "tftp $loadaddr $bootfile;" \ 438 "tftp $fdtaddr $fdtfile;" \ 439 "bootm $loadaddr $ramdiskaddr $fdtaddr" 440 441 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 442 443 #endif /* __CONFIG_H */ 444