1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9131 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_NAND_FSL_IFC 15 16 #ifdef CONFIG_SPIFLASH 17 #define CONFIG_RAMBOOT_SPIFLASH 18 #define CONFIG_SYS_RAMBOOT 19 #define CONFIG_SYS_EXTRA_ENV_RELOC 20 #define CONFIG_SYS_TEXT_BASE 0x11000000 21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 22 #endif 23 24 #ifdef CONFIG_NAND 25 #define CONFIG_SPL_INIT_MINIMAL 26 #define CONFIG_SPL_NAND_BOOT 27 #define CONFIG_SPL_FLUSH_IMAGE 28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 29 30 #define CONFIG_SYS_TEXT_BASE 0x00201000 31 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 32 #define CONFIG_SPL_MAX_SIZE 8192 33 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 34 #define CONFIG_SPL_RELOC_STACK 0x00100000 35 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 36 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 37 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 38 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 39 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 40 #endif 41 42 #ifdef CONFIG_SPL_BUILD 43 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 44 #else 45 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 46 #endif 47 48 /* High Level Configuration Options */ 49 50 #define CONFIG_TSEC_ENET 51 #define CONFIG_ENV_OVERWRITE 52 53 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ 54 #if defined(CONFIG_SYS_CLK_100) 55 #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */ 56 #else 57 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ 58 #endif 59 60 #define CONFIG_HWCONFIG 61 /* 62 * These can be toggled for performance analysis, otherwise use default. 63 */ 64 #define CONFIG_L2_CACHE /* toggle L2 cache */ 65 #define CONFIG_BTB /* enable branch predition */ 66 67 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 68 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 69 70 /* DDR Setup */ 71 #undef CONFIG_SYS_DDR_RAW_TIMING 72 #undef CONFIG_DDR_SPD 73 #define CONFIG_SYS_SPD_BUS_NUM 0 74 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ 75 76 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 77 78 #ifndef __ASSEMBLY__ 79 extern unsigned long get_sdram_size(void); 80 #endif 81 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 82 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 83 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 84 85 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 86 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 87 88 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 89 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 90 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 91 92 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 93 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 94 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 95 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 96 97 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 98 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 99 #define CONFIG_SYS_DDR_RCW_1 0x00000000 100 #define CONFIG_SYS_DDR_RCW_2 0x00000000 101 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 102 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 103 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 104 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 105 106 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 107 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 108 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 109 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf 110 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 111 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 112 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 113 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 114 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 115 116 /* 117 * Base addresses -- Note these are effective addresses where the 118 * actual resources get mapped (not physical addresses) 119 */ 120 /* relocated CCSRBAR */ 121 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 122 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 123 124 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ 125 /* CONFIG_SYS_IMMR */ 126 /* DSP CCSRBAR */ 127 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 128 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 129 130 /* 131 * Memory map 132 * 133 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable 134 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M 135 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M 136 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M 137 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K 138 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K 139 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K 140 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M 141 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M 142 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M 143 * 144 */ 145 146 /* 147 * IFC Definitions 148 */ 149 150 /* NAND Flash on IFC */ 151 #define CONFIG_SYS_NAND_BASE 0xff800000 152 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 153 154 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 155 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ 156 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 157 | CSPR_V) 158 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 159 160 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 161 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 162 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 163 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 164 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 165 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 166 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 167 168 /* NAND Flash Timing Params */ 169 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 170 | FTIM0_NAND_TWP(0x05) \ 171 | FTIM0_NAND_TWCHT(0x02) \ 172 | FTIM0_NAND_TWH(0x04)) 173 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ 174 | FTIM1_NAND_TWBE(0x1E) \ 175 | FTIM1_NAND_TRR(0x07) \ 176 | FTIM1_NAND_TRP(0x05)) 177 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 178 | FTIM2_NAND_TREH(0x04) \ 179 | FTIM2_NAND_TWHRE(0x11)) 180 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 181 182 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 183 #define CONFIG_SYS_MAX_NAND_DEVICE 1 184 #define CONFIG_CMD_NAND 185 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 186 187 #define CONFIG_SYS_NAND_DDR_LAW 11 188 189 /* Set up IFC registers for boot location NAND */ 190 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 191 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 192 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 193 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 194 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 195 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 196 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 197 198 #define CONFIG_SYS_INIT_RAM_LOCK 199 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 200 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */ 201 202 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 203 - GENERATED_GBL_DATA_SIZE) 204 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 205 206 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 207 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 208 209 /* Serial Port */ 210 #define CONFIG_CONS_INDEX 1 211 #undef CONFIG_SERIAL_SOFTWARE_FIFO 212 #define CONFIG_SYS_NS16550_SERIAL 213 #define CONFIG_SYS_NS16550_REG_SIZE 1 214 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 215 #ifdef CONFIG_SPL_BUILD 216 #define CONFIG_NS16550_MIN_FUNCTIONS 217 #endif 218 219 #define CONFIG_SYS_BAUDRATE_TABLE \ 220 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 221 222 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 223 224 #define CONFIG_SYS_I2C 225 #define CONFIG_SYS_I2C_FSL 226 #define CONFIG_SYS_FSL_I2C_SPEED 400000 227 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 228 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 229 230 /* I2C EEPROM */ 231 #define CONFIG_CMD_EEPROM 232 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 234 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 235 236 /* eSPI - Enhanced SPI */ 237 #ifdef CONFIG_FSL_ESPI 238 #define CONFIG_SF_DEFAULT_SPEED 10000000 239 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 240 #endif 241 242 #if defined(CONFIG_TSEC_ENET) 243 244 #define CONFIG_MII /* MII PHY management */ 245 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 246 #define CONFIG_TSEC1 1 247 #define CONFIG_TSEC1_NAME "eTSEC1" 248 #define CONFIG_TSEC2 1 249 #define CONFIG_TSEC2_NAME "eTSEC2" 250 251 #define TSEC1_PHY_ADDR 0 252 #define TSEC2_PHY_ADDR 3 253 254 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 255 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 256 257 #define TSEC1_PHYIDX 0 258 259 #define TSEC2_PHYIDX 0 260 261 #define CONFIG_ETHPRIME "eTSEC1" 262 263 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 264 265 #endif /* CONFIG_TSEC_ENET */ 266 267 /* 268 * Environment 269 */ 270 #if defined(CONFIG_RAMBOOT_SPIFLASH) 271 #define CONFIG_ENV_IS_IN_SPI_FLASH 272 #define CONFIG_ENV_SPI_BUS 0 273 #define CONFIG_ENV_SPI_CS 0 274 #define CONFIG_ENV_SPI_MAX_HZ 10000000 275 #define CONFIG_ENV_SPI_MODE 0 276 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 277 #define CONFIG_ENV_SECT_SIZE 0x10000 278 #define CONFIG_ENV_SIZE 0x2000 279 #elif defined(CONFIG_NAND) 280 #define CONFIG_ENV_IS_IN_NAND 281 #define CONFIG_SYS_EXTRA_ENV_RELOC 282 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 283 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 284 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 285 #elif defined(CONFIG_SYS_RAMBOOT) 286 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 287 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 288 #define CONFIG_ENV_SIZE 0x2000 289 #endif 290 291 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 292 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 293 294 /* 295 * Command line configuration. 296 */ 297 #define CONFIG_CMD_ERRATA 298 #define CONFIG_CMD_IRQ 299 #define CONFIG_CMD_REGINFO 300 301 /* 302 * Miscellaneous configurable options 303 */ 304 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 305 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 306 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 307 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 308 309 #if defined(CONFIG_CMD_KGDB) 310 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 311 #else 312 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 313 #endif 314 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 315 /* Print Buffer Size */ 316 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 317 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 318 319 /* 320 * For booting Linux, the board info and command line data 321 * have to be in the first 64 MB of memory, since this is 322 * the maximum mapped by the Linux kernel during initialization. 323 */ 324 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 325 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 326 327 #if defined(CONFIG_CMD_KGDB) 328 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 329 #endif 330 331 /* Hash command with SHA acceleration supported in hardware */ 332 #ifdef CONFIG_FSL_CAAM 333 #define CONFIG_CMD_HASH 334 #define CONFIG_SHA_HW_ACCEL 335 #endif 336 337 #define CONFIG_USB_EHCI 338 339 #ifdef CONFIG_USB_EHCI 340 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 341 #define CONFIG_USB_EHCI_FSL 342 #define CONFIG_HAS_FSL_DR_USB 343 #endif 344 345 /* 346 * Dynamic MTD Partition support with mtdparts 347 */ 348 #define CONFIG_MTD_DEVICE 349 #define CONFIG_MTD_PARTITIONS 350 #define CONFIG_CMD_MTDPARTS 351 #define MTDIDS_DEFAULT "nand0=ff800000.flash," 352 #define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \ 353 "8m(kernel),512k(dtb),-(fs)" 354 355 /* 356 * Environment Configuration 357 */ 358 359 #if defined(CONFIG_TSEC_ENET) 360 #define CONFIG_HAS_ETH0 361 #endif 362 363 #define CONFIG_HOSTNAME BSC9131rdb 364 #define CONFIG_ROOTPATH "/opt/nfsroot" 365 #define CONFIG_BOOTFILE "uImage" 366 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 367 368 #define CONFIG_BAUDRATE 115200 369 370 #define CONFIG_EXTRA_ENV_SETTINGS \ 371 "netdev=eth0\0" \ 372 "uboot=" CONFIG_UBOOTPATH "\0" \ 373 "loadaddr=1000000\0" \ 374 "bootfile=uImage\0" \ 375 "consoledev=ttyS0\0" \ 376 "ramdiskaddr=2000000\0" \ 377 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 378 "fdtaddr=1e00000\0" \ 379 "fdtfile=bsc9131rdb.dtb\0" \ 380 "bdev=sda1\0" \ 381 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 382 "bootm_size=0x37000000\0" \ 383 "othbootargs=ramdisk_size=600000 " \ 384 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \ 385 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 386 "console=$consoledev,$baudrate $othbootargs; " \ 387 "usb start;" \ 388 "ext2load usb 0:4 $loadaddr $bootfile;" \ 389 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 390 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 391 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 392 393 #define CONFIG_RAMBOOTCOMMAND \ 394 "setenv bootargs root=/dev/ram rw " \ 395 "console=$consoledev,$baudrate $othbootargs; " \ 396 "tftp $ramdiskaddr $ramdiskfile;" \ 397 "tftp $loadaddr $bootfile;" \ 398 "tftp $fdtaddr $fdtfile;" \ 399 "bootm $loadaddr $ramdiskaddr $fdtaddr" 400 401 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 402 403 #endif /* __CONFIG_H */ 404