1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9131 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_BSC9131RDB 17 #define CONFIG_BSC9131 18 #define CONFIG_NAND_FSL_IFC 19 #endif 20 21 #ifdef CONFIG_SPIFLASH 22 #define CONFIG_RAMBOOT_SPIFLASH 23 #define CONFIG_SYS_RAMBOOT 24 #define CONFIG_SYS_EXTRA_ENV_RELOC 25 #define CONFIG_SYS_TEXT_BASE 0x11000000 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 27 #endif 28 29 #ifdef CONFIG_NAND 30 #define CONFIG_SPL_INIT_MINIMAL 31 #define CONFIG_SPL_SERIAL_SUPPORT 32 #define CONFIG_SPL_NAND_SUPPORT 33 #define CONFIG_SPL_NAND_BOOT 34 #define CONFIG_SPL_FLUSH_IMAGE 35 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 36 37 #define CONFIG_SYS_TEXT_BASE 0x00201000 38 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 39 #define CONFIG_SPL_MAX_SIZE 8192 40 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 41 #define CONFIG_SPL_RELOC_STACK 0x00100000 42 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 43 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 44 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 45 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 46 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 47 #endif 48 49 #ifdef CONFIG_SPL_BUILD 50 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 51 #else 52 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 53 #endif 54 55 56 /* High Level Configuration Options */ 57 #define CONFIG_BOOKE /* BOOKE */ 58 #define CONFIG_E500 /* BOOKE e500 family */ 59 #define CONFIG_FSL_IFC /* Enable IFC Support */ 60 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 61 62 #define CONFIG_FSL_LAW /* Use common FSL init code */ 63 #define CONFIG_TSEC_ENET 64 #define CONFIG_ENV_OVERWRITE 65 66 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ 67 #if defined(CONFIG_SYS_CLK_100) 68 #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */ 69 #else 70 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ 71 #endif 72 73 #define CONFIG_HWCONFIG 74 /* 75 * These can be toggled for performance analysis, otherwise use default. 76 */ 77 #define CONFIG_L2_CACHE /* toggle L2 cache */ 78 #define CONFIG_BTB /* enable branch predition */ 79 80 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 81 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 82 83 /* DDR Setup */ 84 #define CONFIG_SYS_FSL_DDR3 85 #undef CONFIG_SYS_DDR_RAW_TIMING 86 #undef CONFIG_DDR_SPD 87 #define CONFIG_SYS_SPD_BUS_NUM 0 88 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ 89 90 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 91 92 #ifndef __ASSEMBLY__ 93 extern unsigned long get_sdram_size(void); 94 #endif 95 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 96 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 97 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 98 99 #define CONFIG_NUM_DDR_CONTROLLERS 1 100 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 101 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 102 103 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 104 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 105 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 106 107 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 108 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 109 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 110 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 111 112 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 113 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 114 #define CONFIG_SYS_DDR_RCW_1 0x00000000 115 #define CONFIG_SYS_DDR_RCW_2 0x00000000 116 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 117 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 118 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 119 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 120 121 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 122 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 123 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 124 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf 125 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 126 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 127 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 128 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 129 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 130 131 /* 132 * Base addresses -- Note these are effective addresses where the 133 * actual resources get mapped (not physical addresses) 134 */ 135 /* relocated CCSRBAR */ 136 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 137 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 138 139 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ 140 /* CONFIG_SYS_IMMR */ 141 /* DSP CCSRBAR */ 142 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 143 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 144 145 /* 146 * Memory map 147 * 148 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable 149 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M 150 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M 151 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M 152 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K 153 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K 154 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K 155 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M 156 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M 157 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M 158 * 159 */ 160 161 /* 162 * IFC Definitions 163 */ 164 #define CONFIG_SYS_NO_FLASH 165 166 /* NAND Flash on IFC */ 167 #define CONFIG_SYS_NAND_BASE 0xff800000 168 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 169 170 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 171 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ 172 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 173 | CSPR_V) 174 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 175 176 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 177 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 178 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 179 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 180 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 181 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 182 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 183 184 /* NAND Flash Timing Params */ 185 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 186 | FTIM0_NAND_TWP(0x05) \ 187 | FTIM0_NAND_TWCHT(0x02) \ 188 | FTIM0_NAND_TWH(0x04)) 189 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ 190 | FTIM1_NAND_TWBE(0x1E) \ 191 | FTIM1_NAND_TRR(0x07) \ 192 | FTIM1_NAND_TRP(0x05)) 193 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 194 | FTIM2_NAND_TREH(0x04) \ 195 | FTIM2_NAND_TWHRE(0x11)) 196 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 197 198 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 199 #define CONFIG_SYS_MAX_NAND_DEVICE 1 200 #define CONFIG_CMD_NAND 201 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 202 203 #define CONFIG_SYS_NAND_DDR_LAW 11 204 205 /* Set up IFC registers for boot location NAND */ 206 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 207 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 208 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 209 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 210 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 211 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 212 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 213 214 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 215 216 #define CONFIG_SYS_INIT_RAM_LOCK 217 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 218 #define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */ 219 220 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 221 - GENERATED_GBL_DATA_SIZE) 222 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 223 224 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 225 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 226 227 /* Serial Port */ 228 #define CONFIG_CONS_INDEX 1 229 #undef CONFIG_SERIAL_SOFTWARE_FIFO 230 #define CONFIG_SYS_NS16550_SERIAL 231 #define CONFIG_SYS_NS16550_REG_SIZE 1 232 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 233 #ifdef CONFIG_SPL_BUILD 234 #define CONFIG_NS16550_MIN_FUNCTIONS 235 #endif 236 237 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 238 239 #define CONFIG_SYS_BAUDRATE_TABLE \ 240 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 241 242 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 243 244 /* Use the HUSH parser */ 245 #define CONFIG_SYS_HUSH_PARSER 246 #ifdef CONFIG_SYS_HUSH_PARSER 247 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 248 #endif 249 250 /* 251 * Pass open firmware flat tree 252 */ 253 #define CONFIG_OF_LIBFDT 254 #define CONFIG_OF_BOARD_SETUP 255 #define CONFIG_OF_STDOUT_VIA_ALIAS 256 257 /* new uImage format support */ 258 #define CONFIG_FIT 259 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 260 261 #define CONFIG_SYS_I2C 262 #define CONFIG_SYS_I2C_FSL 263 #define CONFIG_SYS_FSL_I2C_SPEED 400000 264 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 265 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 266 267 /* I2C EEPROM */ 268 #define CONFIG_CMD_EEPROM 269 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 270 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 271 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 272 273 #define CONFIG_CMD_I2C 274 275 276 /* eSPI - Enhanced SPI */ 277 #ifdef CONFIG_FSL_ESPI 278 #define CONFIG_CMD_SF 279 #define CONFIG_SF_DEFAULT_SPEED 10000000 280 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 281 #endif 282 283 #if defined(CONFIG_TSEC_ENET) 284 285 #define CONFIG_MII /* MII PHY management */ 286 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 287 #define CONFIG_TSEC1 1 288 #define CONFIG_TSEC1_NAME "eTSEC1" 289 #define CONFIG_TSEC2 1 290 #define CONFIG_TSEC2_NAME "eTSEC2" 291 292 #define TSEC1_PHY_ADDR 0 293 #define TSEC2_PHY_ADDR 3 294 295 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 296 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 297 298 #define TSEC1_PHYIDX 0 299 300 #define TSEC2_PHYIDX 0 301 302 #define CONFIG_ETHPRIME "eTSEC1" 303 304 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 305 306 #endif /* CONFIG_TSEC_ENET */ 307 308 /* 309 * Environment 310 */ 311 #if defined(CONFIG_RAMBOOT_SPIFLASH) 312 #define CONFIG_ENV_IS_IN_SPI_FLASH 313 #define CONFIG_ENV_SPI_BUS 0 314 #define CONFIG_ENV_SPI_CS 0 315 #define CONFIG_ENV_SPI_MAX_HZ 10000000 316 #define CONFIG_ENV_SPI_MODE 0 317 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 318 #define CONFIG_ENV_SECT_SIZE 0x10000 319 #define CONFIG_ENV_SIZE 0x2000 320 #elif defined(CONFIG_NAND) 321 #define CONFIG_ENV_IS_IN_NAND 322 #define CONFIG_SYS_EXTRA_ENV_RELOC 323 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 324 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 325 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 326 #elif defined(CONFIG_SYS_RAMBOOT) 327 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 328 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 329 #define CONFIG_ENV_SIZE 0x2000 330 #endif 331 332 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 333 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 334 335 /* 336 * Command line configuration. 337 */ 338 #define CONFIG_CMD_DHCP 339 #define CONFIG_CMD_ERRATA 340 #define CONFIG_CMD_EXT2 341 #define CONFIG_CMD_FAT 342 #define CONFIG_CMD_IRQ 343 #define CONFIG_CMD_MII 344 #define CONFIG_DOS_PARTITION 345 #define CONFIG_CMD_PING 346 #define CONFIG_CMD_REGINFO 347 348 /* 349 * Miscellaneous configurable options 350 */ 351 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 352 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 353 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 354 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 355 356 #if defined(CONFIG_CMD_KGDB) 357 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 358 #else 359 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 360 #endif 361 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 362 /* Print Buffer Size */ 363 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 364 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 365 366 /* 367 * For booting Linux, the board info and command line data 368 * have to be in the first 64 MB of memory, since this is 369 * the maximum mapped by the Linux kernel during initialization. 370 */ 371 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 372 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 373 374 #if defined(CONFIG_CMD_KGDB) 375 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 376 #endif 377 378 /* Hash command with SHA acceleration supported in hardware */ 379 #ifdef CONFIG_FSL_CAAM 380 #define CONFIG_CMD_HASH 381 #define CONFIG_SHA_HW_ACCEL 382 #endif 383 384 #define CONFIG_USB_EHCI 385 386 #ifdef CONFIG_USB_EHCI 387 #define CONFIG_CMD_USB 388 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 389 #define CONFIG_USB_EHCI_FSL 390 #define CONFIG_USB_STORAGE 391 #define CONFIG_HAS_FSL_DR_USB 392 #endif 393 394 /* 395 * Dynamic MTD Partition support with mtdparts 396 */ 397 #define CONFIG_MTD_DEVICE 398 #define CONFIG_MTD_PARTITIONS 399 #define CONFIG_CMD_MTDPARTS 400 #define MTDIDS_DEFAULT "nand0=ff800000.flash," 401 #define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \ 402 "8m(kernel),512k(dtb),-(fs)" 403 /* 404 * Override partitions in device tree using info 405 * in "mtdparts" environment variable 406 */ 407 #ifdef CONFIG_CMD_MTDPARTS 408 #define CONFIG_FDT_FIXUP_PARTITIONS 409 #endif 410 411 /* 412 * Environment Configuration 413 */ 414 415 #if defined(CONFIG_TSEC_ENET) 416 #define CONFIG_HAS_ETH0 417 #endif 418 419 #define CONFIG_HOSTNAME BSC9131rdb 420 #define CONFIG_ROOTPATH "/opt/nfsroot" 421 #define CONFIG_BOOTFILE "uImage" 422 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 423 424 #define CONFIG_BAUDRATE 115200 425 #define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */ 426 427 #define CONFIG_EXTRA_ENV_SETTINGS \ 428 "netdev=eth0\0" \ 429 "uboot=" CONFIG_UBOOTPATH "\0" \ 430 "loadaddr=1000000\0" \ 431 "bootfile=uImage\0" \ 432 "consoledev=ttyS0\0" \ 433 "ramdiskaddr=2000000\0" \ 434 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 435 "fdtaddr=c00000\0" \ 436 "fdtfile=bsc9131rdb.dtb\0" \ 437 "bdev=sda1\0" \ 438 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 439 "bootm_size=0x37000000\0" \ 440 "othbootargs=ramdisk_size=600000 " \ 441 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \ 442 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 443 "console=$consoledev,$baudrate $othbootargs; " \ 444 "usb start;" \ 445 "ext2load usb 0:4 $loadaddr $bootfile;" \ 446 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 447 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 448 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 449 450 #define CONFIG_RAMBOOTCOMMAND \ 451 "setenv bootargs root=/dev/ram rw " \ 452 "console=$consoledev,$baudrate $othbootargs; " \ 453 "tftp $ramdiskaddr $ramdiskfile;" \ 454 "tftp $loadaddr $bootfile;" \ 455 "tftp $fdtaddr $fdtfile;" \ 456 "bootm $loadaddr $ramdiskaddr $fdtaddr" 457 458 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 459 460 #endif /* __CONFIG_H */ 461