17530d341SPrabhakar Kushwaha /* 27530d341SPrabhakar Kushwaha * Copyright 2011-2012 Freescale Semiconductor, Inc. 37530d341SPrabhakar Kushwaha * 47530d341SPrabhakar Kushwaha * See file CREDITS for list of people who contributed to this 57530d341SPrabhakar Kushwaha * project. 67530d341SPrabhakar Kushwaha * 77530d341SPrabhakar Kushwaha * This program is free software; you can redistribute it and/or 87530d341SPrabhakar Kushwaha * modify it under the terms of the GNU General Public License as 97530d341SPrabhakar Kushwaha * published by the Free Software Foundation; either version 2 of 107530d341SPrabhakar Kushwaha * the License, or (at your option) any later version. 117530d341SPrabhakar Kushwaha * 127530d341SPrabhakar Kushwaha * This program is distributed in the hope that it will be useful, 137530d341SPrabhakar Kushwaha * but WITHOUT ANY WARRANTY; without even the implied warranty of 147530d341SPrabhakar Kushwaha * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the 157530d341SPrabhakar Kushwaha * GNU General Public License for more details. 167530d341SPrabhakar Kushwaha * 177530d341SPrabhakar Kushwaha * You should have received a copy of the GNU General Public License 187530d341SPrabhakar Kushwaha * along with this program; if not, write to the Free Software 197530d341SPrabhakar Kushwaha * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 207530d341SPrabhakar Kushwaha * MA 02111-1307 USA 217530d341SPrabhakar Kushwaha */ 227530d341SPrabhakar Kushwaha 237530d341SPrabhakar Kushwaha /* 247530d341SPrabhakar Kushwaha * BSC9131 RDB board configuration file 257530d341SPrabhakar Kushwaha */ 267530d341SPrabhakar Kushwaha 277530d341SPrabhakar Kushwaha #ifndef __CONFIG_H 287530d341SPrabhakar Kushwaha #define __CONFIG_H 297530d341SPrabhakar Kushwaha 307530d341SPrabhakar Kushwaha #ifdef CONFIG_BSC9131RDB 317530d341SPrabhakar Kushwaha #define CONFIG_BSC9131 327530d341SPrabhakar Kushwaha #define CONFIG_NAND_FSL_IFC 337530d341SPrabhakar Kushwaha #endif 347530d341SPrabhakar Kushwaha 357530d341SPrabhakar Kushwaha #ifdef CONFIG_SPIFLASH 367530d341SPrabhakar Kushwaha #define CONFIG_RAMBOOT_SPIFLASH 377530d341SPrabhakar Kushwaha #define CONFIG_SYS_RAMBOOT 387530d341SPrabhakar Kushwaha #define CONFIG_SYS_EXTRA_ENV_RELOC 397530d341SPrabhakar Kushwaha #define CONFIG_SYS_TEXT_BASE 0x11000000 407530d341SPrabhakar Kushwaha #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 417530d341SPrabhakar Kushwaha #endif 427530d341SPrabhakar Kushwaha 43f1593269SPrabhakar Kushwaha #ifdef CONFIG_NAND 44f1593269SPrabhakar Kushwaha #define CONFIG_SPL 45f1593269SPrabhakar Kushwaha #define CONFIG_SPL_INIT_MINIMAL 46f1593269SPrabhakar Kushwaha #define CONFIG_SPL_SERIAL_SUPPORT 47f1593269SPrabhakar Kushwaha #define CONFIG_SPL_NAND_SUPPORT 48f1593269SPrabhakar Kushwaha #define CONFIG_SPL_NAND_MINIMAL 49f1593269SPrabhakar Kushwaha #define CONFIG_SPL_FLUSH_IMAGE 50f1593269SPrabhakar Kushwaha #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 51f1593269SPrabhakar Kushwaha 52f1593269SPrabhakar Kushwaha #define CONFIG_SYS_TEXT_BASE 0x00201000 53f1593269SPrabhakar Kushwaha #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 54f1593269SPrabhakar Kushwaha #define CONFIG_SPL_MAX_SIZE 8192 55f1593269SPrabhakar Kushwaha #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 56f1593269SPrabhakar Kushwaha #define CONFIG_SPL_RELOC_STACK 0x00100000 57f1593269SPrabhakar Kushwaha #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 58f1593269SPrabhakar Kushwaha #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 59f1593269SPrabhakar Kushwaha #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 60f1593269SPrabhakar Kushwaha #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 61f1593269SPrabhakar Kushwaha #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 62f1593269SPrabhakar Kushwaha #endif 63f1593269SPrabhakar Kushwaha 64f1593269SPrabhakar Kushwaha #ifdef CONFIG_SPL_BUILD 65f1593269SPrabhakar Kushwaha #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 66f1593269SPrabhakar Kushwaha #else 677530d341SPrabhakar Kushwaha #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 687530d341SPrabhakar Kushwaha #endif 697530d341SPrabhakar Kushwaha 70f1593269SPrabhakar Kushwaha 717530d341SPrabhakar Kushwaha /* High Level Configuration Options */ 727530d341SPrabhakar Kushwaha #define CONFIG_BOOKE /* BOOKE */ 737530d341SPrabhakar Kushwaha #define CONFIG_E500 /* BOOKE e500 family */ 747530d341SPrabhakar Kushwaha #define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/ 757530d341SPrabhakar Kushwaha #define CONFIG_FSL_IFC /* Enable IFC Support */ 767530d341SPrabhakar Kushwaha 777530d341SPrabhakar Kushwaha #define CONFIG_FSL_LAW /* Use common FSL init code */ 787530d341SPrabhakar Kushwaha #define CONFIG_TSEC_ENET 797530d341SPrabhakar Kushwaha #define CONFIG_ENV_OVERWRITE 807530d341SPrabhakar Kushwaha 817530d341SPrabhakar Kushwaha #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ 82*087cf44fSPriyanka Jain #if defined(CONFIG_SYS_CLK_100) 83*087cf44fSPriyanka Jain #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */ 84*087cf44fSPriyanka Jain #else 857530d341SPrabhakar Kushwaha #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ 86*087cf44fSPriyanka Jain #endif 877530d341SPrabhakar Kushwaha 887530d341SPrabhakar Kushwaha #define CONFIG_HWCONFIG 897530d341SPrabhakar Kushwaha /* 907530d341SPrabhakar Kushwaha * These can be toggled for performance analysis, otherwise use default. 917530d341SPrabhakar Kushwaha */ 927530d341SPrabhakar Kushwaha #define CONFIG_L2_CACHE /* toggle L2 cache */ 937530d341SPrabhakar Kushwaha #define CONFIG_BTB /* enable branch predition */ 947530d341SPrabhakar Kushwaha 957530d341SPrabhakar Kushwaha #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 967530d341SPrabhakar Kushwaha #define CONFIG_SYS_MEMTEST_END 0x01ffffff 977530d341SPrabhakar Kushwaha 987530d341SPrabhakar Kushwaha /* DDR Setup */ 997530d341SPrabhakar Kushwaha #define CONFIG_FSL_DDR3 1007530d341SPrabhakar Kushwaha #undef CONFIG_SYS_DDR_RAW_TIMING 1017530d341SPrabhakar Kushwaha #undef CONFIG_DDR_SPD 1027530d341SPrabhakar Kushwaha #define CONFIG_SYS_SPD_BUS_NUM 0 1037530d341SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ 1047530d341SPrabhakar Kushwaha 1057530d341SPrabhakar Kushwaha #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 1067530d341SPrabhakar Kushwaha 1077530d341SPrabhakar Kushwaha #ifndef __ASSEMBLY__ 1087530d341SPrabhakar Kushwaha extern unsigned long get_sdram_size(void); 1097530d341SPrabhakar Kushwaha #endif 1107530d341SPrabhakar Kushwaha #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 1117530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 1127530d341SPrabhakar Kushwaha #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 1137530d341SPrabhakar Kushwaha 1147530d341SPrabhakar Kushwaha #define CONFIG_NUM_DDR_CONTROLLERS 1 1157530d341SPrabhakar Kushwaha #define CONFIG_DIMM_SLOTS_PER_CTLR 1 1167530d341SPrabhakar Kushwaha #define CONFIG_CHIP_SELECTS_PER_CTRL 1 1177530d341SPrabhakar Kushwaha 1187530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 1197530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 1207530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 1217530d341SPrabhakar Kushwaha 1227530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 1237530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 1247530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 1257530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 1267530d341SPrabhakar Kushwaha 1277530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 1287530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 1297530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_RCW_1 0x00000000 1307530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_RCW_2 0x00000000 1317530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 1327530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 1337530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_TIMING_4 0x00000001 1347530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_TIMING_5 0x02401400 1357530d341SPrabhakar Kushwaha 1367530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 1377530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 1387530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 1397530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf 1407530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 1417530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 1427530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 1437530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 1447530d341SPrabhakar Kushwaha #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 1457530d341SPrabhakar Kushwaha 1467530d341SPrabhakar Kushwaha /* 1477530d341SPrabhakar Kushwaha * Base addresses -- Note these are effective addresses where the 1487530d341SPrabhakar Kushwaha * actual resources get mapped (not physical addresses) 1497530d341SPrabhakar Kushwaha */ 1507530d341SPrabhakar Kushwaha /* relocated CCSRBAR */ 1517530d341SPrabhakar Kushwaha #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 1527530d341SPrabhakar Kushwaha #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 1537530d341SPrabhakar Kushwaha 1547530d341SPrabhakar Kushwaha #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ 1557530d341SPrabhakar Kushwaha /* CONFIG_SYS_IMMR */ 1567530d341SPrabhakar Kushwaha 1577530d341SPrabhakar Kushwaha /* 1587530d341SPrabhakar Kushwaha * Memory map 1597530d341SPrabhakar Kushwaha * 1607530d341SPrabhakar Kushwaha * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable 1617530d341SPrabhakar Kushwaha * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M 1627530d341SPrabhakar Kushwaha * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M 1637530d341SPrabhakar Kushwaha * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K 1647530d341SPrabhakar Kushwaha * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K 1657530d341SPrabhakar Kushwaha * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K 1667530d341SPrabhakar Kushwaha * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M 1677530d341SPrabhakar Kushwaha * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M 1687530d341SPrabhakar Kushwaha * 1697530d341SPrabhakar Kushwaha */ 1707530d341SPrabhakar Kushwaha 1717530d341SPrabhakar Kushwaha /* 1727530d341SPrabhakar Kushwaha * IFC Definitions 1737530d341SPrabhakar Kushwaha */ 1747530d341SPrabhakar Kushwaha #define CONFIG_SYS_NO_FLASH 1757530d341SPrabhakar Kushwaha 1767530d341SPrabhakar Kushwaha /* NAND Flash on IFC */ 1777530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_BASE 0xff800000 1787530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 1797530d341SPrabhakar Kushwaha 1807530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 1817530d341SPrabhakar Kushwaha | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ 1827530d341SPrabhakar Kushwaha | CSPR_MSEL_NAND /* MSEL = NAND */ \ 1837530d341SPrabhakar Kushwaha | CSPR_V) 1847530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 1857530d341SPrabhakar Kushwaha 1867530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 1877530d341SPrabhakar Kushwaha | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 1887530d341SPrabhakar Kushwaha | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 1897530d341SPrabhakar Kushwaha | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 1907530d341SPrabhakar Kushwaha | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 1917530d341SPrabhakar Kushwaha | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 1927530d341SPrabhakar Kushwaha | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 1937530d341SPrabhakar Kushwaha 1947530d341SPrabhakar Kushwaha /* NAND Flash Timing Params */ 1957530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x08) \ 1967530d341SPrabhakar Kushwaha | FTIM0_NAND_TWP(0x06) \ 1977530d341SPrabhakar Kushwaha | FTIM0_NAND_TWCHT(0x03) \ 1987530d341SPrabhakar Kushwaha | FTIM0_NAND_TWH(0x04)) 1997530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x18) \ 2007530d341SPrabhakar Kushwaha | FTIM1_NAND_TWBE(0x23) \ 2017530d341SPrabhakar Kushwaha | FTIM1_NAND_TRR(0x08) \ 2027530d341SPrabhakar Kushwaha | FTIM1_NAND_TRP(0x05)) 2037530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 2047530d341SPrabhakar Kushwaha | FTIM2_NAND_TREH(0x04) \ 2057530d341SPrabhakar Kushwaha | FTIM2_NAND_TWHRE(0x3f)) 2067530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x22) 2077530d341SPrabhakar Kushwaha 2087530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 2097530d341SPrabhakar Kushwaha #define CONFIG_SYS_MAX_NAND_DEVICE 1 2107530d341SPrabhakar Kushwaha #define CONFIG_MTD_NAND_VERIFY_WRITE 2117530d341SPrabhakar Kushwaha #define CONFIG_CMD_NAND 2127530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 2137530d341SPrabhakar Kushwaha 2147530d341SPrabhakar Kushwaha #define CONFIG_SYS_NAND_DDR_LAW 11 2157530d341SPrabhakar Kushwaha 2167530d341SPrabhakar Kushwaha /* Set up IFC registers for boot location NAND */ 2177530d341SPrabhakar Kushwaha #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 2187530d341SPrabhakar Kushwaha #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 2197530d341SPrabhakar Kushwaha #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 2207530d341SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 2217530d341SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 2227530d341SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 2237530d341SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 2247530d341SPrabhakar Kushwaha 2257530d341SPrabhakar Kushwaha #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 2267530d341SPrabhakar Kushwaha 2277530d341SPrabhakar Kushwaha #define CONFIG_SYS_INIT_RAM_LOCK 2287530d341SPrabhakar Kushwaha #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 2297530d341SPrabhakar Kushwaha #define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */ 2307530d341SPrabhakar Kushwaha 2317530d341SPrabhakar Kushwaha #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 2327530d341SPrabhakar Kushwaha - GENERATED_GBL_DATA_SIZE) 2337530d341SPrabhakar Kushwaha #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 2347530d341SPrabhakar Kushwaha 2357530d341SPrabhakar Kushwaha #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ 2367530d341SPrabhakar Kushwaha #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 2377530d341SPrabhakar Kushwaha 2387530d341SPrabhakar Kushwaha /* Serial Port */ 2397530d341SPrabhakar Kushwaha #define CONFIG_CONS_INDEX 1 2407530d341SPrabhakar Kushwaha #undef CONFIG_SERIAL_SOFTWARE_FIFO 2417530d341SPrabhakar Kushwaha #define CONFIG_SYS_NS16550 2427530d341SPrabhakar Kushwaha #define CONFIG_SYS_NS16550_SERIAL 2437530d341SPrabhakar Kushwaha #define CONFIG_SYS_NS16550_REG_SIZE 1 2447530d341SPrabhakar Kushwaha #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 245f1593269SPrabhakar Kushwaha #ifdef CONFIG_SPL_BUILD 246f1593269SPrabhakar Kushwaha #define CONFIG_NS16550_MIN_FUNCTIONS 247f1593269SPrabhakar Kushwaha #endif 2487530d341SPrabhakar Kushwaha 2497530d341SPrabhakar Kushwaha #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 2507530d341SPrabhakar Kushwaha 2517530d341SPrabhakar Kushwaha #define CONFIG_SYS_BAUDRATE_TABLE \ 2527530d341SPrabhakar Kushwaha {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 2537530d341SPrabhakar Kushwaha 2547530d341SPrabhakar Kushwaha #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 2557530d341SPrabhakar Kushwaha 2567530d341SPrabhakar Kushwaha /* Use the HUSH parser */ 2577530d341SPrabhakar Kushwaha #define CONFIG_SYS_HUSH_PARSER 2587530d341SPrabhakar Kushwaha #ifdef CONFIG_SYS_HUSH_PARSER 2597530d341SPrabhakar Kushwaha #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 2607530d341SPrabhakar Kushwaha #endif 2617530d341SPrabhakar Kushwaha 2627530d341SPrabhakar Kushwaha /* 2637530d341SPrabhakar Kushwaha * Pass open firmware flat tree 2647530d341SPrabhakar Kushwaha */ 2657530d341SPrabhakar Kushwaha #define CONFIG_OF_LIBFDT 2667530d341SPrabhakar Kushwaha #define CONFIG_OF_BOARD_SETUP 2677530d341SPrabhakar Kushwaha #define CONFIG_OF_STDOUT_VIA_ALIAS 2687530d341SPrabhakar Kushwaha 2697530d341SPrabhakar Kushwaha /* new uImage format support */ 2707530d341SPrabhakar Kushwaha #define CONFIG_FIT 2717530d341SPrabhakar Kushwaha #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 2727530d341SPrabhakar Kushwaha 2737530d341SPrabhakar Kushwaha #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 2747530d341SPrabhakar Kushwaha #define CONFIG_HARD_I2C /* I2C with hardware support */ 2757530d341SPrabhakar Kushwaha #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 2767530d341SPrabhakar Kushwaha #define CONFIG_I2C_MULTI_BUS 2777530d341SPrabhakar Kushwaha #define CONFIG_I2C_CMD_TREE 2787530d341SPrabhakar Kushwaha #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ 2797530d341SPrabhakar Kushwaha #define CONFIG_SYS_I2C_OFFSET 0x3000 2807530d341SPrabhakar Kushwaha 2817530d341SPrabhakar Kushwaha /* I2C EEPROM */ 2827530d341SPrabhakar Kushwaha #define CONFIG_CMD_EEPROM 2837530d341SPrabhakar Kushwaha #define CONFIG_SYS_I2C_MULTI_EEPROMS 2847530d341SPrabhakar Kushwaha #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 2857530d341SPrabhakar Kushwaha #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 2867530d341SPrabhakar Kushwaha #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 2877530d341SPrabhakar Kushwaha 2887530d341SPrabhakar Kushwaha #define CONFIG_CMD_I2C 2897530d341SPrabhakar Kushwaha 2907530d341SPrabhakar Kushwaha 2917530d341SPrabhakar Kushwaha #define CONFIG_FSL_ESPI 2927530d341SPrabhakar Kushwaha /* eSPI - Enhanced SPI */ 2937530d341SPrabhakar Kushwaha #ifdef CONFIG_FSL_ESPI 2947530d341SPrabhakar Kushwaha #define CONFIG_SPI_FLASH 2957530d341SPrabhakar Kushwaha #define CONFIG_SPI_FLASH_SPANSION 2967530d341SPrabhakar Kushwaha #define CONFIG_CMD_SF 2977530d341SPrabhakar Kushwaha #define CONFIG_SF_DEFAULT_SPEED 10000000 2987530d341SPrabhakar Kushwaha #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 2997530d341SPrabhakar Kushwaha #endif 3007530d341SPrabhakar Kushwaha 3017530d341SPrabhakar Kushwaha #if defined(CONFIG_TSEC_ENET) 3027530d341SPrabhakar Kushwaha 3037530d341SPrabhakar Kushwaha #define CONFIG_MII /* MII PHY management */ 3047530d341SPrabhakar Kushwaha #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 3057530d341SPrabhakar Kushwaha #define CONFIG_TSEC1 1 3067530d341SPrabhakar Kushwaha #define CONFIG_TSEC1_NAME "eTSEC1" 3077530d341SPrabhakar Kushwaha #define CONFIG_TSEC2 1 3087530d341SPrabhakar Kushwaha #define CONFIG_TSEC2_NAME "eTSEC2" 3097530d341SPrabhakar Kushwaha 3107530d341SPrabhakar Kushwaha #define TSEC1_PHY_ADDR 0 3117530d341SPrabhakar Kushwaha #define TSEC2_PHY_ADDR 3 3127530d341SPrabhakar Kushwaha 3137530d341SPrabhakar Kushwaha #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 3147530d341SPrabhakar Kushwaha #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 3157530d341SPrabhakar Kushwaha 3167530d341SPrabhakar Kushwaha #define TSEC1_PHYIDX 0 3177530d341SPrabhakar Kushwaha 3187530d341SPrabhakar Kushwaha #define TSEC2_PHYIDX 0 3197530d341SPrabhakar Kushwaha 3207530d341SPrabhakar Kushwaha #define CONFIG_ETHPRIME "eTSEC1" 3217530d341SPrabhakar Kushwaha 3227530d341SPrabhakar Kushwaha #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 3237530d341SPrabhakar Kushwaha 3247530d341SPrabhakar Kushwaha #endif /* CONFIG_TSEC_ENET */ 3257530d341SPrabhakar Kushwaha 3267530d341SPrabhakar Kushwaha /* 3277530d341SPrabhakar Kushwaha * Environment 3287530d341SPrabhakar Kushwaha */ 3297530d341SPrabhakar Kushwaha #if defined(CONFIG_RAMBOOT_SPIFLASH) 3307530d341SPrabhakar Kushwaha #define CONFIG_ENV_IS_IN_SPI_FLASH 3317530d341SPrabhakar Kushwaha #define CONFIG_ENV_SPI_BUS 0 3327530d341SPrabhakar Kushwaha #define CONFIG_ENV_SPI_CS 0 3337530d341SPrabhakar Kushwaha #define CONFIG_ENV_SPI_MAX_HZ 10000000 3347530d341SPrabhakar Kushwaha #define CONFIG_ENV_SPI_MODE 0 3357530d341SPrabhakar Kushwaha #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 3367530d341SPrabhakar Kushwaha #define CONFIG_ENV_SECT_SIZE 0x10000 3377530d341SPrabhakar Kushwaha #define CONFIG_ENV_SIZE 0x2000 338f1593269SPrabhakar Kushwaha #elif defined(CONFIG_NAND) 339f1593269SPrabhakar Kushwaha #define CONFIG_ENV_IS_IN_NAND 340f1593269SPrabhakar Kushwaha #define CONFIG_SYS_EXTRA_ENV_RELOC 341f1593269SPrabhakar Kushwaha #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 342f1593269SPrabhakar Kushwaha #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 343f1593269SPrabhakar Kushwaha #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 344f1593269SPrabhakar Kushwaha #elif defined(CONFIG_SYS_RAMBOOT) 3457530d341SPrabhakar Kushwaha #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 3467530d341SPrabhakar Kushwaha #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 3477530d341SPrabhakar Kushwaha #define CONFIG_ENV_SIZE 0x2000 3487530d341SPrabhakar Kushwaha #endif 3497530d341SPrabhakar Kushwaha 3507530d341SPrabhakar Kushwaha #define CONFIG_LOADS_ECHO /* echo on for serial download */ 3517530d341SPrabhakar Kushwaha #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 3527530d341SPrabhakar Kushwaha 3537530d341SPrabhakar Kushwaha /* 3547530d341SPrabhakar Kushwaha * Command line configuration. 3557530d341SPrabhakar Kushwaha */ 3567530d341SPrabhakar Kushwaha #include <config_cmd_default.h> 3577530d341SPrabhakar Kushwaha 3587530d341SPrabhakar Kushwaha #define CONFIG_CMD_DHCP 3597530d341SPrabhakar Kushwaha #define CONFIG_CMD_ERRATA 3607530d341SPrabhakar Kushwaha #define CONFIG_CMD_ELF 3617530d341SPrabhakar Kushwaha #define CONFIG_CMD_EXT2 3627530d341SPrabhakar Kushwaha #define CONFIG_CMD_FAT 3637530d341SPrabhakar Kushwaha #define CONFIG_CMD_IRQ 3647530d341SPrabhakar Kushwaha #define CONFIG_CMD_MII 3657530d341SPrabhakar Kushwaha #define CONFIG_DOS_PARTITION 3667530d341SPrabhakar Kushwaha #define CONFIG_CMD_PING 3677530d341SPrabhakar Kushwaha #define CONFIG_CMD_REGINFO 3687530d341SPrabhakar Kushwaha #define CONFIG_CMD_SETEXPR 3697530d341SPrabhakar Kushwaha 3707530d341SPrabhakar Kushwaha /* 3717530d341SPrabhakar Kushwaha * Miscellaneous configurable options 3727530d341SPrabhakar Kushwaha */ 3737530d341SPrabhakar Kushwaha #define CONFIG_SYS_LONGHELP /* undef to save memory */ 3747530d341SPrabhakar Kushwaha #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 3757530d341SPrabhakar Kushwaha #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 3767530d341SPrabhakar Kushwaha #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 3777530d341SPrabhakar Kushwaha #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 3787530d341SPrabhakar Kushwaha 3797530d341SPrabhakar Kushwaha #if defined(CONFIG_CMD_KGDB) 3807530d341SPrabhakar Kushwaha #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 3817530d341SPrabhakar Kushwaha #else 3827530d341SPrabhakar Kushwaha #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 3837530d341SPrabhakar Kushwaha #endif 3847530d341SPrabhakar Kushwaha #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 3857530d341SPrabhakar Kushwaha /* Print Buffer Size */ 3867530d341SPrabhakar Kushwaha #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 3877530d341SPrabhakar Kushwaha #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 3887530d341SPrabhakar Kushwaha #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 3897530d341SPrabhakar Kushwaha 3907530d341SPrabhakar Kushwaha /* 3917530d341SPrabhakar Kushwaha * For booting Linux, the board info and command line data 3927530d341SPrabhakar Kushwaha * have to be in the first 64 MB of memory, since this is 3937530d341SPrabhakar Kushwaha * the maximum mapped by the Linux kernel during initialization. 3947530d341SPrabhakar Kushwaha */ 3957530d341SPrabhakar Kushwaha #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 3967530d341SPrabhakar Kushwaha #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 3977530d341SPrabhakar Kushwaha 3987530d341SPrabhakar Kushwaha #if defined(CONFIG_CMD_KGDB) 3997530d341SPrabhakar Kushwaha #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 4007530d341SPrabhakar Kushwaha #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 4017530d341SPrabhakar Kushwaha #endif 4027530d341SPrabhakar Kushwaha 4037530d341SPrabhakar Kushwaha #define CONFIG_USB_EHCI 4047530d341SPrabhakar Kushwaha 4057530d341SPrabhakar Kushwaha #ifdef CONFIG_USB_EHCI 4067530d341SPrabhakar Kushwaha #define CONFIG_CMD_USB 4077530d341SPrabhakar Kushwaha #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 4087530d341SPrabhakar Kushwaha #define CONFIG_USB_EHCI_FSL 4097530d341SPrabhakar Kushwaha #define CONFIG_USB_STORAGE 4107530d341SPrabhakar Kushwaha #define CONFIG_HAS_FSL_DR_USB 4117530d341SPrabhakar Kushwaha #endif 4127530d341SPrabhakar Kushwaha 4137530d341SPrabhakar Kushwaha /* 4147530d341SPrabhakar Kushwaha * Environment Configuration 4157530d341SPrabhakar Kushwaha */ 4167530d341SPrabhakar Kushwaha 4177530d341SPrabhakar Kushwaha #if defined(CONFIG_TSEC_ENET) 4187530d341SPrabhakar Kushwaha #define CONFIG_HAS_ETH0 4197530d341SPrabhakar Kushwaha #endif 4207530d341SPrabhakar Kushwaha 4217530d341SPrabhakar Kushwaha #define CONFIG_HOSTNAME BSC9131rdb 4227530d341SPrabhakar Kushwaha #define CONFIG_ROOTPATH "/opt/nfsroot" 4237530d341SPrabhakar Kushwaha #define CONFIG_BOOTFILE "uImage" 4247530d341SPrabhakar Kushwaha #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 4257530d341SPrabhakar Kushwaha 4267530d341SPrabhakar Kushwaha #define CONFIG_BAUDRATE 115200 4277530d341SPrabhakar Kushwaha 4287530d341SPrabhakar Kushwaha #define CONFIG_EXTRA_ENV_SETTINGS \ 4297530d341SPrabhakar Kushwaha "netdev=eth0\0" \ 4307530d341SPrabhakar Kushwaha "uboot=" CONFIG_UBOOTPATH "\0" \ 4317530d341SPrabhakar Kushwaha "loadaddr=1000000\0" \ 4327530d341SPrabhakar Kushwaha "bootfile=uImage\0" \ 4337530d341SPrabhakar Kushwaha "consoledev=ttyS0\0" \ 4347530d341SPrabhakar Kushwaha "ramdiskaddr=2000000\0" \ 4357530d341SPrabhakar Kushwaha "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 4367530d341SPrabhakar Kushwaha "fdtaddr=c00000\0" \ 4377530d341SPrabhakar Kushwaha "fdtfile=bsc9131rdb.dtb\0" \ 4387530d341SPrabhakar Kushwaha "bdev=sda1\0" \ 4397530d341SPrabhakar Kushwaha "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 4407530d341SPrabhakar Kushwaha "othbootargs=ramdisk_size=600000 \0" \ 4417530d341SPrabhakar Kushwaha "usbext2boot=setenv bootargs root=/dev/ram rw " \ 4427530d341SPrabhakar Kushwaha "console=$consoledev,$baudrate $othbootargs; " \ 4437530d341SPrabhakar Kushwaha "usb start;" \ 4447530d341SPrabhakar Kushwaha "ext2load usb 0:4 $loadaddr $bootfile;" \ 4457530d341SPrabhakar Kushwaha "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 4467530d341SPrabhakar Kushwaha "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 4477530d341SPrabhakar Kushwaha "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 4487530d341SPrabhakar Kushwaha 4497530d341SPrabhakar Kushwaha #define CONFIG_RAMBOOTCOMMAND \ 4507530d341SPrabhakar Kushwaha "setenv bootargs root=/dev/ram rw " \ 4517530d341SPrabhakar Kushwaha "console=$consoledev,$baudrate $othbootargs; " \ 4527530d341SPrabhakar Kushwaha "tftp $ramdiskaddr $ramdiskfile;" \ 4537530d341SPrabhakar Kushwaha "tftp $loadaddr $bootfile;" \ 4547530d341SPrabhakar Kushwaha "tftp $fdtaddr $fdtfile;" \ 4557530d341SPrabhakar Kushwaha "bootm $loadaddr $ramdiskaddr $fdtaddr" 4567530d341SPrabhakar Kushwaha 4577530d341SPrabhakar Kushwaha #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 4587530d341SPrabhakar Kushwaha 4597530d341SPrabhakar Kushwaha #endif /* __CONFIG_H */ 460