1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 /* 10 * B4860 QDS board configuration file 11 */ 12 #ifdef CONFIG_RAMBOOT_PBL 13 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 14 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 15 #ifndef CONFIG_NAND 16 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 18 #else 19 #define CONFIG_SPL_FLUSH_IMAGE 20 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 21 #define CONFIG_SPL_PAD_TO 0x40000 22 #define CONFIG_SPL_MAX_SIZE 0x28000 23 #define RESET_VECTOR_OFFSET 0x27FFC 24 #define BOOT_PAGE_OFFSET 0x27000 25 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 26 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 27 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 28 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 29 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 30 #define CONFIG_SPL_NAND_BOOT 31 #ifdef CONFIG_SPL_BUILD 32 #define CONFIG_SPL_SKIP_RELOCATE 33 #define CONFIG_SPL_COMMON_INIT_DDR 34 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #endif 46 47 /* High Level Configuration Options */ 48 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 49 50 #ifndef CONFIG_RESET_VECTOR_ADDRESS 51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 52 #endif 53 54 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 55 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 56 #define CONFIG_PCIE1 /* PCIE controller 1 */ 57 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 58 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 59 60 #ifndef CONFIG_ARCH_B4420 61 #define CONFIG_SYS_SRIO 62 #define CONFIG_SRIO1 /* SRIO port 1 */ 63 #define CONFIG_SRIO2 /* SRIO port 2 */ 64 #define CONFIG_SRIO_PCIE_BOOT_MASTER 65 #endif 66 67 /* I2C bus multiplexer */ 68 #define I2C_MUX_PCA_ADDR 0x77 69 70 /* VSC Crossbar switches */ 71 #define CONFIG_VSC_CROSSBAR 72 #define I2C_CH_DEFAULT 0x8 73 #define I2C_CH_VSC3316 0xc 74 #define I2C_CH_VSC3308 0xd 75 76 #define VSC3316_TX_ADDRESS 0x70 77 #define VSC3316_RX_ADDRESS 0x71 78 #define VSC3308_TX_ADDRESS 0x02 79 #define VSC3308_RX_ADDRESS 0x03 80 81 /* IDT clock synthesizers */ 82 #define CONFIG_IDT8T49N222A 83 #define I2C_CH_IDT 0x9 84 85 #define IDT_SERDES1_ADDRESS 0x6E 86 #define IDT_SERDES2_ADDRESS 0x6C 87 88 /* Voltage monitor on channel 2*/ 89 #define I2C_MUX_CH_VOL_MONITOR 0xa 90 #define I2C_VOL_MONITOR_ADDR 0x40 91 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 92 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 93 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 94 95 #define CONFIG_ZM7300 96 #define I2C_MUX_CH_DPM 0xa 97 #define I2C_DPM_ADDR 0x28 98 99 #define CONFIG_ENV_OVERWRITE 100 101 #ifndef CONFIG_MTD_NOR_FLASH 102 #else 103 #define CONFIG_FLASH_CFI_DRIVER 104 #define CONFIG_SYS_FLASH_CFI 105 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 106 #endif 107 108 #if defined(CONFIG_SPIFLASH) 109 #define CONFIG_ENV_SPI_BUS 0 110 #define CONFIG_ENV_SPI_CS 0 111 #define CONFIG_ENV_SPI_MAX_HZ 10000000 112 #define CONFIG_ENV_SPI_MODE 0 113 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 114 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 115 #define CONFIG_ENV_SECT_SIZE 0x10000 116 #elif defined(CONFIG_SDCARD) 117 #define CONFIG_SYS_MMC_ENV_DEV 0 118 #define CONFIG_ENV_SIZE 0x2000 119 #define CONFIG_ENV_OFFSET (512 * 1097) 120 #elif defined(CONFIG_NAND) 121 #define CONFIG_ENV_SIZE 0x2000 122 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 123 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 124 #define CONFIG_ENV_ADDR 0xffe20000 125 #define CONFIG_ENV_SIZE 0x2000 126 #elif defined(CONFIG_ENV_IS_NOWHERE) 127 #define CONFIG_ENV_SIZE 0x2000 128 #else 129 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 130 #define CONFIG_ENV_SIZE 0x2000 131 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 132 #endif 133 134 #ifndef __ASSEMBLY__ 135 unsigned long get_board_sys_clk(void); 136 unsigned long get_board_ddr_clk(void); 137 #endif 138 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 139 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 140 141 /* 142 * These can be toggled for performance analysis, otherwise use default. 143 */ 144 #define CONFIG_SYS_CACHE_STASHING 145 #define CONFIG_BTB /* toggle branch predition */ 146 #define CONFIG_DDR_ECC 147 #ifdef CONFIG_DDR_ECC 148 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 149 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 150 #endif 151 152 #define CONFIG_ENABLE_36BIT_PHYS 153 154 #ifdef CONFIG_PHYS_64BIT 155 #define CONFIG_ADDR_MAP 156 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 157 #endif 158 159 #if 0 160 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 161 #endif 162 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 163 #define CONFIG_SYS_MEMTEST_END 0x00400000 164 165 /* 166 * Config the L3 Cache as L3 SRAM 167 */ 168 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 169 #define CONFIG_SYS_L3_SIZE 256 << 10 170 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 171 #ifdef CONFIG_NAND 172 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 173 #endif 174 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 175 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 176 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 177 178 #ifdef CONFIG_PHYS_64BIT 179 #define CONFIG_SYS_DCSRBAR 0xf0000000 180 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 181 #endif 182 183 /* EEPROM */ 184 #define CONFIG_ID_EEPROM 185 #define CONFIG_SYS_I2C_EEPROM_NXID 186 #define CONFIG_SYS_EEPROM_BUS_NUM 0 187 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 188 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 189 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 190 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 191 192 /* 193 * DDR Setup 194 */ 195 #define CONFIG_VERY_BIG_RAM 196 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 197 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 198 199 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 200 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 201 202 #define CONFIG_DDR_SPD 203 #define CONFIG_SYS_DDR_RAW_TIMING 204 #ifndef CONFIG_SPL_BUILD 205 #define CONFIG_FSL_DDR_INTERACTIVE 206 #endif 207 208 #define CONFIG_SYS_SPD_BUS_NUM 0 209 #define SPD_EEPROM_ADDRESS1 0x51 210 #define SPD_EEPROM_ADDRESS2 0x53 211 212 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 213 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 214 215 /* 216 * IFC Definitions 217 */ 218 #define CONFIG_SYS_FLASH_BASE 0xe0000000 219 #ifdef CONFIG_PHYS_64BIT 220 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 221 #else 222 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 223 #endif 224 225 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 226 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 227 + 0x8000000) | \ 228 CSPR_PORT_SIZE_16 | \ 229 CSPR_MSEL_NOR | \ 230 CSPR_V) 231 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 232 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 233 CSPR_PORT_SIZE_16 | \ 234 CSPR_MSEL_NOR | \ 235 CSPR_V) 236 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 237 /* NOR Flash Timing Params */ 238 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 239 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 240 FTIM0_NOR_TEADC(0x04) | \ 241 FTIM0_NOR_TEAHC(0x20)) 242 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 243 FTIM1_NOR_TRAD_NOR(0x1A) |\ 244 FTIM1_NOR_TSEQRAD_NOR(0x13)) 245 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 246 FTIM2_NOR_TCH(0x0E) | \ 247 FTIM2_NOR_TWPH(0x0E) | \ 248 FTIM2_NOR_TWP(0x1c)) 249 #define CONFIG_SYS_NOR_FTIM3 0x0 250 251 #define CONFIG_SYS_FLASH_QUIET_TEST 252 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 253 254 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 255 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 256 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 257 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 258 259 #define CONFIG_SYS_FLASH_EMPTY_INFO 260 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 261 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 262 263 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 264 #define CONFIG_FSL_QIXIS_V2 265 #define QIXIS_BASE 0xffdf0000 266 #ifdef CONFIG_PHYS_64BIT 267 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 268 #else 269 #define QIXIS_BASE_PHYS QIXIS_BASE 270 #endif 271 #define QIXIS_LBMAP_SWITCH 0x01 272 #define QIXIS_LBMAP_MASK 0x0f 273 #define QIXIS_LBMAP_SHIFT 0 274 #define QIXIS_LBMAP_DFLTBANK 0x00 275 #define QIXIS_LBMAP_ALTBANK 0x02 276 #define QIXIS_RST_CTL_RESET 0x31 277 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 278 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 279 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 280 281 #define CONFIG_SYS_CSPR3_EXT (0xf) 282 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 283 | CSPR_PORT_SIZE_8 \ 284 | CSPR_MSEL_GPCM \ 285 | CSPR_V) 286 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 287 #define CONFIG_SYS_CSOR3 0x0 288 /* QIXIS Timing parameters for IFC CS3 */ 289 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 290 FTIM0_GPCM_TEADC(0x0e) | \ 291 FTIM0_GPCM_TEAHC(0x0e)) 292 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 293 FTIM1_GPCM_TRAD(0x1f)) 294 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 295 FTIM2_GPCM_TCH(0x8) | \ 296 FTIM2_GPCM_TWP(0x1f)) 297 #define CONFIG_SYS_CS3_FTIM3 0x0 298 299 /* NAND Flash on IFC */ 300 #define CONFIG_NAND_FSL_IFC 301 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 302 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 303 #define CONFIG_SYS_NAND_BASE 0xff800000 304 #ifdef CONFIG_PHYS_64BIT 305 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 306 #else 307 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 308 #endif 309 310 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 311 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 312 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 313 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 314 | CSPR_V) 315 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 316 317 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 318 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 319 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 320 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 321 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 322 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 323 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 324 325 #define CONFIG_SYS_NAND_ONFI_DETECTION 326 327 /* ONFI NAND Flash mode0 Timing Params */ 328 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 329 FTIM0_NAND_TWP(0x18) | \ 330 FTIM0_NAND_TWCHT(0x07) | \ 331 FTIM0_NAND_TWH(0x0a)) 332 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 333 FTIM1_NAND_TWBE(0x39) | \ 334 FTIM1_NAND_TRR(0x0e) | \ 335 FTIM1_NAND_TRP(0x18)) 336 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 337 FTIM2_NAND_TREH(0x0a) | \ 338 FTIM2_NAND_TWHRE(0x1e)) 339 #define CONFIG_SYS_NAND_FTIM3 0x0 340 341 #define CONFIG_SYS_NAND_DDR_LAW 11 342 343 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 344 #define CONFIG_SYS_MAX_NAND_DEVICE 1 345 346 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 347 348 #if defined(CONFIG_NAND) 349 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 350 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 351 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 352 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 353 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 354 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 355 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 356 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 357 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 358 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 359 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 360 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 361 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 362 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 363 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 364 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 365 #else 366 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 367 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 368 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 369 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 370 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 371 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 372 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 373 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 374 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 375 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 376 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 377 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 378 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 379 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 380 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 381 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 382 #endif 383 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 384 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 385 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 386 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 387 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 388 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 389 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 390 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 391 392 #ifdef CONFIG_SPL_BUILD 393 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 394 #else 395 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 396 #endif 397 398 #if defined(CONFIG_RAMBOOT_PBL) 399 #define CONFIG_SYS_RAMBOOT 400 #endif 401 402 #define CONFIG_HWCONFIG 403 404 /* define to use L1 as initial stack */ 405 #define CONFIG_L1_INIT_RAM 406 #define CONFIG_SYS_INIT_RAM_LOCK 407 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 408 #ifdef CONFIG_PHYS_64BIT 409 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 410 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 411 /* The assembler doesn't like typecast */ 412 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 413 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 414 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 415 #else 416 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 417 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 419 #endif 420 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 421 422 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 423 GENERATED_GBL_DATA_SIZE) 424 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 425 426 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 427 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 428 429 /* Serial Port - controlled on board with jumper J8 430 * open - index 2 431 * shorted - index 1 432 */ 433 #define CONFIG_SYS_NS16550_SERIAL 434 #define CONFIG_SYS_NS16550_REG_SIZE 1 435 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 436 437 #define CONFIG_SYS_BAUDRATE_TABLE \ 438 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 439 440 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 441 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 442 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 443 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 444 445 /* I2C */ 446 #define CONFIG_SYS_I2C 447 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 448 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 449 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 450 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 451 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 452 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 453 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 454 455 /* 456 * RTC configuration 457 */ 458 #define RTC 459 #define CONFIG_RTC_DS3231 1 460 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 461 462 /* 463 * RapidIO 464 */ 465 #ifdef CONFIG_SYS_SRIO 466 #ifdef CONFIG_SRIO1 467 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 468 #ifdef CONFIG_PHYS_64BIT 469 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 470 #else 471 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 472 #endif 473 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 474 #endif 475 476 #ifdef CONFIG_SRIO2 477 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 478 #ifdef CONFIG_PHYS_64BIT 479 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 480 #else 481 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 482 #endif 483 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 484 #endif 485 #endif 486 487 /* 488 * for slave u-boot IMAGE instored in master memory space, 489 * PHYS must be aligned based on the SIZE 490 */ 491 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 492 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 493 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 494 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 495 /* 496 * for slave UCODE and ENV instored in master memory space, 497 * PHYS must be aligned based on the SIZE 498 */ 499 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 500 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 501 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 502 503 /* slave core release by master*/ 504 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 505 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 506 507 /* 508 * SRIO_PCIE_BOOT - SLAVE 509 */ 510 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 511 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 512 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 513 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 514 #endif 515 516 /* 517 * eSPI - Enhanced SPI 518 */ 519 #define CONFIG_SF_DEFAULT_SPEED 10000000 520 #define CONFIG_SF_DEFAULT_MODE 0 521 522 /* 523 * MAPLE 524 */ 525 #ifdef CONFIG_PHYS_64BIT 526 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 527 #else 528 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 529 #endif 530 531 /* 532 * General PCI 533 * Memory space is mapped 1-1, but I/O space must start from 0. 534 */ 535 536 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 537 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 538 #ifdef CONFIG_PHYS_64BIT 539 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 540 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 541 #else 542 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 543 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 544 #endif 545 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 546 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 547 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 548 #ifdef CONFIG_PHYS_64BIT 549 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 550 #else 551 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 552 #endif 553 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 554 555 /* Qman/Bman */ 556 #ifndef CONFIG_NOBQFMAN 557 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 558 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 559 #ifdef CONFIG_PHYS_64BIT 560 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 561 #else 562 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 563 #endif 564 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 565 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 566 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 567 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 568 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 569 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 570 CONFIG_SYS_BMAN_CENA_SIZE) 571 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 572 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 573 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 574 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 575 #ifdef CONFIG_PHYS_64BIT 576 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 577 #else 578 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 579 #endif 580 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 581 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 582 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 583 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 584 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 585 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 586 CONFIG_SYS_QMAN_CENA_SIZE) 587 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 588 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 589 590 #define CONFIG_SYS_DPAA_FMAN 591 592 #define CONFIG_SYS_DPAA_RMAN 593 594 /* Default address of microcode for the Linux Fman driver */ 595 #if defined(CONFIG_SPIFLASH) 596 /* 597 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 598 * env, so we got 0x110000. 599 */ 600 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 601 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 602 #elif defined(CONFIG_SDCARD) 603 /* 604 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 605 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 606 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 607 */ 608 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 609 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 610 #elif defined(CONFIG_NAND) 611 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 612 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 613 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 614 /* 615 * Slave has no ucode locally, it can fetch this from remote. When implementing 616 * in two corenet boards, slave's ucode could be stored in master's memory 617 * space, the address can be mapped from slave TLB->slave LAW-> 618 * slave SRIO or PCIE outbound window->master inbound window-> 619 * master LAW->the ucode address in master's memory space. 620 */ 621 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 622 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 623 #else 624 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 625 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 626 #endif 627 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 628 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 629 #endif /* CONFIG_NOBQFMAN */ 630 631 #ifdef CONFIG_SYS_DPAA_FMAN 632 #define CONFIG_FMAN_ENET 633 #define CONFIG_PHYLIB_10G 634 #define CONFIG_PHY_VITESSE 635 #define CONFIG_PHY_TERANETICS 636 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 637 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 638 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 639 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 640 #endif 641 642 #ifdef CONFIG_PCI 643 #define CONFIG_PCI_INDIRECT_BRIDGE 644 645 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 646 #endif /* CONFIG_PCI */ 647 648 #ifdef CONFIG_FMAN_ENET 649 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 650 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 651 652 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 653 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 654 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 655 656 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 657 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 658 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 659 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 660 661 #define CONFIG_ETHPRIME "FM1@DTSEC1" 662 #endif 663 664 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR 665 666 /* 667 * Environment 668 */ 669 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 670 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 671 672 /* 673 * USB 674 */ 675 #define CONFIG_HAS_FSL_DR_USB 676 677 #ifdef CONFIG_HAS_FSL_DR_USB 678 #ifdef CONFIG_USB_EHCI_HCD 679 #define CONFIG_USB_EHCI_FSL 680 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 681 #endif 682 #endif 683 684 /* 685 * Miscellaneous configurable options 686 */ 687 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 688 689 /* 690 * For booting Linux, the board info and command line data 691 * have to be in the first 64 MB of memory, since this is 692 * the maximum mapped by the Linux kernel during initialization. 693 */ 694 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 695 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 696 697 #ifdef CONFIG_CMD_KGDB 698 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 699 #endif 700 701 /* 702 * Environment Configuration 703 */ 704 #define CONFIG_ROOTPATH "/opt/nfsroot" 705 #define CONFIG_BOOTFILE "uImage" 706 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 707 708 /* default location for tftp and bootm */ 709 #define CONFIG_LOADADDR 1000000 710 711 #define __USB_PHY_TYPE ulpi 712 713 #ifdef CONFIG_ARCH_B4860 714 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 715 "bank_intlv=cs0_cs1;" \ 716 "en_cpc:cpc2;" 717 #else 718 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 719 #endif 720 721 #define CONFIG_EXTRA_ENV_SETTINGS \ 722 HWCONFIG \ 723 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 724 "netdev=eth0\0" \ 725 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 726 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 727 "tftpflash=tftpboot $loadaddr $uboot && " \ 728 "protect off $ubootaddr +$filesize && " \ 729 "erase $ubootaddr +$filesize && " \ 730 "cp.b $loadaddr $ubootaddr $filesize && " \ 731 "protect on $ubootaddr +$filesize && " \ 732 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 733 "consoledev=ttyS0\0" \ 734 "ramdiskaddr=2000000\0" \ 735 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 736 "fdtaddr=1e00000\0" \ 737 "fdtfile=b4860qds/b4860qds.dtb\0" \ 738 "bdev=sda3\0" 739 740 /* For emulation this causes u-boot to jump to the start of the proof point 741 app code automatically */ 742 #define CONFIG_PROOF_POINTS \ 743 "setenv bootargs root=/dev/$bdev rw " \ 744 "console=$consoledev,$baudrate $othbootargs;" \ 745 "cpu 1 release 0x29000000 - - -;" \ 746 "cpu 2 release 0x29000000 - - -;" \ 747 "cpu 3 release 0x29000000 - - -;" \ 748 "cpu 4 release 0x29000000 - - -;" \ 749 "cpu 5 release 0x29000000 - - -;" \ 750 "cpu 6 release 0x29000000 - - -;" \ 751 "cpu 7 release 0x29000000 - - -;" \ 752 "go 0x29000000" 753 754 #define CONFIG_HVBOOT \ 755 "setenv bootargs config-addr=0x60000000; " \ 756 "bootm 0x01000000 - 0x00f00000" 757 758 #define CONFIG_ALU \ 759 "setenv bootargs root=/dev/$bdev rw " \ 760 "console=$consoledev,$baudrate $othbootargs;" \ 761 "cpu 1 release 0x01000000 - - -;" \ 762 "cpu 2 release 0x01000000 - - -;" \ 763 "cpu 3 release 0x01000000 - - -;" \ 764 "cpu 4 release 0x01000000 - - -;" \ 765 "cpu 5 release 0x01000000 - - -;" \ 766 "cpu 6 release 0x01000000 - - -;" \ 767 "cpu 7 release 0x01000000 - - -;" \ 768 "go 0x01000000" 769 770 #define CONFIG_LINUX \ 771 "setenv bootargs root=/dev/ram rw " \ 772 "console=$consoledev,$baudrate $othbootargs;" \ 773 "setenv ramdiskaddr 0x02000000;" \ 774 "setenv fdtaddr 0x01e00000;" \ 775 "setenv loadaddr 0x1000000;" \ 776 "bootm $loadaddr $ramdiskaddr $fdtaddr" 777 778 #define CONFIG_HDBOOT \ 779 "setenv bootargs root=/dev/$bdev rw " \ 780 "console=$consoledev,$baudrate $othbootargs;" \ 781 "tftp $loadaddr $bootfile;" \ 782 "tftp $fdtaddr $fdtfile;" \ 783 "bootm $loadaddr - $fdtaddr" 784 785 #define CONFIG_NFSBOOTCOMMAND \ 786 "setenv bootargs root=/dev/nfs rw " \ 787 "nfsroot=$serverip:$rootpath " \ 788 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 789 "console=$consoledev,$baudrate $othbootargs;" \ 790 "tftp $loadaddr $bootfile;" \ 791 "tftp $fdtaddr $fdtfile;" \ 792 "bootm $loadaddr - $fdtaddr" 793 794 #define CONFIG_RAMBOOTCOMMAND \ 795 "setenv bootargs root=/dev/ram rw " \ 796 "console=$consoledev,$baudrate $othbootargs;" \ 797 "tftp $ramdiskaddr $ramdiskfile;" \ 798 "tftp $loadaddr $bootfile;" \ 799 "tftp $fdtaddr $fdtfile;" \ 800 "bootm $loadaddr $ramdiskaddr $fdtaddr" 801 802 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 803 804 #include <asm/fsl_secure_boot.h> 805 806 #endif /* __CONFIG_H */ 807