1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_SYS_GENERIC_BOARD 11 #define CONFIG_DISPLAY_BOARDINFO 12 13 /* 14 * B4860 QDS board configuration file 15 */ 16 #define CONFIG_B4860QDS 17 #define CONFIG_PHYS_64BIT 18 19 #ifdef CONFIG_RAMBOOT_PBL 20 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 21 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 22 #ifndef CONFIG_NAND 23 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 25 #else 26 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 27 #define CONFIG_SPL_ENV_SUPPORT 28 #define CONFIG_SPL_SERIAL_SUPPORT 29 #define CONFIG_SPL_FLUSH_IMAGE 30 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 31 #define CONFIG_SPL_LIBGENERIC_SUPPORT 32 #define CONFIG_SPL_LIBCOMMON_SUPPORT 33 #define CONFIG_SPL_I2C_SUPPORT 34 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 35 #define CONFIG_FSL_LAW /* Use common FSL init code */ 36 #define CONFIG_SYS_TEXT_BASE 0x00201000 37 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 38 #define CONFIG_SPL_PAD_TO 0x40000 39 #define CONFIG_SPL_MAX_SIZE 0x28000 40 #define RESET_VECTOR_OFFSET 0x27FFC 41 #define BOOT_PAGE_OFFSET 0x27000 42 #define CONFIG_SPL_NAND_SUPPORT 43 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 44 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 45 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 46 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 47 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 48 #define CONFIG_SPL_NAND_BOOT 49 #ifdef CONFIG_SPL_BUILD 50 #define CONFIG_SPL_SKIP_RELOCATE 51 #define CONFIG_SPL_COMMON_INIT_DDR 52 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 53 #define CONFIG_SYS_NO_FLASH 54 #endif 55 #endif 56 #endif 57 58 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 59 /* Set 1M boot space */ 60 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 61 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 62 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 63 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 64 #define CONFIG_SYS_NO_FLASH 65 #endif 66 67 /* High Level Configuration Options */ 68 #define CONFIG_BOOKE 69 #define CONFIG_E500 /* BOOKE e500 family */ 70 #define CONFIG_E500MC /* BOOKE e500mc family */ 71 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 72 #define CONFIG_MP /* support multiple processors */ 73 74 #ifndef CONFIG_SYS_TEXT_BASE 75 #define CONFIG_SYS_TEXT_BASE 0xeff40000 76 #endif 77 78 #ifndef CONFIG_RESET_VECTOR_ADDRESS 79 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 80 #endif 81 82 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 83 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 84 #define CONFIG_FSL_IFC /* Enable IFC Support */ 85 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 86 #define CONFIG_PCI /* Enable PCI/PCIE */ 87 #define CONFIG_PCIE1 /* PCIE controler 1 */ 88 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 89 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 90 91 #ifndef CONFIG_PPC_B4420 92 #define CONFIG_SYS_SRIO 93 #define CONFIG_SRIO1 /* SRIO port 1 */ 94 #define CONFIG_SRIO2 /* SRIO port 2 */ 95 #define CONFIG_SRIO_PCIE_BOOT_MASTER 96 #endif 97 98 #define CONFIG_FSL_LAW /* Use common FSL init code */ 99 100 /* I2C bus multiplexer */ 101 #define I2C_MUX_PCA_ADDR 0x77 102 103 /* VSC Crossbar switches */ 104 #define CONFIG_VSC_CROSSBAR 105 #define I2C_CH_DEFAULT 0x8 106 #define I2C_CH_VSC3316 0xc 107 #define I2C_CH_VSC3308 0xd 108 109 #define VSC3316_TX_ADDRESS 0x70 110 #define VSC3316_RX_ADDRESS 0x71 111 #define VSC3308_TX_ADDRESS 0x02 112 #define VSC3308_RX_ADDRESS 0x03 113 114 /* IDT clock synthesizers */ 115 #define CONFIG_IDT8T49N222A 116 #define I2C_CH_IDT 0x9 117 118 #define IDT_SERDES1_ADDRESS 0x6E 119 #define IDT_SERDES2_ADDRESS 0x6C 120 121 /* Voltage monitor on channel 2*/ 122 #define I2C_MUX_CH_VOL_MONITOR 0xa 123 #define I2C_VOL_MONITOR_ADDR 0x40 124 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 125 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 126 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 127 128 #define CONFIG_ZM7300 129 #define I2C_MUX_CH_DPM 0xa 130 #define I2C_DPM_ADDR 0x28 131 132 #define CONFIG_ENV_OVERWRITE 133 134 #ifdef CONFIG_SYS_NO_FLASH 135 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 136 #define CONFIG_ENV_IS_NOWHERE 137 #endif 138 #else 139 #define CONFIG_FLASH_CFI_DRIVER 140 #define CONFIG_SYS_FLASH_CFI 141 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 142 #endif 143 144 #if defined(CONFIG_SPIFLASH) 145 #define CONFIG_SYS_EXTRA_ENV_RELOC 146 #define CONFIG_ENV_IS_IN_SPI_FLASH 147 #define CONFIG_ENV_SPI_BUS 0 148 #define CONFIG_ENV_SPI_CS 0 149 #define CONFIG_ENV_SPI_MAX_HZ 10000000 150 #define CONFIG_ENV_SPI_MODE 0 151 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 152 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 153 #define CONFIG_ENV_SECT_SIZE 0x10000 154 #elif defined(CONFIG_SDCARD) 155 #define CONFIG_SYS_EXTRA_ENV_RELOC 156 #define CONFIG_ENV_IS_IN_MMC 157 #define CONFIG_SYS_MMC_ENV_DEV 0 158 #define CONFIG_ENV_SIZE 0x2000 159 #define CONFIG_ENV_OFFSET (512 * 1097) 160 #elif defined(CONFIG_NAND) 161 #define CONFIG_SYS_EXTRA_ENV_RELOC 162 #define CONFIG_ENV_IS_IN_NAND 163 #define CONFIG_ENV_SIZE 0x2000 164 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 165 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 166 #define CONFIG_ENV_IS_IN_REMOTE 167 #define CONFIG_ENV_ADDR 0xffe20000 168 #define CONFIG_ENV_SIZE 0x2000 169 #elif defined(CONFIG_ENV_IS_NOWHERE) 170 #define CONFIG_ENV_SIZE 0x2000 171 #else 172 #define CONFIG_ENV_IS_IN_FLASH 173 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 174 #define CONFIG_ENV_SIZE 0x2000 175 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 176 #endif 177 178 #ifndef __ASSEMBLY__ 179 unsigned long get_board_sys_clk(void); 180 unsigned long get_board_ddr_clk(void); 181 #endif 182 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 183 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 184 185 /* 186 * These can be toggled for performance analysis, otherwise use default. 187 */ 188 #define CONFIG_SYS_CACHE_STASHING 189 #define CONFIG_BTB /* toggle branch predition */ 190 #define CONFIG_DDR_ECC 191 #ifdef CONFIG_DDR_ECC 192 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 193 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 194 #endif 195 196 #define CONFIG_ENABLE_36BIT_PHYS 197 198 #ifdef CONFIG_PHYS_64BIT 199 #define CONFIG_ADDR_MAP 200 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 201 #endif 202 203 #if 0 204 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 205 #endif 206 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 207 #define CONFIG_SYS_MEMTEST_END 0x00400000 208 #define CONFIG_SYS_ALT_MEMTEST 209 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 210 211 /* 212 * Config the L3 Cache as L3 SRAM 213 */ 214 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 215 #define CONFIG_SYS_L3_SIZE 256 << 10 216 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 217 #ifdef CONFIG_NAND 218 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 219 #endif 220 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 221 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 222 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 223 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 224 225 #ifdef CONFIG_PHYS_64BIT 226 #define CONFIG_SYS_DCSRBAR 0xf0000000 227 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 228 #endif 229 230 /* EEPROM */ 231 #define CONFIG_ID_EEPROM 232 #define CONFIG_SYS_I2C_EEPROM_NXID 233 #define CONFIG_SYS_EEPROM_BUS_NUM 0 234 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 235 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 236 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 237 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 238 239 /* 240 * DDR Setup 241 */ 242 #define CONFIG_VERY_BIG_RAM 243 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 244 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 245 246 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 247 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 248 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 249 250 #define CONFIG_DDR_SPD 251 #define CONFIG_SYS_DDR_RAW_TIMING 252 #define CONFIG_SYS_FSL_DDR3 253 #ifndef CONFIG_SPL_BUILD 254 #define CONFIG_FSL_DDR_INTERACTIVE 255 #endif 256 257 #define CONFIG_SYS_SPD_BUS_NUM 0 258 #define SPD_EEPROM_ADDRESS1 0x51 259 #define SPD_EEPROM_ADDRESS2 0x53 260 261 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 262 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 263 264 /* 265 * IFC Definitions 266 */ 267 #define CONFIG_SYS_FLASH_BASE 0xe0000000 268 #ifdef CONFIG_PHYS_64BIT 269 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 270 #else 271 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 272 #endif 273 274 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 275 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 276 + 0x8000000) | \ 277 CSPR_PORT_SIZE_16 | \ 278 CSPR_MSEL_NOR | \ 279 CSPR_V) 280 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 281 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 282 CSPR_PORT_SIZE_16 | \ 283 CSPR_MSEL_NOR | \ 284 CSPR_V) 285 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 286 /* NOR Flash Timing Params */ 287 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 288 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 289 FTIM0_NOR_TEADC(0x04) | \ 290 FTIM0_NOR_TEAHC(0x20)) 291 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 292 FTIM1_NOR_TRAD_NOR(0x1A) |\ 293 FTIM1_NOR_TSEQRAD_NOR(0x13)) 294 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 295 FTIM2_NOR_TCH(0x0E) | \ 296 FTIM2_NOR_TWPH(0x0E) | \ 297 FTIM2_NOR_TWP(0x1c)) 298 #define CONFIG_SYS_NOR_FTIM3 0x0 299 300 #define CONFIG_SYS_FLASH_QUIET_TEST 301 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 302 303 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 304 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 305 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 306 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 307 308 #define CONFIG_SYS_FLASH_EMPTY_INFO 309 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 310 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 311 312 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 313 #define CONFIG_FSL_QIXIS_V2 314 #define QIXIS_BASE 0xffdf0000 315 #ifdef CONFIG_PHYS_64BIT 316 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 317 #else 318 #define QIXIS_BASE_PHYS QIXIS_BASE 319 #endif 320 #define QIXIS_LBMAP_SWITCH 0x01 321 #define QIXIS_LBMAP_MASK 0x0f 322 #define QIXIS_LBMAP_SHIFT 0 323 #define QIXIS_LBMAP_DFLTBANK 0x00 324 #define QIXIS_LBMAP_ALTBANK 0x02 325 #define QIXIS_RST_CTL_RESET 0x31 326 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 327 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 328 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 329 330 #define CONFIG_SYS_CSPR3_EXT (0xf) 331 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 332 | CSPR_PORT_SIZE_8 \ 333 | CSPR_MSEL_GPCM \ 334 | CSPR_V) 335 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 336 #define CONFIG_SYS_CSOR3 0x0 337 /* QIXIS Timing parameters for IFC CS3 */ 338 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 339 FTIM0_GPCM_TEADC(0x0e) | \ 340 FTIM0_GPCM_TEAHC(0x0e)) 341 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 342 FTIM1_GPCM_TRAD(0x1f)) 343 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 344 FTIM2_GPCM_TCH(0x8) | \ 345 FTIM2_GPCM_TWP(0x1f)) 346 #define CONFIG_SYS_CS3_FTIM3 0x0 347 348 /* NAND Flash on IFC */ 349 #define CONFIG_NAND_FSL_IFC 350 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 351 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 352 #define CONFIG_SYS_NAND_BASE 0xff800000 353 #ifdef CONFIG_PHYS_64BIT 354 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 355 #else 356 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 357 #endif 358 359 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 360 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 361 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 362 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 363 | CSPR_V) 364 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 365 366 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 367 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 368 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 369 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 370 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 371 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 372 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 373 374 #define CONFIG_SYS_NAND_ONFI_DETECTION 375 376 /* ONFI NAND Flash mode0 Timing Params */ 377 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 378 FTIM0_NAND_TWP(0x18) | \ 379 FTIM0_NAND_TWCHT(0x07) | \ 380 FTIM0_NAND_TWH(0x0a)) 381 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 382 FTIM1_NAND_TWBE(0x39) | \ 383 FTIM1_NAND_TRR(0x0e) | \ 384 FTIM1_NAND_TRP(0x18)) 385 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 386 FTIM2_NAND_TREH(0x0a) | \ 387 FTIM2_NAND_TWHRE(0x1e)) 388 #define CONFIG_SYS_NAND_FTIM3 0x0 389 390 #define CONFIG_SYS_NAND_DDR_LAW 11 391 392 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 393 #define CONFIG_SYS_MAX_NAND_DEVICE 1 394 #define CONFIG_CMD_NAND 395 396 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 397 398 #if defined(CONFIG_NAND) 399 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 400 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 401 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 402 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 403 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 404 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 405 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 406 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 407 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 408 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 409 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 410 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 411 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 412 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 413 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 414 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 415 #else 416 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 417 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 418 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 419 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 420 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 421 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 422 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 423 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 424 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 425 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 426 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 427 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 428 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 429 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 430 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 431 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 432 #endif 433 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 434 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 435 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 436 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 437 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 438 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 439 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 440 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 441 442 #ifdef CONFIG_SPL_BUILD 443 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 444 #else 445 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 446 #endif 447 448 #if defined(CONFIG_RAMBOOT_PBL) 449 #define CONFIG_SYS_RAMBOOT 450 #endif 451 452 #define CONFIG_BOARD_EARLY_INIT_R 453 #define CONFIG_MISC_INIT_R 454 455 #define CONFIG_HWCONFIG 456 457 /* define to use L1 as initial stack */ 458 #define CONFIG_L1_INIT_RAM 459 #define CONFIG_SYS_INIT_RAM_LOCK 460 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 461 #ifdef CONFIG_PHYS_64BIT 462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 464 /* The assembler doesn't like typecast */ 465 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 466 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 467 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 468 #else 469 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 472 #endif 473 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 474 475 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 476 GENERATED_GBL_DATA_SIZE) 477 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 478 479 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 480 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 481 482 /* Serial Port - controlled on board with jumper J8 483 * open - index 2 484 * shorted - index 1 485 */ 486 #define CONFIG_CONS_INDEX 1 487 #define CONFIG_SYS_NS16550 488 #define CONFIG_SYS_NS16550_SERIAL 489 #define CONFIG_SYS_NS16550_REG_SIZE 1 490 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 491 492 #define CONFIG_SYS_BAUDRATE_TABLE \ 493 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 494 495 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 496 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 497 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 498 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 499 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 500 #ifndef CONFIG_SPL_BUILD 501 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 502 #endif 503 504 505 /* Use the HUSH parser */ 506 #define CONFIG_SYS_HUSH_PARSER 507 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 508 509 /* pass open firmware flat tree */ 510 #define CONFIG_OF_LIBFDT 511 #define CONFIG_OF_BOARD_SETUP 512 #define CONFIG_OF_STDOUT_VIA_ALIAS 513 514 /* new uImage format support */ 515 #define CONFIG_FIT 516 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 517 518 /* I2C */ 519 #define CONFIG_SYS_I2C 520 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 521 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 522 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 523 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 524 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 525 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 526 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 527 528 /* 529 * RTC configuration 530 */ 531 #define RTC 532 #define CONFIG_RTC_DS3231 1 533 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 534 535 /* 536 * RapidIO 537 */ 538 #ifdef CONFIG_SYS_SRIO 539 #ifdef CONFIG_SRIO1 540 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 541 #ifdef CONFIG_PHYS_64BIT 542 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 543 #else 544 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 545 #endif 546 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 547 #endif 548 549 #ifdef CONFIG_SRIO2 550 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 551 #ifdef CONFIG_PHYS_64BIT 552 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 553 #else 554 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 555 #endif 556 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 557 #endif 558 #endif 559 560 /* 561 * for slave u-boot IMAGE instored in master memory space, 562 * PHYS must be aligned based on the SIZE 563 */ 564 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 565 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 566 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 567 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 568 /* 569 * for slave UCODE and ENV instored in master memory space, 570 * PHYS must be aligned based on the SIZE 571 */ 572 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 573 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 574 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 575 576 /* slave core release by master*/ 577 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 578 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 579 580 /* 581 * SRIO_PCIE_BOOT - SLAVE 582 */ 583 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 584 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 585 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 586 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 587 #endif 588 589 /* 590 * eSPI - Enhanced SPI 591 */ 592 #define CONFIG_FSL_ESPI 593 #define CONFIG_SPI_FLASH 594 #define CONFIG_SPI_FLASH_SST 595 #define CONFIG_CMD_SF 596 #define CONFIG_SF_DEFAULT_SPEED 10000000 597 #define CONFIG_SF_DEFAULT_MODE 0 598 599 /* 600 * MAPLE 601 */ 602 #ifdef CONFIG_PHYS_64BIT 603 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 604 #else 605 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 606 #endif 607 608 /* 609 * General PCI 610 * Memory space is mapped 1-1, but I/O space must start from 0. 611 */ 612 613 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 614 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 615 #ifdef CONFIG_PHYS_64BIT 616 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 617 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 618 #else 619 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 620 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 621 #endif 622 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 623 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 624 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 625 #ifdef CONFIG_PHYS_64BIT 626 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 627 #else 628 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 629 #endif 630 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 631 632 /* Qman/Bman */ 633 #ifndef CONFIG_NOBQFMAN 634 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 635 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 636 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 637 #ifdef CONFIG_PHYS_64BIT 638 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 639 #else 640 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 641 #endif 642 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 643 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 644 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 645 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 646 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 647 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 648 CONFIG_SYS_BMAN_CENA_SIZE) 649 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 650 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 651 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 652 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 653 #ifdef CONFIG_PHYS_64BIT 654 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 655 #else 656 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 657 #endif 658 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 659 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 660 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 661 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 662 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 663 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 664 CONFIG_SYS_QMAN_CENA_SIZE) 665 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 666 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 667 668 #define CONFIG_SYS_DPAA_FMAN 669 670 #define CONFIG_SYS_DPAA_RMAN 671 672 /* Default address of microcode for the Linux Fman driver */ 673 #if defined(CONFIG_SPIFLASH) 674 /* 675 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 676 * env, so we got 0x110000. 677 */ 678 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 679 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 680 #elif defined(CONFIG_SDCARD) 681 /* 682 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 683 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 684 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 685 */ 686 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 687 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 688 #elif defined(CONFIG_NAND) 689 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 690 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 691 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 692 /* 693 * Slave has no ucode locally, it can fetch this from remote. When implementing 694 * in two corenet boards, slave's ucode could be stored in master's memory 695 * space, the address can be mapped from slave TLB->slave LAW-> 696 * slave SRIO or PCIE outbound window->master inbound window-> 697 * master LAW->the ucode address in master's memory space. 698 */ 699 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 700 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 701 #else 702 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 703 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 704 #endif 705 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 706 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 707 #endif /* CONFIG_NOBQFMAN */ 708 709 #ifdef CONFIG_SYS_DPAA_FMAN 710 #define CONFIG_FMAN_ENET 711 #define CONFIG_PHYLIB_10G 712 #define CONFIG_PHY_VITESSE 713 #define CONFIG_PHY_TERANETICS 714 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 715 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 716 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 717 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 718 #endif 719 720 #ifdef CONFIG_PCI 721 #define CONFIG_PCI_INDIRECT_BRIDGE 722 #define CONFIG_NET_MULTI 723 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 724 #define CONFIG_E1000 725 726 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 727 #define CONFIG_DOS_PARTITION 728 #endif /* CONFIG_PCI */ 729 730 #ifdef CONFIG_FMAN_ENET 731 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 732 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 733 734 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 735 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 736 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 737 738 739 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 740 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 741 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 742 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 743 744 #define CONFIG_MII /* MII PHY management */ 745 #define CONFIG_ETHPRIME "FM1@DTSEC1" 746 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 747 #endif 748 749 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR 750 751 /* 752 * Environment 753 */ 754 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 755 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 756 757 /* 758 * Command line configuration. 759 */ 760 #include <config_cmd_default.h> 761 762 #define CONFIG_CMD_DATE 763 #define CONFIG_CMD_DHCP 764 #define CONFIG_CMD_EEPROM 765 #define CONFIG_CMD_ELF 766 #define CONFIG_CMD_ERRATA 767 #define CONFIG_CMD_GREPENV 768 #define CONFIG_CMD_IRQ 769 #define CONFIG_CMD_I2C 770 #define CONFIG_CMD_MII 771 #define CONFIG_CMD_PING 772 #define CONFIG_CMD_REGINFO 773 #define CONFIG_CMD_SETEXPR 774 775 #ifdef CONFIG_PCI 776 #define CONFIG_CMD_PCI 777 #define CONFIG_CMD_NET 778 #endif 779 780 /* Hash command with SHA acceleration supported in hardware */ 781 #ifdef CONFIG_FSL_CAAM 782 #define CONFIG_CMD_HASH 783 #define CONFIG_SHA_HW_ACCEL 784 #endif 785 786 /* 787 * USB 788 */ 789 #define CONFIG_HAS_FSL_DR_USB 790 791 #ifdef CONFIG_HAS_FSL_DR_USB 792 #define CONFIG_USB_EHCI 793 794 #ifdef CONFIG_USB_EHCI 795 #define CONFIG_CMD_USB 796 #define CONFIG_USB_STORAGE 797 #define CONFIG_USB_EHCI_FSL 798 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 799 #define CONFIG_CMD_EXT2 800 #endif 801 #endif 802 803 /* 804 * Miscellaneous configurable options 805 */ 806 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 807 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 808 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 809 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 810 #ifdef CONFIG_CMD_KGDB 811 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 812 #else 813 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 814 #endif 815 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 816 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 817 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 818 819 /* 820 * For booting Linux, the board info and command line data 821 * have to be in the first 64 MB of memory, since this is 822 * the maximum mapped by the Linux kernel during initialization. 823 */ 824 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 825 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 826 827 #ifdef CONFIG_CMD_KGDB 828 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 829 #endif 830 831 /* 832 * Environment Configuration 833 */ 834 #define CONFIG_ROOTPATH "/opt/nfsroot" 835 #define CONFIG_BOOTFILE "uImage" 836 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 837 838 /* default location for tftp and bootm */ 839 #define CONFIG_LOADADDR 1000000 840 841 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 842 843 #define CONFIG_BAUDRATE 115200 844 845 #define __USB_PHY_TYPE ulpi 846 847 #ifdef CONFIG_PPC_B4860 848 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 849 "bank_intlv=cs0_cs1;" \ 850 "en_cpc:cpc2;" 851 #else 852 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 853 #endif 854 855 #define CONFIG_EXTRA_ENV_SETTINGS \ 856 HWCONFIG \ 857 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 858 "netdev=eth0\0" \ 859 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 860 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 861 "tftpflash=tftpboot $loadaddr $uboot && " \ 862 "protect off $ubootaddr +$filesize && " \ 863 "erase $ubootaddr +$filesize && " \ 864 "cp.b $loadaddr $ubootaddr $filesize && " \ 865 "protect on $ubootaddr +$filesize && " \ 866 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 867 "consoledev=ttyS0\0" \ 868 "ramdiskaddr=2000000\0" \ 869 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 870 "fdtaddr=c00000\0" \ 871 "fdtfile=b4860qds/b4860qds.dtb\0" \ 872 "bdev=sda3\0" 873 874 /* For emulation this causes u-boot to jump to the start of the proof point 875 app code automatically */ 876 #define CONFIG_PROOF_POINTS \ 877 "setenv bootargs root=/dev/$bdev rw " \ 878 "console=$consoledev,$baudrate $othbootargs;" \ 879 "cpu 1 release 0x29000000 - - -;" \ 880 "cpu 2 release 0x29000000 - - -;" \ 881 "cpu 3 release 0x29000000 - - -;" \ 882 "cpu 4 release 0x29000000 - - -;" \ 883 "cpu 5 release 0x29000000 - - -;" \ 884 "cpu 6 release 0x29000000 - - -;" \ 885 "cpu 7 release 0x29000000 - - -;" \ 886 "go 0x29000000" 887 888 #define CONFIG_HVBOOT \ 889 "setenv bootargs config-addr=0x60000000; " \ 890 "bootm 0x01000000 - 0x00f00000" 891 892 #define CONFIG_ALU \ 893 "setenv bootargs root=/dev/$bdev rw " \ 894 "console=$consoledev,$baudrate $othbootargs;" \ 895 "cpu 1 release 0x01000000 - - -;" \ 896 "cpu 2 release 0x01000000 - - -;" \ 897 "cpu 3 release 0x01000000 - - -;" \ 898 "cpu 4 release 0x01000000 - - -;" \ 899 "cpu 5 release 0x01000000 - - -;" \ 900 "cpu 6 release 0x01000000 - - -;" \ 901 "cpu 7 release 0x01000000 - - -;" \ 902 "go 0x01000000" 903 904 #define CONFIG_LINUX \ 905 "setenv bootargs root=/dev/ram rw " \ 906 "console=$consoledev,$baudrate $othbootargs;" \ 907 "setenv ramdiskaddr 0x02000000;" \ 908 "setenv fdtaddr 0x00c00000;" \ 909 "setenv loadaddr 0x1000000;" \ 910 "bootm $loadaddr $ramdiskaddr $fdtaddr" 911 912 #define CONFIG_HDBOOT \ 913 "setenv bootargs root=/dev/$bdev rw " \ 914 "console=$consoledev,$baudrate $othbootargs;" \ 915 "tftp $loadaddr $bootfile;" \ 916 "tftp $fdtaddr $fdtfile;" \ 917 "bootm $loadaddr - $fdtaddr" 918 919 #define CONFIG_NFSBOOTCOMMAND \ 920 "setenv bootargs root=/dev/nfs rw " \ 921 "nfsroot=$serverip:$rootpath " \ 922 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 923 "console=$consoledev,$baudrate $othbootargs;" \ 924 "tftp $loadaddr $bootfile;" \ 925 "tftp $fdtaddr $fdtfile;" \ 926 "bootm $loadaddr - $fdtaddr" 927 928 #define CONFIG_RAMBOOTCOMMAND \ 929 "setenv bootargs root=/dev/ram rw " \ 930 "console=$consoledev,$baudrate $othbootargs;" \ 931 "tftp $ramdiskaddr $ramdiskfile;" \ 932 "tftp $loadaddr $bootfile;" \ 933 "tftp $fdtaddr $fdtfile;" \ 934 "bootm $loadaddr $ramdiskaddr $fdtaddr" 935 936 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 937 938 #include <asm/fsl_secure_boot.h> 939 940 #ifdef CONFIG_SECURE_BOOT 941 #define CONFIG_CMD_BLOB 942 #endif 943 944 #endif /* __CONFIG_H */ 945