1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * B4860 QDS board configuration file 12 */ 13 #ifdef CONFIG_RAMBOOT_PBL 14 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 15 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 16 #ifndef CONFIG_NAND 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #else 20 #define CONFIG_SPL_FLUSH_IMAGE 21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 22 #define CONFIG_SYS_TEXT_BASE 0x00201000 23 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 24 #define CONFIG_SPL_PAD_TO 0x40000 25 #define CONFIG_SPL_MAX_SIZE 0x28000 26 #define RESET_VECTOR_OFFSET 0x27FFC 27 #define BOOT_PAGE_OFFSET 0x27000 28 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 29 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 30 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 31 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 32 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 33 #define CONFIG_SPL_NAND_BOOT 34 #ifdef CONFIG_SPL_BUILD 35 #define CONFIG_SPL_SKIP_RELOCATE 36 #define CONFIG_SPL_COMMON_INIT_DDR 37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 38 #endif 39 #endif 40 #endif 41 42 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 43 /* Set 1M boot space */ 44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 45 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 46 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 47 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 48 #endif 49 50 /* High Level Configuration Options */ 51 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 52 #define CONFIG_MP /* support multiple processors */ 53 54 #ifndef CONFIG_SYS_TEXT_BASE 55 #define CONFIG_SYS_TEXT_BASE 0xeff40000 56 #endif 57 58 #ifndef CONFIG_RESET_VECTOR_ADDRESS 59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 60 #endif 61 62 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 63 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 64 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 65 #define CONFIG_PCIE1 /* PCIE controller 1 */ 66 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 67 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 68 69 #ifndef CONFIG_ARCH_B4420 70 #define CONFIG_SYS_SRIO 71 #define CONFIG_SRIO1 /* SRIO port 1 */ 72 #define CONFIG_SRIO2 /* SRIO port 2 */ 73 #define CONFIG_SRIO_PCIE_BOOT_MASTER 74 #endif 75 76 /* I2C bus multiplexer */ 77 #define I2C_MUX_PCA_ADDR 0x77 78 79 /* VSC Crossbar switches */ 80 #define CONFIG_VSC_CROSSBAR 81 #define I2C_CH_DEFAULT 0x8 82 #define I2C_CH_VSC3316 0xc 83 #define I2C_CH_VSC3308 0xd 84 85 #define VSC3316_TX_ADDRESS 0x70 86 #define VSC3316_RX_ADDRESS 0x71 87 #define VSC3308_TX_ADDRESS 0x02 88 #define VSC3308_RX_ADDRESS 0x03 89 90 /* IDT clock synthesizers */ 91 #define CONFIG_IDT8T49N222A 92 #define I2C_CH_IDT 0x9 93 94 #define IDT_SERDES1_ADDRESS 0x6E 95 #define IDT_SERDES2_ADDRESS 0x6C 96 97 /* Voltage monitor on channel 2*/ 98 #define I2C_MUX_CH_VOL_MONITOR 0xa 99 #define I2C_VOL_MONITOR_ADDR 0x40 100 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 101 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 102 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 103 104 #define CONFIG_ZM7300 105 #define I2C_MUX_CH_DPM 0xa 106 #define I2C_DPM_ADDR 0x28 107 108 #define CONFIG_ENV_OVERWRITE 109 110 #ifndef CONFIG_MTD_NOR_FLASH 111 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 112 #define CONFIG_ENV_IS_NOWHERE 113 #endif 114 #else 115 #define CONFIG_FLASH_CFI_DRIVER 116 #define CONFIG_SYS_FLASH_CFI 117 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 118 #endif 119 120 #if defined(CONFIG_SPIFLASH) 121 #define CONFIG_SYS_EXTRA_ENV_RELOC 122 #define CONFIG_ENV_IS_IN_SPI_FLASH 123 #define CONFIG_ENV_SPI_BUS 0 124 #define CONFIG_ENV_SPI_CS 0 125 #define CONFIG_ENV_SPI_MAX_HZ 10000000 126 #define CONFIG_ENV_SPI_MODE 0 127 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 128 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 129 #define CONFIG_ENV_SECT_SIZE 0x10000 130 #elif defined(CONFIG_SDCARD) 131 #define CONFIG_SYS_EXTRA_ENV_RELOC 132 #define CONFIG_ENV_IS_IN_MMC 133 #define CONFIG_SYS_MMC_ENV_DEV 0 134 #define CONFIG_ENV_SIZE 0x2000 135 #define CONFIG_ENV_OFFSET (512 * 1097) 136 #elif defined(CONFIG_NAND) 137 #define CONFIG_SYS_EXTRA_ENV_RELOC 138 #define CONFIG_ENV_IS_IN_NAND 139 #define CONFIG_ENV_SIZE 0x2000 140 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 141 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 142 #define CONFIG_ENV_IS_IN_REMOTE 143 #define CONFIG_ENV_ADDR 0xffe20000 144 #define CONFIG_ENV_SIZE 0x2000 145 #elif defined(CONFIG_ENV_IS_NOWHERE) 146 #define CONFIG_ENV_SIZE 0x2000 147 #else 148 #define CONFIG_ENV_IS_IN_FLASH 149 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 150 #define CONFIG_ENV_SIZE 0x2000 151 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 152 #endif 153 154 #ifndef __ASSEMBLY__ 155 unsigned long get_board_sys_clk(void); 156 unsigned long get_board_ddr_clk(void); 157 #endif 158 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 159 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 160 161 /* 162 * These can be toggled for performance analysis, otherwise use default. 163 */ 164 #define CONFIG_SYS_CACHE_STASHING 165 #define CONFIG_BTB /* toggle branch predition */ 166 #define CONFIG_DDR_ECC 167 #ifdef CONFIG_DDR_ECC 168 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 169 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 170 #endif 171 172 #define CONFIG_ENABLE_36BIT_PHYS 173 174 #ifdef CONFIG_PHYS_64BIT 175 #define CONFIG_ADDR_MAP 176 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 177 #endif 178 179 #if 0 180 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 181 #endif 182 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 183 #define CONFIG_SYS_MEMTEST_END 0x00400000 184 #define CONFIG_SYS_ALT_MEMTEST 185 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 186 187 /* 188 * Config the L3 Cache as L3 SRAM 189 */ 190 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 191 #define CONFIG_SYS_L3_SIZE 256 << 10 192 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 193 #ifdef CONFIG_NAND 194 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 195 #endif 196 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 197 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 198 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 199 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 200 201 #ifdef CONFIG_PHYS_64BIT 202 #define CONFIG_SYS_DCSRBAR 0xf0000000 203 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 204 #endif 205 206 /* EEPROM */ 207 #define CONFIG_ID_EEPROM 208 #define CONFIG_SYS_I2C_EEPROM_NXID 209 #define CONFIG_SYS_EEPROM_BUS_NUM 0 210 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 211 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 212 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 213 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 214 215 /* 216 * DDR Setup 217 */ 218 #define CONFIG_VERY_BIG_RAM 219 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 220 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 221 222 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 223 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 224 225 #define CONFIG_DDR_SPD 226 #define CONFIG_SYS_DDR_RAW_TIMING 227 #ifndef CONFIG_SPL_BUILD 228 #define CONFIG_FSL_DDR_INTERACTIVE 229 #endif 230 231 #define CONFIG_SYS_SPD_BUS_NUM 0 232 #define SPD_EEPROM_ADDRESS1 0x51 233 #define SPD_EEPROM_ADDRESS2 0x53 234 235 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 236 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 237 238 /* 239 * IFC Definitions 240 */ 241 #define CONFIG_SYS_FLASH_BASE 0xe0000000 242 #ifdef CONFIG_PHYS_64BIT 243 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 244 #else 245 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 246 #endif 247 248 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 249 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 250 + 0x8000000) | \ 251 CSPR_PORT_SIZE_16 | \ 252 CSPR_MSEL_NOR | \ 253 CSPR_V) 254 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 255 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 256 CSPR_PORT_SIZE_16 | \ 257 CSPR_MSEL_NOR | \ 258 CSPR_V) 259 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 260 /* NOR Flash Timing Params */ 261 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 262 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 263 FTIM0_NOR_TEADC(0x04) | \ 264 FTIM0_NOR_TEAHC(0x20)) 265 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 266 FTIM1_NOR_TRAD_NOR(0x1A) |\ 267 FTIM1_NOR_TSEQRAD_NOR(0x13)) 268 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 269 FTIM2_NOR_TCH(0x0E) | \ 270 FTIM2_NOR_TWPH(0x0E) | \ 271 FTIM2_NOR_TWP(0x1c)) 272 #define CONFIG_SYS_NOR_FTIM3 0x0 273 274 #define CONFIG_SYS_FLASH_QUIET_TEST 275 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 276 277 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 278 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 279 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 280 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 281 282 #define CONFIG_SYS_FLASH_EMPTY_INFO 283 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 284 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 285 286 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 287 #define CONFIG_FSL_QIXIS_V2 288 #define QIXIS_BASE 0xffdf0000 289 #ifdef CONFIG_PHYS_64BIT 290 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 291 #else 292 #define QIXIS_BASE_PHYS QIXIS_BASE 293 #endif 294 #define QIXIS_LBMAP_SWITCH 0x01 295 #define QIXIS_LBMAP_MASK 0x0f 296 #define QIXIS_LBMAP_SHIFT 0 297 #define QIXIS_LBMAP_DFLTBANK 0x00 298 #define QIXIS_LBMAP_ALTBANK 0x02 299 #define QIXIS_RST_CTL_RESET 0x31 300 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 301 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 302 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 303 304 #define CONFIG_SYS_CSPR3_EXT (0xf) 305 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 306 | CSPR_PORT_SIZE_8 \ 307 | CSPR_MSEL_GPCM \ 308 | CSPR_V) 309 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 310 #define CONFIG_SYS_CSOR3 0x0 311 /* QIXIS Timing parameters for IFC CS3 */ 312 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 313 FTIM0_GPCM_TEADC(0x0e) | \ 314 FTIM0_GPCM_TEAHC(0x0e)) 315 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 316 FTIM1_GPCM_TRAD(0x1f)) 317 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 318 FTIM2_GPCM_TCH(0x8) | \ 319 FTIM2_GPCM_TWP(0x1f)) 320 #define CONFIG_SYS_CS3_FTIM3 0x0 321 322 /* NAND Flash on IFC */ 323 #define CONFIG_NAND_FSL_IFC 324 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 325 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 326 #define CONFIG_SYS_NAND_BASE 0xff800000 327 #ifdef CONFIG_PHYS_64BIT 328 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 329 #else 330 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 331 #endif 332 333 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 334 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 335 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 336 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 337 | CSPR_V) 338 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 339 340 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 341 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 342 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 343 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 344 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 345 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 346 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 347 348 #define CONFIG_SYS_NAND_ONFI_DETECTION 349 350 /* ONFI NAND Flash mode0 Timing Params */ 351 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 352 FTIM0_NAND_TWP(0x18) | \ 353 FTIM0_NAND_TWCHT(0x07) | \ 354 FTIM0_NAND_TWH(0x0a)) 355 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 356 FTIM1_NAND_TWBE(0x39) | \ 357 FTIM1_NAND_TRR(0x0e) | \ 358 FTIM1_NAND_TRP(0x18)) 359 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 360 FTIM2_NAND_TREH(0x0a) | \ 361 FTIM2_NAND_TWHRE(0x1e)) 362 #define CONFIG_SYS_NAND_FTIM3 0x0 363 364 #define CONFIG_SYS_NAND_DDR_LAW 11 365 366 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 367 #define CONFIG_SYS_MAX_NAND_DEVICE 1 368 #define CONFIG_CMD_NAND 369 370 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 371 372 #if defined(CONFIG_NAND) 373 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 374 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 375 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 376 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 377 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 378 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 379 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 380 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 381 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 382 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 383 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 384 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 385 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 386 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 387 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 388 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 389 #else 390 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 391 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 392 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 393 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 394 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 395 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 396 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 397 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 398 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 399 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 400 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 401 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 402 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 403 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 404 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 405 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 406 #endif 407 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 408 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 409 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 410 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 411 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 412 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 413 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 414 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 415 416 #ifdef CONFIG_SPL_BUILD 417 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 418 #else 419 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 420 #endif 421 422 #if defined(CONFIG_RAMBOOT_PBL) 423 #define CONFIG_SYS_RAMBOOT 424 #endif 425 426 #define CONFIG_BOARD_EARLY_INIT_R 427 #define CONFIG_MISC_INIT_R 428 429 #define CONFIG_HWCONFIG 430 431 /* define to use L1 as initial stack */ 432 #define CONFIG_L1_INIT_RAM 433 #define CONFIG_SYS_INIT_RAM_LOCK 434 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 435 #ifdef CONFIG_PHYS_64BIT 436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 437 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 438 /* The assembler doesn't like typecast */ 439 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 440 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 441 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 442 #else 443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 444 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 446 #endif 447 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 448 449 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 450 GENERATED_GBL_DATA_SIZE) 451 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 452 453 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 454 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 455 456 /* Serial Port - controlled on board with jumper J8 457 * open - index 2 458 * shorted - index 1 459 */ 460 #define CONFIG_CONS_INDEX 1 461 #define CONFIG_SYS_NS16550_SERIAL 462 #define CONFIG_SYS_NS16550_REG_SIZE 1 463 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 464 465 #define CONFIG_SYS_BAUDRATE_TABLE \ 466 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 467 468 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 469 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 470 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 471 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 472 473 /* I2C */ 474 #define CONFIG_SYS_I2C 475 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 476 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 477 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 478 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 479 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 480 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 481 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 482 483 /* 484 * RTC configuration 485 */ 486 #define RTC 487 #define CONFIG_RTC_DS3231 1 488 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 489 490 /* 491 * RapidIO 492 */ 493 #ifdef CONFIG_SYS_SRIO 494 #ifdef CONFIG_SRIO1 495 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 496 #ifdef CONFIG_PHYS_64BIT 497 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 498 #else 499 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 500 #endif 501 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 502 #endif 503 504 #ifdef CONFIG_SRIO2 505 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 506 #ifdef CONFIG_PHYS_64BIT 507 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 508 #else 509 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 510 #endif 511 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 512 #endif 513 #endif 514 515 /* 516 * for slave u-boot IMAGE instored in master memory space, 517 * PHYS must be aligned based on the SIZE 518 */ 519 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 520 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 521 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 522 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 523 /* 524 * for slave UCODE and ENV instored in master memory space, 525 * PHYS must be aligned based on the SIZE 526 */ 527 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 528 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 529 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 530 531 /* slave core release by master*/ 532 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 533 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 534 535 /* 536 * SRIO_PCIE_BOOT - SLAVE 537 */ 538 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 539 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 540 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 541 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 542 #endif 543 544 /* 545 * eSPI - Enhanced SPI 546 */ 547 #define CONFIG_SF_DEFAULT_SPEED 10000000 548 #define CONFIG_SF_DEFAULT_MODE 0 549 550 /* 551 * MAPLE 552 */ 553 #ifdef CONFIG_PHYS_64BIT 554 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 555 #else 556 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 557 #endif 558 559 /* 560 * General PCI 561 * Memory space is mapped 1-1, but I/O space must start from 0. 562 */ 563 564 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 565 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 566 #ifdef CONFIG_PHYS_64BIT 567 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 568 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 569 #else 570 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 571 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 572 #endif 573 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 574 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 575 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 576 #ifdef CONFIG_PHYS_64BIT 577 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 578 #else 579 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 580 #endif 581 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 582 583 /* Qman/Bman */ 584 #ifndef CONFIG_NOBQFMAN 585 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 586 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 587 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 588 #ifdef CONFIG_PHYS_64BIT 589 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 590 #else 591 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 592 #endif 593 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 594 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 595 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 596 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 597 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 598 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 599 CONFIG_SYS_BMAN_CENA_SIZE) 600 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 601 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 602 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 603 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 604 #ifdef CONFIG_PHYS_64BIT 605 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 606 #else 607 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 608 #endif 609 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 610 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 611 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 612 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 613 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 614 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 615 CONFIG_SYS_QMAN_CENA_SIZE) 616 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 617 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 618 619 #define CONFIG_SYS_DPAA_FMAN 620 621 #define CONFIG_SYS_DPAA_RMAN 622 623 /* Default address of microcode for the Linux Fman driver */ 624 #if defined(CONFIG_SPIFLASH) 625 /* 626 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 627 * env, so we got 0x110000. 628 */ 629 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 630 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 631 #elif defined(CONFIG_SDCARD) 632 /* 633 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 634 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 635 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 636 */ 637 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 638 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 639 #elif defined(CONFIG_NAND) 640 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 641 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 642 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 643 /* 644 * Slave has no ucode locally, it can fetch this from remote. When implementing 645 * in two corenet boards, slave's ucode could be stored in master's memory 646 * space, the address can be mapped from slave TLB->slave LAW-> 647 * slave SRIO or PCIE outbound window->master inbound window-> 648 * master LAW->the ucode address in master's memory space. 649 */ 650 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 651 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 652 #else 653 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 654 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 655 #endif 656 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 657 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 658 #endif /* CONFIG_NOBQFMAN */ 659 660 #ifdef CONFIG_SYS_DPAA_FMAN 661 #define CONFIG_FMAN_ENET 662 #define CONFIG_PHYLIB_10G 663 #define CONFIG_PHY_VITESSE 664 #define CONFIG_PHY_TERANETICS 665 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 666 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 667 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 668 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 669 #endif 670 671 #ifdef CONFIG_PCI 672 #define CONFIG_PCI_INDIRECT_BRIDGE 673 674 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 675 #endif /* CONFIG_PCI */ 676 677 #ifdef CONFIG_FMAN_ENET 678 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 679 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 680 681 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 682 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 683 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 684 685 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 686 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 687 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 688 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 689 690 #define CONFIG_MII /* MII PHY management */ 691 #define CONFIG_ETHPRIME "FM1@DTSEC1" 692 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 693 #endif 694 695 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR 696 697 /* 698 * Environment 699 */ 700 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 701 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 702 703 /* 704 * Command line configuration. 705 */ 706 #define CONFIG_CMD_DATE 707 #define CONFIG_CMD_EEPROM 708 #define CONFIG_CMD_ERRATA 709 #define CONFIG_CMD_IRQ 710 #define CONFIG_CMD_REGINFO 711 712 #ifdef CONFIG_PCI 713 #define CONFIG_CMD_PCI 714 #endif 715 716 /* Hash command with SHA acceleration supported in hardware */ 717 #ifdef CONFIG_FSL_CAAM 718 #define CONFIG_CMD_HASH 719 #define CONFIG_SHA_HW_ACCEL 720 #endif 721 722 /* 723 * USB 724 */ 725 #define CONFIG_HAS_FSL_DR_USB 726 727 #ifdef CONFIG_HAS_FSL_DR_USB 728 #define CONFIG_USB_EHCI 729 730 #ifdef CONFIG_USB_EHCI 731 #define CONFIG_USB_EHCI_FSL 732 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 733 #endif 734 #endif 735 736 /* 737 * Miscellaneous configurable options 738 */ 739 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 740 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 741 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 742 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 743 #ifdef CONFIG_CMD_KGDB 744 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 745 #else 746 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 747 #endif 748 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 749 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 750 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 751 752 /* 753 * For booting Linux, the board info and command line data 754 * have to be in the first 64 MB of memory, since this is 755 * the maximum mapped by the Linux kernel during initialization. 756 */ 757 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 758 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 759 760 #ifdef CONFIG_CMD_KGDB 761 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 762 #endif 763 764 /* 765 * Environment Configuration 766 */ 767 #define CONFIG_ROOTPATH "/opt/nfsroot" 768 #define CONFIG_BOOTFILE "uImage" 769 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 770 771 /* default location for tftp and bootm */ 772 #define CONFIG_LOADADDR 1000000 773 774 775 #define CONFIG_BAUDRATE 115200 776 777 #define __USB_PHY_TYPE ulpi 778 779 #ifdef CONFIG_ARCH_B4860 780 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 781 "bank_intlv=cs0_cs1;" \ 782 "en_cpc:cpc2;" 783 #else 784 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 785 #endif 786 787 #define CONFIG_EXTRA_ENV_SETTINGS \ 788 HWCONFIG \ 789 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 790 "netdev=eth0\0" \ 791 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 792 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 793 "tftpflash=tftpboot $loadaddr $uboot && " \ 794 "protect off $ubootaddr +$filesize && " \ 795 "erase $ubootaddr +$filesize && " \ 796 "cp.b $loadaddr $ubootaddr $filesize && " \ 797 "protect on $ubootaddr +$filesize && " \ 798 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 799 "consoledev=ttyS0\0" \ 800 "ramdiskaddr=2000000\0" \ 801 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 802 "fdtaddr=1e00000\0" \ 803 "fdtfile=b4860qds/b4860qds.dtb\0" \ 804 "bdev=sda3\0" 805 806 /* For emulation this causes u-boot to jump to the start of the proof point 807 app code automatically */ 808 #define CONFIG_PROOF_POINTS \ 809 "setenv bootargs root=/dev/$bdev rw " \ 810 "console=$consoledev,$baudrate $othbootargs;" \ 811 "cpu 1 release 0x29000000 - - -;" \ 812 "cpu 2 release 0x29000000 - - -;" \ 813 "cpu 3 release 0x29000000 - - -;" \ 814 "cpu 4 release 0x29000000 - - -;" \ 815 "cpu 5 release 0x29000000 - - -;" \ 816 "cpu 6 release 0x29000000 - - -;" \ 817 "cpu 7 release 0x29000000 - - -;" \ 818 "go 0x29000000" 819 820 #define CONFIG_HVBOOT \ 821 "setenv bootargs config-addr=0x60000000; " \ 822 "bootm 0x01000000 - 0x00f00000" 823 824 #define CONFIG_ALU \ 825 "setenv bootargs root=/dev/$bdev rw " \ 826 "console=$consoledev,$baudrate $othbootargs;" \ 827 "cpu 1 release 0x01000000 - - -;" \ 828 "cpu 2 release 0x01000000 - - -;" \ 829 "cpu 3 release 0x01000000 - - -;" \ 830 "cpu 4 release 0x01000000 - - -;" \ 831 "cpu 5 release 0x01000000 - - -;" \ 832 "cpu 6 release 0x01000000 - - -;" \ 833 "cpu 7 release 0x01000000 - - -;" \ 834 "go 0x01000000" 835 836 #define CONFIG_LINUX \ 837 "setenv bootargs root=/dev/ram rw " \ 838 "console=$consoledev,$baudrate $othbootargs;" \ 839 "setenv ramdiskaddr 0x02000000;" \ 840 "setenv fdtaddr 0x01e00000;" \ 841 "setenv loadaddr 0x1000000;" \ 842 "bootm $loadaddr $ramdiskaddr $fdtaddr" 843 844 #define CONFIG_HDBOOT \ 845 "setenv bootargs root=/dev/$bdev rw " \ 846 "console=$consoledev,$baudrate $othbootargs;" \ 847 "tftp $loadaddr $bootfile;" \ 848 "tftp $fdtaddr $fdtfile;" \ 849 "bootm $loadaddr - $fdtaddr" 850 851 #define CONFIG_NFSBOOTCOMMAND \ 852 "setenv bootargs root=/dev/nfs rw " \ 853 "nfsroot=$serverip:$rootpath " \ 854 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 855 "console=$consoledev,$baudrate $othbootargs;" \ 856 "tftp $loadaddr $bootfile;" \ 857 "tftp $fdtaddr $fdtfile;" \ 858 "bootm $loadaddr - $fdtaddr" 859 860 #define CONFIG_RAMBOOTCOMMAND \ 861 "setenv bootargs root=/dev/ram rw " \ 862 "console=$consoledev,$baudrate $othbootargs;" \ 863 "tftp $ramdiskaddr $ramdiskfile;" \ 864 "tftp $loadaddr $bootfile;" \ 865 "tftp $fdtaddr $fdtfile;" \ 866 "bootm $loadaddr $ramdiskaddr $fdtaddr" 867 868 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 869 870 #include <asm/fsl_secure_boot.h> 871 872 #endif /* __CONFIG_H */ 873