1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 /* 10 * B4860 QDS board configuration file 11 */ 12 #ifdef CONFIG_RAMBOOT_PBL 13 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 14 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 15 #ifndef CONFIG_NAND 16 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 18 #else 19 #define CONFIG_SPL_FLUSH_IMAGE 20 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 21 #define CONFIG_SPL_PAD_TO 0x40000 22 #define CONFIG_SPL_MAX_SIZE 0x28000 23 #define RESET_VECTOR_OFFSET 0x27FFC 24 #define BOOT_PAGE_OFFSET 0x27000 25 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 26 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 27 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 28 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 29 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 30 #define CONFIG_SPL_NAND_BOOT 31 #ifdef CONFIG_SPL_BUILD 32 #define CONFIG_SPL_SKIP_RELOCATE 33 #define CONFIG_SPL_COMMON_INIT_DDR 34 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #endif 46 47 /* High Level Configuration Options */ 48 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 49 50 #ifndef CONFIG_RESET_VECTOR_ADDRESS 51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 52 #endif 53 54 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 55 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 56 #define CONFIG_PCIE1 /* PCIE controller 1 */ 57 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 58 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 59 60 #ifndef CONFIG_ARCH_B4420 61 #define CONFIG_SYS_SRIO 62 #define CONFIG_SRIO1 /* SRIO port 1 */ 63 #define CONFIG_SRIO2 /* SRIO port 2 */ 64 #define CONFIG_SRIO_PCIE_BOOT_MASTER 65 #endif 66 67 /* I2C bus multiplexer */ 68 #define I2C_MUX_PCA_ADDR 0x77 69 70 /* VSC Crossbar switches */ 71 #define CONFIG_VSC_CROSSBAR 72 #define I2C_CH_DEFAULT 0x8 73 #define I2C_CH_VSC3316 0xc 74 #define I2C_CH_VSC3308 0xd 75 76 #define VSC3316_TX_ADDRESS 0x70 77 #define VSC3316_RX_ADDRESS 0x71 78 #define VSC3308_TX_ADDRESS 0x02 79 #define VSC3308_RX_ADDRESS 0x03 80 81 /* IDT clock synthesizers */ 82 #define CONFIG_IDT8T49N222A 83 #define I2C_CH_IDT 0x9 84 85 #define IDT_SERDES1_ADDRESS 0x6E 86 #define IDT_SERDES2_ADDRESS 0x6C 87 88 /* Voltage monitor on channel 2*/ 89 #define I2C_MUX_CH_VOL_MONITOR 0xa 90 #define I2C_VOL_MONITOR_ADDR 0x40 91 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 92 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 93 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 94 95 #define CONFIG_ZM7300 96 #define I2C_MUX_CH_DPM 0xa 97 #define I2C_DPM_ADDR 0x28 98 99 #define CONFIG_ENV_OVERWRITE 100 101 #if defined(CONFIG_SPIFLASH) 102 #define CONFIG_ENV_SPI_BUS 0 103 #define CONFIG_ENV_SPI_CS 0 104 #define CONFIG_ENV_SPI_MAX_HZ 10000000 105 #define CONFIG_ENV_SPI_MODE 0 106 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 107 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 108 #define CONFIG_ENV_SECT_SIZE 0x10000 109 #elif defined(CONFIG_SDCARD) 110 #define CONFIG_SYS_MMC_ENV_DEV 0 111 #define CONFIG_ENV_SIZE 0x2000 112 #define CONFIG_ENV_OFFSET (512 * 1097) 113 #elif defined(CONFIG_NAND) 114 #define CONFIG_ENV_SIZE 0x2000 115 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 116 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 117 #define CONFIG_ENV_ADDR 0xffe20000 118 #define CONFIG_ENV_SIZE 0x2000 119 #elif defined(CONFIG_ENV_IS_NOWHERE) 120 #define CONFIG_ENV_SIZE 0x2000 121 #else 122 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 123 #define CONFIG_ENV_SIZE 0x2000 124 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 125 #endif 126 127 #ifndef __ASSEMBLY__ 128 unsigned long get_board_sys_clk(void); 129 unsigned long get_board_ddr_clk(void); 130 #endif 131 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 132 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 133 134 /* 135 * These can be toggled for performance analysis, otherwise use default. 136 */ 137 #define CONFIG_SYS_CACHE_STASHING 138 #define CONFIG_BTB /* toggle branch predition */ 139 #define CONFIG_DDR_ECC 140 #ifdef CONFIG_DDR_ECC 141 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 142 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 143 #endif 144 145 #define CONFIG_ENABLE_36BIT_PHYS 146 147 #ifdef CONFIG_PHYS_64BIT 148 #define CONFIG_ADDR_MAP 149 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 150 #endif 151 152 #if 0 153 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 154 #endif 155 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 156 #define CONFIG_SYS_MEMTEST_END 0x00400000 157 158 /* 159 * Config the L3 Cache as L3 SRAM 160 */ 161 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 162 #define CONFIG_SYS_L3_SIZE 256 << 10 163 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 164 #ifdef CONFIG_NAND 165 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 166 #endif 167 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 168 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 169 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 170 171 #ifdef CONFIG_PHYS_64BIT 172 #define CONFIG_SYS_DCSRBAR 0xf0000000 173 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 174 #endif 175 176 /* EEPROM */ 177 #define CONFIG_ID_EEPROM 178 #define CONFIG_SYS_I2C_EEPROM_NXID 179 #define CONFIG_SYS_EEPROM_BUS_NUM 0 180 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 181 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 182 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 183 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 184 185 /* 186 * DDR Setup 187 */ 188 #define CONFIG_VERY_BIG_RAM 189 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 190 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 191 192 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 193 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 194 195 #define CONFIG_DDR_SPD 196 #define CONFIG_SYS_DDR_RAW_TIMING 197 #ifndef CONFIG_SPL_BUILD 198 #define CONFIG_FSL_DDR_INTERACTIVE 199 #endif 200 201 #define CONFIG_SYS_SPD_BUS_NUM 0 202 #define SPD_EEPROM_ADDRESS1 0x51 203 #define SPD_EEPROM_ADDRESS2 0x53 204 205 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 206 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 207 208 /* 209 * IFC Definitions 210 */ 211 #define CONFIG_SYS_FLASH_BASE 0xe0000000 212 #ifdef CONFIG_PHYS_64BIT 213 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 214 #else 215 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 216 #endif 217 218 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 219 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 220 + 0x8000000) | \ 221 CSPR_PORT_SIZE_16 | \ 222 CSPR_MSEL_NOR | \ 223 CSPR_V) 224 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 225 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 226 CSPR_PORT_SIZE_16 | \ 227 CSPR_MSEL_NOR | \ 228 CSPR_V) 229 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 230 /* NOR Flash Timing Params */ 231 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 232 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 233 FTIM0_NOR_TEADC(0x04) | \ 234 FTIM0_NOR_TEAHC(0x20)) 235 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 236 FTIM1_NOR_TRAD_NOR(0x1A) |\ 237 FTIM1_NOR_TSEQRAD_NOR(0x13)) 238 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 239 FTIM2_NOR_TCH(0x0E) | \ 240 FTIM2_NOR_TWPH(0x0E) | \ 241 FTIM2_NOR_TWP(0x1c)) 242 #define CONFIG_SYS_NOR_FTIM3 0x0 243 244 #define CONFIG_SYS_FLASH_QUIET_TEST 245 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 246 247 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 248 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 249 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 250 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 251 252 #define CONFIG_SYS_FLASH_EMPTY_INFO 253 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 254 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 255 256 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 257 #define CONFIG_FSL_QIXIS_V2 258 #define QIXIS_BASE 0xffdf0000 259 #ifdef CONFIG_PHYS_64BIT 260 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 261 #else 262 #define QIXIS_BASE_PHYS QIXIS_BASE 263 #endif 264 #define QIXIS_LBMAP_SWITCH 0x01 265 #define QIXIS_LBMAP_MASK 0x0f 266 #define QIXIS_LBMAP_SHIFT 0 267 #define QIXIS_LBMAP_DFLTBANK 0x00 268 #define QIXIS_LBMAP_ALTBANK 0x02 269 #define QIXIS_RST_CTL_RESET 0x31 270 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 271 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 272 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 273 274 #define CONFIG_SYS_CSPR3_EXT (0xf) 275 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 276 | CSPR_PORT_SIZE_8 \ 277 | CSPR_MSEL_GPCM \ 278 | CSPR_V) 279 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) 280 #define CONFIG_SYS_CSOR3 0x0 281 /* QIXIS Timing parameters for IFC CS3 */ 282 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 283 FTIM0_GPCM_TEADC(0x0e) | \ 284 FTIM0_GPCM_TEAHC(0x0e)) 285 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 286 FTIM1_GPCM_TRAD(0x1f)) 287 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 288 FTIM2_GPCM_TCH(0x8) | \ 289 FTIM2_GPCM_TWP(0x1f)) 290 #define CONFIG_SYS_CS3_FTIM3 0x0 291 292 /* NAND Flash on IFC */ 293 #define CONFIG_NAND_FSL_IFC 294 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 295 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 296 #define CONFIG_SYS_NAND_BASE 0xff800000 297 #ifdef CONFIG_PHYS_64BIT 298 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 299 #else 300 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 301 #endif 302 303 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 304 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 305 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 306 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 307 | CSPR_V) 308 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 309 310 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 311 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 312 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 313 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 314 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 315 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 316 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 317 318 #define CONFIG_SYS_NAND_ONFI_DETECTION 319 320 /* ONFI NAND Flash mode0 Timing Params */ 321 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 322 FTIM0_NAND_TWP(0x18) | \ 323 FTIM0_NAND_TWCHT(0x07) | \ 324 FTIM0_NAND_TWH(0x0a)) 325 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 326 FTIM1_NAND_TWBE(0x39) | \ 327 FTIM1_NAND_TRR(0x0e) | \ 328 FTIM1_NAND_TRP(0x18)) 329 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 330 FTIM2_NAND_TREH(0x0a) | \ 331 FTIM2_NAND_TWHRE(0x1e)) 332 #define CONFIG_SYS_NAND_FTIM3 0x0 333 334 #define CONFIG_SYS_NAND_DDR_LAW 11 335 336 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 337 #define CONFIG_SYS_MAX_NAND_DEVICE 1 338 339 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 340 341 #if defined(CONFIG_NAND) 342 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 343 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 344 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 345 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 346 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 347 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 348 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 349 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 350 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 351 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 352 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 353 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 354 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 355 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 356 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 357 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 358 #else 359 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 360 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 361 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 362 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 363 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 364 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 365 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 366 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 367 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 368 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 369 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 370 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 371 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 372 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 373 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 374 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 375 #endif 376 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 377 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 378 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 379 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 380 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 381 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 382 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 383 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 384 385 #ifdef CONFIG_SPL_BUILD 386 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 387 #else 388 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 389 #endif 390 391 #if defined(CONFIG_RAMBOOT_PBL) 392 #define CONFIG_SYS_RAMBOOT 393 #endif 394 395 #define CONFIG_HWCONFIG 396 397 /* define to use L1 as initial stack */ 398 #define CONFIG_L1_INIT_RAM 399 #define CONFIG_SYS_INIT_RAM_LOCK 400 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 401 #ifdef CONFIG_PHYS_64BIT 402 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 403 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 404 /* The assembler doesn't like typecast */ 405 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 406 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 407 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 408 #else 409 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 410 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 411 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 412 #endif 413 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 414 415 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 416 GENERATED_GBL_DATA_SIZE) 417 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 418 419 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 420 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 421 422 /* Serial Port - controlled on board with jumper J8 423 * open - index 2 424 * shorted - index 1 425 */ 426 #define CONFIG_SYS_NS16550_SERIAL 427 #define CONFIG_SYS_NS16550_REG_SIZE 1 428 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 429 430 #define CONFIG_SYS_BAUDRATE_TABLE \ 431 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 432 433 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 434 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 435 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 436 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 437 438 /* I2C */ 439 #define CONFIG_SYS_I2C 440 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 441 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 442 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 443 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 444 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 445 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 446 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 447 448 /* 449 * RTC configuration 450 */ 451 #define RTC 452 #define CONFIG_RTC_DS3231 1 453 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 454 455 /* 456 * RapidIO 457 */ 458 #ifdef CONFIG_SYS_SRIO 459 #ifdef CONFIG_SRIO1 460 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 461 #ifdef CONFIG_PHYS_64BIT 462 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 463 #else 464 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 465 #endif 466 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 467 #endif 468 469 #ifdef CONFIG_SRIO2 470 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 471 #ifdef CONFIG_PHYS_64BIT 472 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 473 #else 474 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 475 #endif 476 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 477 #endif 478 #endif 479 480 /* 481 * for slave u-boot IMAGE instored in master memory space, 482 * PHYS must be aligned based on the SIZE 483 */ 484 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 485 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 486 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 487 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 488 /* 489 * for slave UCODE and ENV instored in master memory space, 490 * PHYS must be aligned based on the SIZE 491 */ 492 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 493 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 494 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 495 496 /* slave core release by master*/ 497 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 498 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 499 500 /* 501 * SRIO_PCIE_BOOT - SLAVE 502 */ 503 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 504 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 505 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 506 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 507 #endif 508 509 /* 510 * eSPI - Enhanced SPI 511 */ 512 #define CONFIG_SF_DEFAULT_SPEED 10000000 513 #define CONFIG_SF_DEFAULT_MODE 0 514 515 /* 516 * MAPLE 517 */ 518 #ifdef CONFIG_PHYS_64BIT 519 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 520 #else 521 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 522 #endif 523 524 /* 525 * General PCI 526 * Memory space is mapped 1-1, but I/O space must start from 0. 527 */ 528 529 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 530 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 531 #ifdef CONFIG_PHYS_64BIT 532 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 533 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 534 #else 535 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 536 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 537 #endif 538 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 539 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 540 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 541 #ifdef CONFIG_PHYS_64BIT 542 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 543 #else 544 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 545 #endif 546 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 547 548 /* Qman/Bman */ 549 #ifndef CONFIG_NOBQFMAN 550 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 551 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 552 #ifdef CONFIG_PHYS_64BIT 553 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 554 #else 555 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 556 #endif 557 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 558 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 559 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 560 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 561 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 562 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 563 CONFIG_SYS_BMAN_CENA_SIZE) 564 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 565 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 566 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 567 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 568 #ifdef CONFIG_PHYS_64BIT 569 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 570 #else 571 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 572 #endif 573 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 574 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 575 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 576 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 577 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 578 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 579 CONFIG_SYS_QMAN_CENA_SIZE) 580 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 581 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 582 583 #define CONFIG_SYS_DPAA_FMAN 584 585 #define CONFIG_SYS_DPAA_RMAN 586 587 /* Default address of microcode for the Linux Fman driver */ 588 #if defined(CONFIG_SPIFLASH) 589 /* 590 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 591 * env, so we got 0x110000. 592 */ 593 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 594 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 595 #elif defined(CONFIG_SDCARD) 596 /* 597 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 598 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 599 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 600 */ 601 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 602 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 603 #elif defined(CONFIG_NAND) 604 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 605 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 606 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 607 /* 608 * Slave has no ucode locally, it can fetch this from remote. When implementing 609 * in two corenet boards, slave's ucode could be stored in master's memory 610 * space, the address can be mapped from slave TLB->slave LAW-> 611 * slave SRIO or PCIE outbound window->master inbound window-> 612 * master LAW->the ucode address in master's memory space. 613 */ 614 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 615 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 616 #else 617 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 618 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 619 #endif 620 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 621 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 622 #endif /* CONFIG_NOBQFMAN */ 623 624 #ifdef CONFIG_SYS_DPAA_FMAN 625 #define CONFIG_FMAN_ENET 626 #define CONFIG_PHYLIB_10G 627 #define CONFIG_PHY_VITESSE 628 #define CONFIG_PHY_TERANETICS 629 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 630 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 631 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 632 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 633 #endif 634 635 #ifdef CONFIG_PCI 636 #define CONFIG_PCI_INDIRECT_BRIDGE 637 638 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 639 #endif /* CONFIG_PCI */ 640 641 #ifdef CONFIG_FMAN_ENET 642 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 643 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 644 645 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 646 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 647 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 648 649 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 650 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 651 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 652 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 653 654 #define CONFIG_ETHPRIME "FM1@DTSEC1" 655 #endif 656 657 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR 658 659 /* 660 * Environment 661 */ 662 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 663 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 664 665 /* 666 * USB 667 */ 668 #define CONFIG_HAS_FSL_DR_USB 669 670 #ifdef CONFIG_HAS_FSL_DR_USB 671 #ifdef CONFIG_USB_EHCI_HCD 672 #define CONFIG_USB_EHCI_FSL 673 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 674 #endif 675 #endif 676 677 /* 678 * Miscellaneous configurable options 679 */ 680 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 681 682 /* 683 * For booting Linux, the board info and command line data 684 * have to be in the first 64 MB of memory, since this is 685 * the maximum mapped by the Linux kernel during initialization. 686 */ 687 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 688 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 689 690 #ifdef CONFIG_CMD_KGDB 691 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 692 #endif 693 694 /* 695 * Environment Configuration 696 */ 697 #define CONFIG_ROOTPATH "/opt/nfsroot" 698 #define CONFIG_BOOTFILE "uImage" 699 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 700 701 /* default location for tftp and bootm */ 702 #define CONFIG_LOADADDR 1000000 703 704 #define __USB_PHY_TYPE ulpi 705 706 #ifdef CONFIG_ARCH_B4860 707 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 708 "bank_intlv=cs0_cs1;" \ 709 "en_cpc:cpc2;" 710 #else 711 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 712 #endif 713 714 #define CONFIG_EXTRA_ENV_SETTINGS \ 715 HWCONFIG \ 716 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 717 "netdev=eth0\0" \ 718 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 719 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 720 "tftpflash=tftpboot $loadaddr $uboot && " \ 721 "protect off $ubootaddr +$filesize && " \ 722 "erase $ubootaddr +$filesize && " \ 723 "cp.b $loadaddr $ubootaddr $filesize && " \ 724 "protect on $ubootaddr +$filesize && " \ 725 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 726 "consoledev=ttyS0\0" \ 727 "ramdiskaddr=2000000\0" \ 728 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 729 "fdtaddr=1e00000\0" \ 730 "fdtfile=b4860qds/b4860qds.dtb\0" \ 731 "bdev=sda3\0" 732 733 /* For emulation this causes u-boot to jump to the start of the proof point 734 app code automatically */ 735 #define CONFIG_PROOF_POINTS \ 736 "setenv bootargs root=/dev/$bdev rw " \ 737 "console=$consoledev,$baudrate $othbootargs;" \ 738 "cpu 1 release 0x29000000 - - -;" \ 739 "cpu 2 release 0x29000000 - - -;" \ 740 "cpu 3 release 0x29000000 - - -;" \ 741 "cpu 4 release 0x29000000 - - -;" \ 742 "cpu 5 release 0x29000000 - - -;" \ 743 "cpu 6 release 0x29000000 - - -;" \ 744 "cpu 7 release 0x29000000 - - -;" \ 745 "go 0x29000000" 746 747 #define CONFIG_HVBOOT \ 748 "setenv bootargs config-addr=0x60000000; " \ 749 "bootm 0x01000000 - 0x00f00000" 750 751 #define CONFIG_ALU \ 752 "setenv bootargs root=/dev/$bdev rw " \ 753 "console=$consoledev,$baudrate $othbootargs;" \ 754 "cpu 1 release 0x01000000 - - -;" \ 755 "cpu 2 release 0x01000000 - - -;" \ 756 "cpu 3 release 0x01000000 - - -;" \ 757 "cpu 4 release 0x01000000 - - -;" \ 758 "cpu 5 release 0x01000000 - - -;" \ 759 "cpu 6 release 0x01000000 - - -;" \ 760 "cpu 7 release 0x01000000 - - -;" \ 761 "go 0x01000000" 762 763 #define CONFIG_LINUX \ 764 "setenv bootargs root=/dev/ram rw " \ 765 "console=$consoledev,$baudrate $othbootargs;" \ 766 "setenv ramdiskaddr 0x02000000;" \ 767 "setenv fdtaddr 0x01e00000;" \ 768 "setenv loadaddr 0x1000000;" \ 769 "bootm $loadaddr $ramdiskaddr $fdtaddr" 770 771 #define CONFIG_HDBOOT \ 772 "setenv bootargs root=/dev/$bdev rw " \ 773 "console=$consoledev,$baudrate $othbootargs;" \ 774 "tftp $loadaddr $bootfile;" \ 775 "tftp $fdtaddr $fdtfile;" \ 776 "bootm $loadaddr - $fdtaddr" 777 778 #define CONFIG_NFSBOOTCOMMAND \ 779 "setenv bootargs root=/dev/nfs rw " \ 780 "nfsroot=$serverip:$rootpath " \ 781 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 782 "console=$consoledev,$baudrate $othbootargs;" \ 783 "tftp $loadaddr $bootfile;" \ 784 "tftp $fdtaddr $fdtfile;" \ 785 "bootm $loadaddr - $fdtaddr" 786 787 #define CONFIG_RAMBOOTCOMMAND \ 788 "setenv bootargs root=/dev/ram rw " \ 789 "console=$consoledev,$baudrate $othbootargs;" \ 790 "tftp $ramdiskaddr $ramdiskfile;" \ 791 "tftp $loadaddr $bootfile;" \ 792 "tftp $fdtaddr $fdtfile;" \ 793 "bootm $loadaddr $ramdiskaddr $fdtaddr" 794 795 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 796 797 #include <asm/fsl_secure_boot.h> 798 799 #endif /* __CONFIG_H */ 800