1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * B4860 QDS board configuration file 12 */ 13 #ifdef CONFIG_RAMBOOT_PBL 14 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 15 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 16 #ifndef CONFIG_NAND 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #else 20 #define CONFIG_SPL_FLUSH_IMAGE 21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 22 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 23 #define CONFIG_SPL_PAD_TO 0x40000 24 #define CONFIG_SPL_MAX_SIZE 0x28000 25 #define RESET_VECTOR_OFFSET 0x27FFC 26 #define BOOT_PAGE_OFFSET 0x27000 27 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 28 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 29 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 30 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 31 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 32 #define CONFIG_SPL_NAND_BOOT 33 #ifdef CONFIG_SPL_BUILD 34 #define CONFIG_SPL_SKIP_RELOCATE 35 #define CONFIG_SPL_COMMON_INIT_DDR 36 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 37 #endif 38 #endif 39 #endif 40 41 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 42 /* Set 1M boot space */ 43 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 45 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 46 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 47 #endif 48 49 /* High Level Configuration Options */ 50 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 51 #define CONFIG_MP /* support multiple processors */ 52 53 #ifndef CONFIG_RESET_VECTOR_ADDRESS 54 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 55 #endif 56 57 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 58 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 59 #define CONFIG_PCIE1 /* PCIE controller 1 */ 60 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 61 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 62 63 #ifndef CONFIG_ARCH_B4420 64 #define CONFIG_SYS_SRIO 65 #define CONFIG_SRIO1 /* SRIO port 1 */ 66 #define CONFIG_SRIO2 /* SRIO port 2 */ 67 #define CONFIG_SRIO_PCIE_BOOT_MASTER 68 #endif 69 70 /* I2C bus multiplexer */ 71 #define I2C_MUX_PCA_ADDR 0x77 72 73 /* VSC Crossbar switches */ 74 #define CONFIG_VSC_CROSSBAR 75 #define I2C_CH_DEFAULT 0x8 76 #define I2C_CH_VSC3316 0xc 77 #define I2C_CH_VSC3308 0xd 78 79 #define VSC3316_TX_ADDRESS 0x70 80 #define VSC3316_RX_ADDRESS 0x71 81 #define VSC3308_TX_ADDRESS 0x02 82 #define VSC3308_RX_ADDRESS 0x03 83 84 /* IDT clock synthesizers */ 85 #define CONFIG_IDT8T49N222A 86 #define I2C_CH_IDT 0x9 87 88 #define IDT_SERDES1_ADDRESS 0x6E 89 #define IDT_SERDES2_ADDRESS 0x6C 90 91 /* Voltage monitor on channel 2*/ 92 #define I2C_MUX_CH_VOL_MONITOR 0xa 93 #define I2C_VOL_MONITOR_ADDR 0x40 94 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 95 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 96 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 97 98 #define CONFIG_ZM7300 99 #define I2C_MUX_CH_DPM 0xa 100 #define I2C_DPM_ADDR 0x28 101 102 #define CONFIG_ENV_OVERWRITE 103 104 #ifndef CONFIG_MTD_NOR_FLASH 105 #else 106 #define CONFIG_FLASH_CFI_DRIVER 107 #define CONFIG_SYS_FLASH_CFI 108 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 109 #endif 110 111 #if defined(CONFIG_SPIFLASH) 112 #define CONFIG_SYS_EXTRA_ENV_RELOC 113 #define CONFIG_ENV_SPI_BUS 0 114 #define CONFIG_ENV_SPI_CS 0 115 #define CONFIG_ENV_SPI_MAX_HZ 10000000 116 #define CONFIG_ENV_SPI_MODE 0 117 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 118 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 119 #define CONFIG_ENV_SECT_SIZE 0x10000 120 #elif defined(CONFIG_SDCARD) 121 #define CONFIG_SYS_EXTRA_ENV_RELOC 122 #define CONFIG_SYS_MMC_ENV_DEV 0 123 #define CONFIG_ENV_SIZE 0x2000 124 #define CONFIG_ENV_OFFSET (512 * 1097) 125 #elif defined(CONFIG_NAND) 126 #define CONFIG_SYS_EXTRA_ENV_RELOC 127 #define CONFIG_ENV_SIZE 0x2000 128 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 129 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 130 #define CONFIG_ENV_ADDR 0xffe20000 131 #define CONFIG_ENV_SIZE 0x2000 132 #elif defined(CONFIG_ENV_IS_NOWHERE) 133 #define CONFIG_ENV_SIZE 0x2000 134 #else 135 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 136 #define CONFIG_ENV_SIZE 0x2000 137 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 138 #endif 139 140 #ifndef __ASSEMBLY__ 141 unsigned long get_board_sys_clk(void); 142 unsigned long get_board_ddr_clk(void); 143 #endif 144 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 145 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 146 147 /* 148 * These can be toggled for performance analysis, otherwise use default. 149 */ 150 #define CONFIG_SYS_CACHE_STASHING 151 #define CONFIG_BTB /* toggle branch predition */ 152 #define CONFIG_DDR_ECC 153 #ifdef CONFIG_DDR_ECC 154 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 155 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 156 #endif 157 158 #define CONFIG_ENABLE_36BIT_PHYS 159 160 #ifdef CONFIG_PHYS_64BIT 161 #define CONFIG_ADDR_MAP 162 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 163 #endif 164 165 #if 0 166 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 167 #endif 168 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 169 #define CONFIG_SYS_MEMTEST_END 0x00400000 170 171 /* 172 * Config the L3 Cache as L3 SRAM 173 */ 174 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 175 #define CONFIG_SYS_L3_SIZE 256 << 10 176 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 177 #ifdef CONFIG_NAND 178 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 179 #endif 180 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 181 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 182 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 183 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 184 185 #ifdef CONFIG_PHYS_64BIT 186 #define CONFIG_SYS_DCSRBAR 0xf0000000 187 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 188 #endif 189 190 /* EEPROM */ 191 #define CONFIG_ID_EEPROM 192 #define CONFIG_SYS_I2C_EEPROM_NXID 193 #define CONFIG_SYS_EEPROM_BUS_NUM 0 194 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 195 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 196 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 197 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 198 199 /* 200 * DDR Setup 201 */ 202 #define CONFIG_VERY_BIG_RAM 203 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 204 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 205 206 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 207 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 208 209 #define CONFIG_DDR_SPD 210 #define CONFIG_SYS_DDR_RAW_TIMING 211 #ifndef CONFIG_SPL_BUILD 212 #define CONFIG_FSL_DDR_INTERACTIVE 213 #endif 214 215 #define CONFIG_SYS_SPD_BUS_NUM 0 216 #define SPD_EEPROM_ADDRESS1 0x51 217 #define SPD_EEPROM_ADDRESS2 0x53 218 219 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 220 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 221 222 /* 223 * IFC Definitions 224 */ 225 #define CONFIG_SYS_FLASH_BASE 0xe0000000 226 #ifdef CONFIG_PHYS_64BIT 227 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 228 #else 229 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 230 #endif 231 232 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 233 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 234 + 0x8000000) | \ 235 CSPR_PORT_SIZE_16 | \ 236 CSPR_MSEL_NOR | \ 237 CSPR_V) 238 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 239 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 240 CSPR_PORT_SIZE_16 | \ 241 CSPR_MSEL_NOR | \ 242 CSPR_V) 243 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 244 /* NOR Flash Timing Params */ 245 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 246 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 247 FTIM0_NOR_TEADC(0x04) | \ 248 FTIM0_NOR_TEAHC(0x20)) 249 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 250 FTIM1_NOR_TRAD_NOR(0x1A) |\ 251 FTIM1_NOR_TSEQRAD_NOR(0x13)) 252 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 253 FTIM2_NOR_TCH(0x0E) | \ 254 FTIM2_NOR_TWPH(0x0E) | \ 255 FTIM2_NOR_TWP(0x1c)) 256 #define CONFIG_SYS_NOR_FTIM3 0x0 257 258 #define CONFIG_SYS_FLASH_QUIET_TEST 259 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 260 261 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 262 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 263 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 264 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 265 266 #define CONFIG_SYS_FLASH_EMPTY_INFO 267 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 268 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 269 270 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 271 #define CONFIG_FSL_QIXIS_V2 272 #define QIXIS_BASE 0xffdf0000 273 #ifdef CONFIG_PHYS_64BIT 274 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 275 #else 276 #define QIXIS_BASE_PHYS QIXIS_BASE 277 #endif 278 #define QIXIS_LBMAP_SWITCH 0x01 279 #define QIXIS_LBMAP_MASK 0x0f 280 #define QIXIS_LBMAP_SHIFT 0 281 #define QIXIS_LBMAP_DFLTBANK 0x00 282 #define QIXIS_LBMAP_ALTBANK 0x02 283 #define QIXIS_RST_CTL_RESET 0x31 284 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 285 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 286 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 287 288 #define CONFIG_SYS_CSPR3_EXT (0xf) 289 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 290 | CSPR_PORT_SIZE_8 \ 291 | CSPR_MSEL_GPCM \ 292 | CSPR_V) 293 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 294 #define CONFIG_SYS_CSOR3 0x0 295 /* QIXIS Timing parameters for IFC CS3 */ 296 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 297 FTIM0_GPCM_TEADC(0x0e) | \ 298 FTIM0_GPCM_TEAHC(0x0e)) 299 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 300 FTIM1_GPCM_TRAD(0x1f)) 301 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 302 FTIM2_GPCM_TCH(0x8) | \ 303 FTIM2_GPCM_TWP(0x1f)) 304 #define CONFIG_SYS_CS3_FTIM3 0x0 305 306 /* NAND Flash on IFC */ 307 #define CONFIG_NAND_FSL_IFC 308 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 309 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 310 #define CONFIG_SYS_NAND_BASE 0xff800000 311 #ifdef CONFIG_PHYS_64BIT 312 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 313 #else 314 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 315 #endif 316 317 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 318 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 319 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 320 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 321 | CSPR_V) 322 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 323 324 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 325 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 326 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 327 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 328 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 329 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 330 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 331 332 #define CONFIG_SYS_NAND_ONFI_DETECTION 333 334 /* ONFI NAND Flash mode0 Timing Params */ 335 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 336 FTIM0_NAND_TWP(0x18) | \ 337 FTIM0_NAND_TWCHT(0x07) | \ 338 FTIM0_NAND_TWH(0x0a)) 339 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 340 FTIM1_NAND_TWBE(0x39) | \ 341 FTIM1_NAND_TRR(0x0e) | \ 342 FTIM1_NAND_TRP(0x18)) 343 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 344 FTIM2_NAND_TREH(0x0a) | \ 345 FTIM2_NAND_TWHRE(0x1e)) 346 #define CONFIG_SYS_NAND_FTIM3 0x0 347 348 #define CONFIG_SYS_NAND_DDR_LAW 11 349 350 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 351 #define CONFIG_SYS_MAX_NAND_DEVICE 1 352 353 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 354 355 #if defined(CONFIG_NAND) 356 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 357 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 358 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 359 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 360 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 361 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 362 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 363 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 364 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 365 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 366 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 367 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 368 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 369 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 370 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 371 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 372 #else 373 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 374 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 375 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 376 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 377 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 378 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 379 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 380 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 381 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 382 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 383 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 384 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 385 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 386 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 387 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 388 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 389 #endif 390 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 391 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 392 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 393 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 394 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 395 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 396 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 397 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 398 399 #ifdef CONFIG_SPL_BUILD 400 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 401 #else 402 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 403 #endif 404 405 #if defined(CONFIG_RAMBOOT_PBL) 406 #define CONFIG_SYS_RAMBOOT 407 #endif 408 409 #define CONFIG_MISC_INIT_R 410 411 #define CONFIG_HWCONFIG 412 413 /* define to use L1 as initial stack */ 414 #define CONFIG_L1_INIT_RAM 415 #define CONFIG_SYS_INIT_RAM_LOCK 416 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 417 #ifdef CONFIG_PHYS_64BIT 418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 419 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 420 /* The assembler doesn't like typecast */ 421 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 422 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 423 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 424 #else 425 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 427 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 428 #endif 429 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 430 431 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 432 GENERATED_GBL_DATA_SIZE) 433 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 434 435 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 436 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 437 438 /* Serial Port - controlled on board with jumper J8 439 * open - index 2 440 * shorted - index 1 441 */ 442 #define CONFIG_SYS_NS16550_SERIAL 443 #define CONFIG_SYS_NS16550_REG_SIZE 1 444 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 445 446 #define CONFIG_SYS_BAUDRATE_TABLE \ 447 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 448 449 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 450 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 451 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 452 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 453 454 /* I2C */ 455 #define CONFIG_SYS_I2C 456 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 457 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 458 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 459 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 460 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 461 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 462 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 463 464 /* 465 * RTC configuration 466 */ 467 #define RTC 468 #define CONFIG_RTC_DS3231 1 469 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 470 471 /* 472 * RapidIO 473 */ 474 #ifdef CONFIG_SYS_SRIO 475 #ifdef CONFIG_SRIO1 476 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 477 #ifdef CONFIG_PHYS_64BIT 478 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 479 #else 480 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 481 #endif 482 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 483 #endif 484 485 #ifdef CONFIG_SRIO2 486 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 487 #ifdef CONFIG_PHYS_64BIT 488 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 489 #else 490 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 491 #endif 492 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 493 #endif 494 #endif 495 496 /* 497 * for slave u-boot IMAGE instored in master memory space, 498 * PHYS must be aligned based on the SIZE 499 */ 500 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 501 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 502 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 503 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 504 /* 505 * for slave UCODE and ENV instored in master memory space, 506 * PHYS must be aligned based on the SIZE 507 */ 508 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 509 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 510 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 511 512 /* slave core release by master*/ 513 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 514 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 515 516 /* 517 * SRIO_PCIE_BOOT - SLAVE 518 */ 519 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 520 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 521 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 522 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 523 #endif 524 525 /* 526 * eSPI - Enhanced SPI 527 */ 528 #define CONFIG_SF_DEFAULT_SPEED 10000000 529 #define CONFIG_SF_DEFAULT_MODE 0 530 531 /* 532 * MAPLE 533 */ 534 #ifdef CONFIG_PHYS_64BIT 535 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 536 #else 537 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 538 #endif 539 540 /* 541 * General PCI 542 * Memory space is mapped 1-1, but I/O space must start from 0. 543 */ 544 545 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 546 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 547 #ifdef CONFIG_PHYS_64BIT 548 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 549 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 550 #else 551 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 552 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 553 #endif 554 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 555 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 556 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 557 #ifdef CONFIG_PHYS_64BIT 558 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 559 #else 560 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 561 #endif 562 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 563 564 /* Qman/Bman */ 565 #ifndef CONFIG_NOBQFMAN 566 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 567 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 568 #ifdef CONFIG_PHYS_64BIT 569 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 570 #else 571 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 572 #endif 573 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 574 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 575 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 576 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 577 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 578 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 579 CONFIG_SYS_BMAN_CENA_SIZE) 580 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 581 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 582 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 583 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 584 #ifdef CONFIG_PHYS_64BIT 585 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 586 #else 587 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 588 #endif 589 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 590 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 591 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 592 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 593 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 594 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 595 CONFIG_SYS_QMAN_CENA_SIZE) 596 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 597 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 598 599 #define CONFIG_SYS_DPAA_FMAN 600 601 #define CONFIG_SYS_DPAA_RMAN 602 603 /* Default address of microcode for the Linux Fman driver */ 604 #if defined(CONFIG_SPIFLASH) 605 /* 606 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 607 * env, so we got 0x110000. 608 */ 609 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 610 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 611 #elif defined(CONFIG_SDCARD) 612 /* 613 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 614 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 615 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 616 */ 617 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 618 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 619 #elif defined(CONFIG_NAND) 620 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 621 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 622 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 623 /* 624 * Slave has no ucode locally, it can fetch this from remote. When implementing 625 * in two corenet boards, slave's ucode could be stored in master's memory 626 * space, the address can be mapped from slave TLB->slave LAW-> 627 * slave SRIO or PCIE outbound window->master inbound window-> 628 * master LAW->the ucode address in master's memory space. 629 */ 630 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 631 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 632 #else 633 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 634 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 635 #endif 636 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 637 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 638 #endif /* CONFIG_NOBQFMAN */ 639 640 #ifdef CONFIG_SYS_DPAA_FMAN 641 #define CONFIG_FMAN_ENET 642 #define CONFIG_PHYLIB_10G 643 #define CONFIG_PHY_VITESSE 644 #define CONFIG_PHY_TERANETICS 645 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 646 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 647 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 648 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 649 #endif 650 651 #ifdef CONFIG_PCI 652 #define CONFIG_PCI_INDIRECT_BRIDGE 653 654 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 655 #endif /* CONFIG_PCI */ 656 657 #ifdef CONFIG_FMAN_ENET 658 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 659 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 660 661 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 662 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 663 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 664 665 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 666 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 667 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 668 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 669 670 #define CONFIG_MII /* MII PHY management */ 671 #define CONFIG_ETHPRIME "FM1@DTSEC1" 672 #endif 673 674 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR 675 676 /* 677 * Environment 678 */ 679 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 680 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 681 682 /* 683 * USB 684 */ 685 #define CONFIG_HAS_FSL_DR_USB 686 687 #ifdef CONFIG_HAS_FSL_DR_USB 688 #ifdef CONFIG_USB_EHCI_HCD 689 #define CONFIG_USB_EHCI_FSL 690 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 691 #endif 692 #endif 693 694 /* 695 * Miscellaneous configurable options 696 */ 697 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 698 699 /* 700 * For booting Linux, the board info and command line data 701 * have to be in the first 64 MB of memory, since this is 702 * the maximum mapped by the Linux kernel during initialization. 703 */ 704 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 705 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 706 707 #ifdef CONFIG_CMD_KGDB 708 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 709 #endif 710 711 /* 712 * Environment Configuration 713 */ 714 #define CONFIG_ROOTPATH "/opt/nfsroot" 715 #define CONFIG_BOOTFILE "uImage" 716 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 717 718 /* default location for tftp and bootm */ 719 #define CONFIG_LOADADDR 1000000 720 721 #define __USB_PHY_TYPE ulpi 722 723 #ifdef CONFIG_ARCH_B4860 724 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 725 "bank_intlv=cs0_cs1;" \ 726 "en_cpc:cpc2;" 727 #else 728 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 729 #endif 730 731 #define CONFIG_EXTRA_ENV_SETTINGS \ 732 HWCONFIG \ 733 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 734 "netdev=eth0\0" \ 735 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 736 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 737 "tftpflash=tftpboot $loadaddr $uboot && " \ 738 "protect off $ubootaddr +$filesize && " \ 739 "erase $ubootaddr +$filesize && " \ 740 "cp.b $loadaddr $ubootaddr $filesize && " \ 741 "protect on $ubootaddr +$filesize && " \ 742 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 743 "consoledev=ttyS0\0" \ 744 "ramdiskaddr=2000000\0" \ 745 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 746 "fdtaddr=1e00000\0" \ 747 "fdtfile=b4860qds/b4860qds.dtb\0" \ 748 "bdev=sda3\0" 749 750 /* For emulation this causes u-boot to jump to the start of the proof point 751 app code automatically */ 752 #define CONFIG_PROOF_POINTS \ 753 "setenv bootargs root=/dev/$bdev rw " \ 754 "console=$consoledev,$baudrate $othbootargs;" \ 755 "cpu 1 release 0x29000000 - - -;" \ 756 "cpu 2 release 0x29000000 - - -;" \ 757 "cpu 3 release 0x29000000 - - -;" \ 758 "cpu 4 release 0x29000000 - - -;" \ 759 "cpu 5 release 0x29000000 - - -;" \ 760 "cpu 6 release 0x29000000 - - -;" \ 761 "cpu 7 release 0x29000000 - - -;" \ 762 "go 0x29000000" 763 764 #define CONFIG_HVBOOT \ 765 "setenv bootargs config-addr=0x60000000; " \ 766 "bootm 0x01000000 - 0x00f00000" 767 768 #define CONFIG_ALU \ 769 "setenv bootargs root=/dev/$bdev rw " \ 770 "console=$consoledev,$baudrate $othbootargs;" \ 771 "cpu 1 release 0x01000000 - - -;" \ 772 "cpu 2 release 0x01000000 - - -;" \ 773 "cpu 3 release 0x01000000 - - -;" \ 774 "cpu 4 release 0x01000000 - - -;" \ 775 "cpu 5 release 0x01000000 - - -;" \ 776 "cpu 6 release 0x01000000 - - -;" \ 777 "cpu 7 release 0x01000000 - - -;" \ 778 "go 0x01000000" 779 780 #define CONFIG_LINUX \ 781 "setenv bootargs root=/dev/ram rw " \ 782 "console=$consoledev,$baudrate $othbootargs;" \ 783 "setenv ramdiskaddr 0x02000000;" \ 784 "setenv fdtaddr 0x01e00000;" \ 785 "setenv loadaddr 0x1000000;" \ 786 "bootm $loadaddr $ramdiskaddr $fdtaddr" 787 788 #define CONFIG_HDBOOT \ 789 "setenv bootargs root=/dev/$bdev rw " \ 790 "console=$consoledev,$baudrate $othbootargs;" \ 791 "tftp $loadaddr $bootfile;" \ 792 "tftp $fdtaddr $fdtfile;" \ 793 "bootm $loadaddr - $fdtaddr" 794 795 #define CONFIG_NFSBOOTCOMMAND \ 796 "setenv bootargs root=/dev/nfs rw " \ 797 "nfsroot=$serverip:$rootpath " \ 798 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 799 "console=$consoledev,$baudrate $othbootargs;" \ 800 "tftp $loadaddr $bootfile;" \ 801 "tftp $fdtaddr $fdtfile;" \ 802 "bootm $loadaddr - $fdtaddr" 803 804 #define CONFIG_RAMBOOTCOMMAND \ 805 "setenv bootargs root=/dev/ram rw " \ 806 "console=$consoledev,$baudrate $othbootargs;" \ 807 "tftp $ramdiskaddr $ramdiskfile;" \ 808 "tftp $loadaddr $bootfile;" \ 809 "tftp $fdtaddr $fdtfile;" \ 810 "bootm $loadaddr $ramdiskaddr $fdtaddr" 811 812 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 813 814 #include <asm/fsl_secure_boot.h> 815 816 #endif /* __CONFIG_H */ 817