1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * B4860 QDS board configuration file 28 */ 29 #define CONFIG_B4860QDS 30 #define CONFIG_PHYS_64BIT 31 32 #ifdef CONFIG_RAMBOOT_PBL 33 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 39 #define CONFIG_E6500 40 #define CONFIG_E500 /* BOOKE e500 family */ 41 #define CONFIG_E500MC /* BOOKE e500mc family */ 42 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 43 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 44 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 45 #define CONFIG_MP /* support multiple processors */ 46 47 #ifndef CONFIG_SYS_TEXT_BASE 48 #define CONFIG_SYS_TEXT_BASE 0xeff80000 49 #endif 50 51 #ifndef CONFIG_RESET_VECTOR_ADDRESS 52 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 53 #endif 54 55 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 56 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 57 #define CONFIG_FSL_IFC /* Enable IFC Support */ 58 #define CONFIG_PCI /* Enable PCI/PCIE */ 59 #define CONFIG_PCIE1 /* PCIE controler 1 */ 60 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 61 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 62 63 #ifndef CONFIG_PPC_B4420 64 #define CONFIG_SYS_SRIO 65 #define CONFIG_SRIO1 /* SRIO port 1 */ 66 #define CONFIG_SRIO2 /* SRIO port 2 */ 67 #endif 68 69 #define CONFIG_FSL_LAW /* Use common FSL init code */ 70 71 /* I2C bus multiplexer */ 72 #define I2C_MUX_PCA_ADDR 0x77 73 74 /* VSC Crossbar switches */ 75 #define CONFIG_VSC_CROSSBAR 76 #define I2C_CH_DEFAULT 0x8 77 #define I2C_CH_VSC3316 0xc 78 #define I2C_CH_VSC3308 0xd 79 80 #define VSC3316_TX_ADDRESS 0x70 81 #define VSC3316_RX_ADDRESS 0x71 82 #define VSC3308_TX_ADDRESS 0x02 83 #define VSC3308_RX_ADDRESS 0x03 84 85 #define CONFIG_ENV_OVERWRITE 86 87 #ifdef CONFIG_SYS_NO_FLASH 88 #define CONFIG_ENV_IS_NOWHERE 89 #else 90 #define CONFIG_FLASH_CFI_DRIVER 91 #define CONFIG_SYS_FLASH_CFI 92 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 93 #endif 94 95 #ifndef CONFIG_SYS_NO_FLASH 96 #if defined(CONFIG_SPIFLASH) 97 #define CONFIG_SYS_EXTRA_ENV_RELOC 98 #define CONFIG_ENV_IS_IN_SPI_FLASH 99 #define CONFIG_ENV_SPI_BUS 0 100 #define CONFIG_ENV_SPI_CS 0 101 #define CONFIG_ENV_SPI_MAX_HZ 10000000 102 #define CONFIG_ENV_SPI_MODE 0 103 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 104 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 105 #define CONFIG_ENV_SECT_SIZE 0x10000 106 #elif defined(CONFIG_SDCARD) 107 #define CONFIG_SYS_EXTRA_ENV_RELOC 108 #define CONFIG_ENV_IS_IN_MMC 109 #define CONFIG_SYS_MMC_ENV_DEV 0 110 #define CONFIG_ENV_SIZE 0x2000 111 #define CONFIG_ENV_OFFSET (512 * 1097) 112 #elif defined(CONFIG_NAND) 113 #define CONFIG_SYS_EXTRA_ENV_RELOC 114 #define CONFIG_ENV_IS_IN_NAND 115 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 116 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 117 #else 118 #define CONFIG_ENV_IS_IN_FLASH 119 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 120 #define CONFIG_ENV_SIZE 0x2000 121 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 122 #endif 123 #else /* CONFIG_SYS_NO_FLASH */ 124 #define CONFIG_ENV_SIZE 0x2000 125 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 126 #endif 127 128 #ifndef __ASSEMBLY__ 129 unsigned long get_board_sys_clk(void); 130 unsigned long get_board_ddr_clk(void); 131 #endif 132 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 133 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 134 135 /* 136 * These can be toggled for performance analysis, otherwise use default. 137 */ 138 #define CONFIG_SYS_CACHE_STASHING 139 #define CONFIG_BTB /* toggle branch predition */ 140 #define CONFIG_DDR_ECC 141 #ifdef CONFIG_DDR_ECC 142 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 143 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 144 #endif 145 146 #define CONFIG_ENABLE_36BIT_PHYS 147 148 #ifdef CONFIG_PHYS_64BIT 149 #define CONFIG_ADDR_MAP 150 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 151 #endif 152 153 #if 0 154 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 155 #endif 156 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 157 #define CONFIG_SYS_MEMTEST_END 0x00400000 158 #define CONFIG_SYS_ALT_MEMTEST 159 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 160 161 /* 162 * Config the L3 Cache as L3 SRAM 163 */ 164 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 165 166 #ifdef CONFIG_PHYS_64BIT 167 #define CONFIG_SYS_DCSRBAR 0xf0000000 168 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 169 #endif 170 171 /* EEPROM */ 172 #define CONFIG_SYS_I2C_EEPROM_NXID 173 #define CONFIG_SYS_EEPROM_BUS_NUM 0 174 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 175 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 176 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 177 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 178 179 /* 180 * DDR Setup 181 */ 182 #define CONFIG_VERY_BIG_RAM 183 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 184 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 185 186 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 187 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 188 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 189 190 #define CONFIG_DDR_SPD 191 #define CONFIG_SYS_DDR_RAW_TIMING 192 #define CONFIG_FSL_DDR3 193 #define CONFIG_FSL_DDR_INTERACTIVE 194 195 #define CONFIG_SYS_SPD_BUS_NUM 0 196 #define SPD_EEPROM_ADDRESS1 0x51 197 #define SPD_EEPROM_ADDRESS2 0x53 198 199 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 200 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 201 202 /* 203 * IFC Definitions 204 */ 205 #define CONFIG_SYS_FLASH_BASE 0xe0000000 206 #ifdef CONFIG_PHYS_64BIT 207 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 208 #else 209 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 210 #endif 211 212 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 213 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 214 + 0x8000000) | \ 215 CSPR_PORT_SIZE_16 | \ 216 CSPR_MSEL_NOR | \ 217 CSPR_V) 218 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 219 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 220 CSPR_PORT_SIZE_16 | \ 221 CSPR_MSEL_NOR | \ 222 CSPR_V) 223 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 224 /* NOR Flash Timing Params */ 225 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 226 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 227 FTIM0_NOR_TEADC(0x01) | \ 228 FTIM0_NOR_TEAHC(0x20)) 229 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 230 FTIM1_NOR_TRAD_NOR(0x1A) |\ 231 FTIM1_NOR_TSEQRAD_NOR(0x13)) 232 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 233 FTIM2_NOR_TCH(0x0E) | \ 234 FTIM2_NOR_TWPH(0x0E) | \ 235 FTIM2_NOR_TWP(0x1c)) 236 #define CONFIG_SYS_NOR_FTIM3 0x0 237 238 #define CONFIG_SYS_FLASH_QUIET_TEST 239 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 240 241 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 242 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 243 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 244 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 245 246 #define CONFIG_SYS_FLASH_EMPTY_INFO 247 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 248 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 249 250 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 251 #define CONFIG_FSL_QIXIS_V2 252 #define QIXIS_BASE 0xffdf0000 253 #ifdef CONFIG_PHYS_64BIT 254 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 255 #else 256 #define QIXIS_BASE_PHYS QIXIS_BASE 257 #endif 258 #define QIXIS_LBMAP_SWITCH 0x01 259 #define QIXIS_LBMAP_MASK 0x0f 260 #define QIXIS_LBMAP_SHIFT 0 261 #define QIXIS_LBMAP_DFLTBANK 0x00 262 #define QIXIS_LBMAP_ALTBANK 0x02 263 #define QIXIS_RST_CTL_RESET 0x31 264 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 265 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 266 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 267 268 #define CONFIG_SYS_CSPR3_EXT (0xf) 269 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 270 | CSPR_PORT_SIZE_8 \ 271 | CSPR_MSEL_GPCM \ 272 | CSPR_V) 273 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 274 #define CONFIG_SYS_CSOR3 0x0 275 /* QIXIS Timing parameters for IFC CS3 */ 276 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 277 FTIM0_GPCM_TEADC(0x0e) | \ 278 FTIM0_GPCM_TEAHC(0x0e)) 279 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 280 FTIM1_GPCM_TRAD(0x1f)) 281 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 282 FTIM2_GPCM_TCH(0x0) | \ 283 FTIM2_GPCM_TWP(0x1f)) 284 #define CONFIG_SYS_CS3_FTIM3 0x0 285 286 /* NAND Flash on IFC */ 287 #define CONFIG_NAND_FSL_IFC 288 #define CONFIG_SYS_NAND_BASE 0xff800000 289 #ifdef CONFIG_PHYS_64BIT 290 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 291 #else 292 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 293 #endif 294 295 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 296 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 297 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 298 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 299 | CSPR_V) 300 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 301 302 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 303 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 304 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 305 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 306 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 307 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 308 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 309 310 #define CONFIG_SYS_NAND_ONFI_DETECTION 311 312 /* ONFI NAND Flash mode0 Timing Params */ 313 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 314 FTIM0_NAND_TWP(0x18) | \ 315 FTIM0_NAND_TWCHT(0x07) | \ 316 FTIM0_NAND_TWH(0x0a)) 317 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 318 FTIM1_NAND_TWBE(0x39) | \ 319 FTIM1_NAND_TRR(0x0e) | \ 320 FTIM1_NAND_TRP(0x18)) 321 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 322 FTIM2_NAND_TREH(0x0a) | \ 323 FTIM2_NAND_TWHRE(0x1e)) 324 #define CONFIG_SYS_NAND_FTIM3 0x0 325 326 #define CONFIG_SYS_NAND_DDR_LAW 11 327 328 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 329 #define CONFIG_SYS_MAX_NAND_DEVICE 1 330 #define CONFIG_MTD_NAND_VERIFY_WRITE 331 #define CONFIG_CMD_NAND 332 333 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 334 335 #if defined(CONFIG_NAND) 336 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 337 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 338 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 339 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 340 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 341 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 342 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 343 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 344 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 345 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 346 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 347 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 348 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 349 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 350 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 351 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 352 #else 353 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 354 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 355 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 356 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 357 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 358 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 359 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 360 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 361 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 362 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 363 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 364 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 365 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 366 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 367 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 368 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 369 #endif 370 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 371 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 372 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 373 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 374 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 375 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 376 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 377 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 378 379 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 380 381 #if defined(CONFIG_RAMBOOT_PBL) 382 #define CONFIG_SYS_RAMBOOT 383 #endif 384 385 #define CONFIG_BOARD_EARLY_INIT_R 386 #define CONFIG_MISC_INIT_R 387 388 #define CONFIG_HWCONFIG 389 390 /* define to use L1 as initial stack */ 391 #define CONFIG_L1_INIT_RAM 392 #define CONFIG_SYS_INIT_RAM_LOCK 393 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 394 #ifdef CONFIG_PHYS_64BIT 395 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 396 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 397 /* The assembler doesn't like typecast */ 398 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 399 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 400 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 401 #else 402 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 403 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 404 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 405 #endif 406 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 407 408 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 409 GENERATED_GBL_DATA_SIZE) 410 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 411 412 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 413 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 414 415 /* Serial Port - controlled on board with jumper J8 416 * open - index 2 417 * shorted - index 1 418 */ 419 #define CONFIG_CONS_INDEX 1 420 #define CONFIG_SYS_NS16550 421 #define CONFIG_SYS_NS16550_SERIAL 422 #define CONFIG_SYS_NS16550_REG_SIZE 1 423 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 424 425 #define CONFIG_SYS_BAUDRATE_TABLE \ 426 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 427 428 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 429 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 430 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 431 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 432 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 433 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 434 435 436 /* Use the HUSH parser */ 437 #define CONFIG_SYS_HUSH_PARSER 438 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 439 440 /* pass open firmware flat tree */ 441 #define CONFIG_OF_LIBFDT 442 #define CONFIG_OF_BOARD_SETUP 443 #define CONFIG_OF_STDOUT_VIA_ALIAS 444 445 /* new uImage format support */ 446 #define CONFIG_FIT 447 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 448 449 /* I2C */ 450 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 451 #define CONFIG_HARD_I2C /* I2C with hardware support */ 452 #define CONFIG_I2C_MULTI_BUS 453 #define CONFIG_I2C_CMD_TREE 454 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed in Hz */ 455 #define CONFIG_SYS_I2C_SLAVE 0x7F 456 #define CONFIG_SYS_I2C_OFFSET 0x118000 457 #define CONFIG_SYS_I2C2_OFFSET 0x119000 458 459 /* 460 * RTC configuration 461 */ 462 #define RTC 463 #define CONFIG_RTC_DS3231 1 464 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 465 466 /* 467 * RapidIO 468 */ 469 #ifdef CONFIG_SYS_SRIO 470 #ifdef CONFIG_SRIO1 471 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 472 #ifdef CONFIG_PHYS_64BIT 473 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 474 #else 475 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 476 #endif 477 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 478 #endif 479 480 #ifdef CONFIG_SRIO2 481 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 482 #ifdef CONFIG_PHYS_64BIT 483 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 484 #else 485 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 486 #endif 487 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 488 #endif 489 #endif 490 491 /* 492 * for slave u-boot IMAGE instored in master memory space, 493 * PHYS must be aligned based on the SIZE 494 */ 495 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 496 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 497 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 498 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 499 /* 500 * for slave UCODE and ENV instored in master memory space, 501 * PHYS must be aligned based on the SIZE 502 */ 503 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 504 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 505 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 506 507 /* slave core release by master*/ 508 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 509 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 510 511 /* 512 * SRIO_PCIE_BOOT - SLAVE 513 */ 514 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 515 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 516 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 517 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 518 #endif 519 520 /* 521 * eSPI - Enhanced SPI 522 */ 523 #define CONFIG_FSL_ESPI 524 #define CONFIG_SPI_FLASH 525 #define CONFIG_SPI_FLASH_SST 526 #define CONFIG_CMD_SF 527 #define CONFIG_SF_DEFAULT_SPEED 10000000 528 #define CONFIG_SF_DEFAULT_MODE 0 529 530 /* 531 * General PCI 532 * Memory space is mapped 1-1, but I/O space must start from 0. 533 */ 534 535 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 536 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 537 #ifdef CONFIG_PHYS_64BIT 538 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 539 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 540 #else 541 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 542 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 543 #endif 544 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 545 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 546 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 547 #ifdef CONFIG_PHYS_64BIT 548 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 549 #else 550 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 551 #endif 552 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 553 554 /* Qman/Bman */ 555 #ifndef CONFIG_NOBQFMAN 556 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 557 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 558 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 559 #ifdef CONFIG_PHYS_64BIT 560 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 561 #else 562 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 563 #endif 564 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 565 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 566 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 567 #ifdef CONFIG_PHYS_64BIT 568 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 569 #else 570 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 571 #endif 572 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 573 574 #define CONFIG_SYS_DPAA_FMAN 575 576 /* Default address of microcode for the Linux Fman driver */ 577 #if defined(CONFIG_SPIFLASH) 578 /* 579 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 580 * env, so we got 0x110000. 581 */ 582 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 583 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 584 #elif defined(CONFIG_SDCARD) 585 /* 586 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 587 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 588 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 589 */ 590 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 591 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 592 #elif defined(CONFIG_NAND) 593 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 594 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 595 #else 596 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 597 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 598 #endif 599 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 600 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 601 #endif /* CONFIG_NOBQFMAN */ 602 603 #ifdef CONFIG_SYS_DPAA_FMAN 604 #define CONFIG_FMAN_ENET 605 #define CONFIG_PHYLIB_10G 606 #define CONFIG_PHY_VITESSE 607 #define CONFIG_PHY_TERANETICS 608 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 609 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 610 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 611 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 612 #endif 613 614 #ifdef CONFIG_PCI 615 #define CONFIG_NET_MULTI 616 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 617 #define CONFIG_E1000 618 619 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 620 #define CONFIG_DOS_PARTITION 621 #endif /* CONFIG_PCI */ 622 623 #ifdef CONFIG_FMAN_ENET 624 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 625 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 626 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 627 628 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 629 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 630 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 631 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 632 633 #define CONFIG_MII /* MII PHY management */ 634 #define CONFIG_ETHPRIME "FM1@DTSEC1" 635 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 636 #endif 637 638 /* 639 * Environment 640 */ 641 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 642 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 643 644 /* 645 * Command line configuration. 646 */ 647 #include <config_cmd_default.h> 648 649 #define CONFIG_CMD_DATE 650 #define CONFIG_CMD_DHCP 651 #define CONFIG_CMD_EEPROM 652 #define CONFIG_CMD_ELF 653 #define CONFIG_CMD_ERRATA 654 #define CONFIG_CMD_GREPENV 655 #define CONFIG_CMD_IRQ 656 #define CONFIG_CMD_I2C 657 #define CONFIG_CMD_MII 658 #define CONFIG_CMD_PING 659 #define CONFIG_CMD_REGINFO 660 #define CONFIG_CMD_SETEXPR 661 662 #ifdef CONFIG_PCI 663 #define CONFIG_CMD_PCI 664 #define CONFIG_CMD_NET 665 #endif 666 667 /* 668 * USB 669 */ 670 #define CONFIG_HAS_FSL_DR_USB 671 672 #ifdef CONFIG_HAS_FSL_DR_USB 673 #define CONFIG_USB_EHCI 674 675 #ifdef CONFIG_USB_EHCI 676 #define CONFIG_CMD_USB 677 #define CONFIG_USB_STORAGE 678 #define CONFIG_USB_EHCI_FSL 679 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 680 #define CONFIG_CMD_EXT2 681 #endif 682 #endif 683 684 /* 685 * Miscellaneous configurable options 686 */ 687 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 688 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 689 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 690 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 691 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 692 #ifdef CONFIG_CMD_KGDB 693 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 694 #else 695 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 696 #endif 697 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 698 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 699 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 700 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ 701 702 /* 703 * For booting Linux, the board info and command line data 704 * have to be in the first 64 MB of memory, since this is 705 * the maximum mapped by the Linux kernel during initialization. 706 */ 707 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 708 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 709 710 #ifdef CONFIG_CMD_KGDB 711 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 712 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 713 #endif 714 715 /* 716 * Environment Configuration 717 */ 718 #define CONFIG_ROOTPATH "/opt/nfsroot" 719 #define CONFIG_BOOTFILE "uImage" 720 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 721 722 /* default location for tftp and bootm */ 723 #define CONFIG_LOADADDR 1000000 724 725 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 726 727 #define CONFIG_BAUDRATE 115200 728 729 #define __USB_PHY_TYPE ulpi 730 731 #define CONFIG_EXTRA_ENV_SETTINGS \ 732 "hwconfig=fsl_ddr:ctlr_intlv=null," \ 733 "bank_intlv=cs0_cs1;" \ 734 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 735 "netdev=eth0\0" \ 736 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 737 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 738 "tftpflash=tftpboot $loadaddr $uboot && " \ 739 "protect off $ubootaddr +$filesize && " \ 740 "erase $ubootaddr +$filesize && " \ 741 "cp.b $loadaddr $ubootaddr $filesize && " \ 742 "protect on $ubootaddr +$filesize && " \ 743 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 744 "consoledev=ttyS0\0" \ 745 "ramdiskaddr=2000000\0" \ 746 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 747 "fdtaddr=c00000\0" \ 748 "fdtfile=b4860qds/b4860qds.dtb\0" \ 749 "bdev=sda3\0" \ 750 "c=ffe\0" 751 752 /* For emulation this causes u-boot to jump to the start of the proof point 753 app code automatically */ 754 #define CONFIG_PROOF_POINTS \ 755 "setenv bootargs root=/dev/$bdev rw " \ 756 "console=$consoledev,$baudrate $othbootargs;" \ 757 "cpu 1 release 0x29000000 - - -;" \ 758 "cpu 2 release 0x29000000 - - -;" \ 759 "cpu 3 release 0x29000000 - - -;" \ 760 "cpu 4 release 0x29000000 - - -;" \ 761 "cpu 5 release 0x29000000 - - -;" \ 762 "cpu 6 release 0x29000000 - - -;" \ 763 "cpu 7 release 0x29000000 - - -;" \ 764 "go 0x29000000" 765 766 #define CONFIG_HVBOOT \ 767 "setenv bootargs config-addr=0x60000000; " \ 768 "bootm 0x01000000 - 0x00f00000" 769 770 #define CONFIG_ALU \ 771 "setenv bootargs root=/dev/$bdev rw " \ 772 "console=$consoledev,$baudrate $othbootargs;" \ 773 "cpu 1 release 0x01000000 - - -;" \ 774 "cpu 2 release 0x01000000 - - -;" \ 775 "cpu 3 release 0x01000000 - - -;" \ 776 "cpu 4 release 0x01000000 - - -;" \ 777 "cpu 5 release 0x01000000 - - -;" \ 778 "cpu 6 release 0x01000000 - - -;" \ 779 "cpu 7 release 0x01000000 - - -;" \ 780 "go 0x01000000" 781 782 #define CONFIG_LINUX \ 783 "setenv bootargs root=/dev/ram rw " \ 784 "console=$consoledev,$baudrate $othbootargs;" \ 785 "setenv ramdiskaddr 0x02000000;" \ 786 "setenv fdtaddr 0x00c00000;" \ 787 "setenv loadaddr 0x1000000;" \ 788 "bootm $loadaddr $ramdiskaddr $fdtaddr" 789 790 #define CONFIG_HDBOOT \ 791 "setenv bootargs root=/dev/$bdev rw " \ 792 "console=$consoledev,$baudrate $othbootargs;" \ 793 "tftp $loadaddr $bootfile;" \ 794 "tftp $fdtaddr $fdtfile;" \ 795 "bootm $loadaddr - $fdtaddr" 796 797 #define CONFIG_NFSBOOTCOMMAND \ 798 "setenv bootargs root=/dev/nfs rw " \ 799 "nfsroot=$serverip:$rootpath " \ 800 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 801 "console=$consoledev,$baudrate $othbootargs;" \ 802 "tftp $loadaddr $bootfile;" \ 803 "tftp $fdtaddr $fdtfile;" \ 804 "bootm $loadaddr - $fdtaddr" 805 806 #define CONFIG_RAMBOOTCOMMAND \ 807 "setenv bootargs root=/dev/ram rw " \ 808 "console=$consoledev,$baudrate $othbootargs;" \ 809 "tftp $ramdiskaddr $ramdiskfile;" \ 810 "tftp $loadaddr $bootfile;" \ 811 "tftp $fdtaddr $fdtfile;" \ 812 "bootm $loadaddr $ramdiskaddr $fdtaddr" 813 814 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 815 816 #ifdef CONFIG_SECURE_BOOT 817 #include <asm/fsl_secure_boot.h> 818 #endif 819 820 #endif /* __CONFIG_H */ 821