1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * B4860 QDS board configuration file 12 */ 13 #ifdef CONFIG_RAMBOOT_PBL 14 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 15 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 16 #ifndef CONFIG_NAND 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #else 20 #define CONFIG_SPL_FLUSH_IMAGE 21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 22 #define CONFIG_SYS_TEXT_BASE 0x00201000 23 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 24 #define CONFIG_SPL_PAD_TO 0x40000 25 #define CONFIG_SPL_MAX_SIZE 0x28000 26 #define RESET_VECTOR_OFFSET 0x27FFC 27 #define BOOT_PAGE_OFFSET 0x27000 28 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 29 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 30 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 31 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 32 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 33 #define CONFIG_SPL_NAND_BOOT 34 #ifdef CONFIG_SPL_BUILD 35 #define CONFIG_SPL_SKIP_RELOCATE 36 #define CONFIG_SPL_COMMON_INIT_DDR 37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 38 #define CONFIG_SYS_NO_FLASH 39 #endif 40 #endif 41 #endif 42 43 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 44 /* Set 1M boot space */ 45 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 46 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 47 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 48 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 49 #define CONFIG_SYS_NO_FLASH 50 #endif 51 52 /* High Level Configuration Options */ 53 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 54 #define CONFIG_MP /* support multiple processors */ 55 56 #ifndef CONFIG_SYS_TEXT_BASE 57 #define CONFIG_SYS_TEXT_BASE 0xeff40000 58 #endif 59 60 #ifndef CONFIG_RESET_VECTOR_ADDRESS 61 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 62 #endif 63 64 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 65 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 66 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 67 #define CONFIG_PCIE1 /* PCIE controller 1 */ 68 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 69 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 70 71 #ifndef CONFIG_ARCH_B4420 72 #define CONFIG_SYS_SRIO 73 #define CONFIG_SRIO1 /* SRIO port 1 */ 74 #define CONFIG_SRIO2 /* SRIO port 2 */ 75 #define CONFIG_SRIO_PCIE_BOOT_MASTER 76 #endif 77 78 /* I2C bus multiplexer */ 79 #define I2C_MUX_PCA_ADDR 0x77 80 81 /* VSC Crossbar switches */ 82 #define CONFIG_VSC_CROSSBAR 83 #define I2C_CH_DEFAULT 0x8 84 #define I2C_CH_VSC3316 0xc 85 #define I2C_CH_VSC3308 0xd 86 87 #define VSC3316_TX_ADDRESS 0x70 88 #define VSC3316_RX_ADDRESS 0x71 89 #define VSC3308_TX_ADDRESS 0x02 90 #define VSC3308_RX_ADDRESS 0x03 91 92 /* IDT clock synthesizers */ 93 #define CONFIG_IDT8T49N222A 94 #define I2C_CH_IDT 0x9 95 96 #define IDT_SERDES1_ADDRESS 0x6E 97 #define IDT_SERDES2_ADDRESS 0x6C 98 99 /* Voltage monitor on channel 2*/ 100 #define I2C_MUX_CH_VOL_MONITOR 0xa 101 #define I2C_VOL_MONITOR_ADDR 0x40 102 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 103 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 104 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 105 106 #define CONFIG_ZM7300 107 #define I2C_MUX_CH_DPM 0xa 108 #define I2C_DPM_ADDR 0x28 109 110 #define CONFIG_ENV_OVERWRITE 111 112 #ifdef CONFIG_SYS_NO_FLASH 113 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 114 #define CONFIG_ENV_IS_NOWHERE 115 #endif 116 #else 117 #define CONFIG_FLASH_CFI_DRIVER 118 #define CONFIG_SYS_FLASH_CFI 119 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 120 #endif 121 122 #if defined(CONFIG_SPIFLASH) 123 #define CONFIG_SYS_EXTRA_ENV_RELOC 124 #define CONFIG_ENV_IS_IN_SPI_FLASH 125 #define CONFIG_ENV_SPI_BUS 0 126 #define CONFIG_ENV_SPI_CS 0 127 #define CONFIG_ENV_SPI_MAX_HZ 10000000 128 #define CONFIG_ENV_SPI_MODE 0 129 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 130 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 131 #define CONFIG_ENV_SECT_SIZE 0x10000 132 #elif defined(CONFIG_SDCARD) 133 #define CONFIG_SYS_EXTRA_ENV_RELOC 134 #define CONFIG_ENV_IS_IN_MMC 135 #define CONFIG_SYS_MMC_ENV_DEV 0 136 #define CONFIG_ENV_SIZE 0x2000 137 #define CONFIG_ENV_OFFSET (512 * 1097) 138 #elif defined(CONFIG_NAND) 139 #define CONFIG_SYS_EXTRA_ENV_RELOC 140 #define CONFIG_ENV_IS_IN_NAND 141 #define CONFIG_ENV_SIZE 0x2000 142 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 143 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 144 #define CONFIG_ENV_IS_IN_REMOTE 145 #define CONFIG_ENV_ADDR 0xffe20000 146 #define CONFIG_ENV_SIZE 0x2000 147 #elif defined(CONFIG_ENV_IS_NOWHERE) 148 #define CONFIG_ENV_SIZE 0x2000 149 #else 150 #define CONFIG_ENV_IS_IN_FLASH 151 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 152 #define CONFIG_ENV_SIZE 0x2000 153 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 154 #endif 155 156 #ifndef __ASSEMBLY__ 157 unsigned long get_board_sys_clk(void); 158 unsigned long get_board_ddr_clk(void); 159 #endif 160 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 161 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 162 163 /* 164 * These can be toggled for performance analysis, otherwise use default. 165 */ 166 #define CONFIG_SYS_CACHE_STASHING 167 #define CONFIG_BTB /* toggle branch predition */ 168 #define CONFIG_DDR_ECC 169 #ifdef CONFIG_DDR_ECC 170 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 171 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 172 #endif 173 174 #define CONFIG_ENABLE_36BIT_PHYS 175 176 #ifdef CONFIG_PHYS_64BIT 177 #define CONFIG_ADDR_MAP 178 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 179 #endif 180 181 #if 0 182 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 183 #endif 184 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 185 #define CONFIG_SYS_MEMTEST_END 0x00400000 186 #define CONFIG_SYS_ALT_MEMTEST 187 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 188 189 /* 190 * Config the L3 Cache as L3 SRAM 191 */ 192 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 193 #define CONFIG_SYS_L3_SIZE 256 << 10 194 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 195 #ifdef CONFIG_NAND 196 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 197 #endif 198 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 199 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 200 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 201 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 202 203 #ifdef CONFIG_PHYS_64BIT 204 #define CONFIG_SYS_DCSRBAR 0xf0000000 205 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 206 #endif 207 208 /* EEPROM */ 209 #define CONFIG_ID_EEPROM 210 #define CONFIG_SYS_I2C_EEPROM_NXID 211 #define CONFIG_SYS_EEPROM_BUS_NUM 0 212 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 213 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 214 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 216 217 /* 218 * DDR Setup 219 */ 220 #define CONFIG_VERY_BIG_RAM 221 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 222 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 223 224 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 225 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 226 227 #define CONFIG_DDR_SPD 228 #define CONFIG_SYS_DDR_RAW_TIMING 229 #ifndef CONFIG_SPL_BUILD 230 #define CONFIG_FSL_DDR_INTERACTIVE 231 #endif 232 233 #define CONFIG_SYS_SPD_BUS_NUM 0 234 #define SPD_EEPROM_ADDRESS1 0x51 235 #define SPD_EEPROM_ADDRESS2 0x53 236 237 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 238 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 239 240 /* 241 * IFC Definitions 242 */ 243 #define CONFIG_SYS_FLASH_BASE 0xe0000000 244 #ifdef CONFIG_PHYS_64BIT 245 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 246 #else 247 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 248 #endif 249 250 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 251 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 252 + 0x8000000) | \ 253 CSPR_PORT_SIZE_16 | \ 254 CSPR_MSEL_NOR | \ 255 CSPR_V) 256 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 257 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 258 CSPR_PORT_SIZE_16 | \ 259 CSPR_MSEL_NOR | \ 260 CSPR_V) 261 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 262 /* NOR Flash Timing Params */ 263 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 264 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 265 FTIM0_NOR_TEADC(0x04) | \ 266 FTIM0_NOR_TEAHC(0x20)) 267 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 268 FTIM1_NOR_TRAD_NOR(0x1A) |\ 269 FTIM1_NOR_TSEQRAD_NOR(0x13)) 270 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 271 FTIM2_NOR_TCH(0x0E) | \ 272 FTIM2_NOR_TWPH(0x0E) | \ 273 FTIM2_NOR_TWP(0x1c)) 274 #define CONFIG_SYS_NOR_FTIM3 0x0 275 276 #define CONFIG_SYS_FLASH_QUIET_TEST 277 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 278 279 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 280 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 281 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 282 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 283 284 #define CONFIG_SYS_FLASH_EMPTY_INFO 285 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 286 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 287 288 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 289 #define CONFIG_FSL_QIXIS_V2 290 #define QIXIS_BASE 0xffdf0000 291 #ifdef CONFIG_PHYS_64BIT 292 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 293 #else 294 #define QIXIS_BASE_PHYS QIXIS_BASE 295 #endif 296 #define QIXIS_LBMAP_SWITCH 0x01 297 #define QIXIS_LBMAP_MASK 0x0f 298 #define QIXIS_LBMAP_SHIFT 0 299 #define QIXIS_LBMAP_DFLTBANK 0x00 300 #define QIXIS_LBMAP_ALTBANK 0x02 301 #define QIXIS_RST_CTL_RESET 0x31 302 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 303 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 304 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 305 306 #define CONFIG_SYS_CSPR3_EXT (0xf) 307 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 308 | CSPR_PORT_SIZE_8 \ 309 | CSPR_MSEL_GPCM \ 310 | CSPR_V) 311 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 312 #define CONFIG_SYS_CSOR3 0x0 313 /* QIXIS Timing parameters for IFC CS3 */ 314 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 315 FTIM0_GPCM_TEADC(0x0e) | \ 316 FTIM0_GPCM_TEAHC(0x0e)) 317 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 318 FTIM1_GPCM_TRAD(0x1f)) 319 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 320 FTIM2_GPCM_TCH(0x8) | \ 321 FTIM2_GPCM_TWP(0x1f)) 322 #define CONFIG_SYS_CS3_FTIM3 0x0 323 324 /* NAND Flash on IFC */ 325 #define CONFIG_NAND_FSL_IFC 326 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 327 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 328 #define CONFIG_SYS_NAND_BASE 0xff800000 329 #ifdef CONFIG_PHYS_64BIT 330 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 331 #else 332 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 333 #endif 334 335 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 336 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 337 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 338 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 339 | CSPR_V) 340 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 341 342 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 343 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 344 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 345 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 346 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 347 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 348 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 349 350 #define CONFIG_SYS_NAND_ONFI_DETECTION 351 352 /* ONFI NAND Flash mode0 Timing Params */ 353 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 354 FTIM0_NAND_TWP(0x18) | \ 355 FTIM0_NAND_TWCHT(0x07) | \ 356 FTIM0_NAND_TWH(0x0a)) 357 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 358 FTIM1_NAND_TWBE(0x39) | \ 359 FTIM1_NAND_TRR(0x0e) | \ 360 FTIM1_NAND_TRP(0x18)) 361 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 362 FTIM2_NAND_TREH(0x0a) | \ 363 FTIM2_NAND_TWHRE(0x1e)) 364 #define CONFIG_SYS_NAND_FTIM3 0x0 365 366 #define CONFIG_SYS_NAND_DDR_LAW 11 367 368 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 369 #define CONFIG_SYS_MAX_NAND_DEVICE 1 370 #define CONFIG_CMD_NAND 371 372 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 373 374 #if defined(CONFIG_NAND) 375 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 376 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 377 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 378 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 379 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 380 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 381 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 382 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 383 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 384 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 385 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 386 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 387 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 388 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 389 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 390 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 391 #else 392 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 393 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 394 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 395 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 396 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 397 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 398 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 399 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 400 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 401 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 402 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 403 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 404 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 405 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 406 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 407 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 408 #endif 409 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 410 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 411 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 412 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 413 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 414 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 415 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 416 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 417 418 #ifdef CONFIG_SPL_BUILD 419 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 420 #else 421 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 422 #endif 423 424 #if defined(CONFIG_RAMBOOT_PBL) 425 #define CONFIG_SYS_RAMBOOT 426 #endif 427 428 #define CONFIG_BOARD_EARLY_INIT_R 429 #define CONFIG_MISC_INIT_R 430 431 #define CONFIG_HWCONFIG 432 433 /* define to use L1 as initial stack */ 434 #define CONFIG_L1_INIT_RAM 435 #define CONFIG_SYS_INIT_RAM_LOCK 436 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 437 #ifdef CONFIG_PHYS_64BIT 438 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 439 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 440 /* The assembler doesn't like typecast */ 441 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 442 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 443 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 444 #else 445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 446 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 447 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 448 #endif 449 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 450 451 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 452 GENERATED_GBL_DATA_SIZE) 453 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 454 455 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 456 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 457 458 /* Serial Port - controlled on board with jumper J8 459 * open - index 2 460 * shorted - index 1 461 */ 462 #define CONFIG_CONS_INDEX 1 463 #define CONFIG_SYS_NS16550_SERIAL 464 #define CONFIG_SYS_NS16550_REG_SIZE 1 465 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 466 467 #define CONFIG_SYS_BAUDRATE_TABLE \ 468 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 469 470 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 471 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 472 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 473 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 474 475 /* I2C */ 476 #define CONFIG_SYS_I2C 477 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 478 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 479 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 480 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 481 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 482 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 483 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 484 485 /* 486 * RTC configuration 487 */ 488 #define RTC 489 #define CONFIG_RTC_DS3231 1 490 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 491 492 /* 493 * RapidIO 494 */ 495 #ifdef CONFIG_SYS_SRIO 496 #ifdef CONFIG_SRIO1 497 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 498 #ifdef CONFIG_PHYS_64BIT 499 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 500 #else 501 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 502 #endif 503 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 504 #endif 505 506 #ifdef CONFIG_SRIO2 507 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 508 #ifdef CONFIG_PHYS_64BIT 509 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 510 #else 511 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 512 #endif 513 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 514 #endif 515 #endif 516 517 /* 518 * for slave u-boot IMAGE instored in master memory space, 519 * PHYS must be aligned based on the SIZE 520 */ 521 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 522 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 523 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 524 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 525 /* 526 * for slave UCODE and ENV instored in master memory space, 527 * PHYS must be aligned based on the SIZE 528 */ 529 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 530 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 531 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 532 533 /* slave core release by master*/ 534 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 535 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 536 537 /* 538 * SRIO_PCIE_BOOT - SLAVE 539 */ 540 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 541 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 542 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 543 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 544 #endif 545 546 /* 547 * eSPI - Enhanced SPI 548 */ 549 #define CONFIG_SF_DEFAULT_SPEED 10000000 550 #define CONFIG_SF_DEFAULT_MODE 0 551 552 /* 553 * MAPLE 554 */ 555 #ifdef CONFIG_PHYS_64BIT 556 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 557 #else 558 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 559 #endif 560 561 /* 562 * General PCI 563 * Memory space is mapped 1-1, but I/O space must start from 0. 564 */ 565 566 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 567 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 568 #ifdef CONFIG_PHYS_64BIT 569 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 570 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 571 #else 572 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 573 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 574 #endif 575 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 576 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 577 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 578 #ifdef CONFIG_PHYS_64BIT 579 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 580 #else 581 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 582 #endif 583 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 584 585 /* Qman/Bman */ 586 #ifndef CONFIG_NOBQFMAN 587 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 588 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 589 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 590 #ifdef CONFIG_PHYS_64BIT 591 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 592 #else 593 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 594 #endif 595 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 596 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 597 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 598 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 599 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 600 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 601 CONFIG_SYS_BMAN_CENA_SIZE) 602 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 603 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 604 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 605 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 606 #ifdef CONFIG_PHYS_64BIT 607 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 608 #else 609 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 610 #endif 611 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 612 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 613 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 614 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 615 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 616 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 617 CONFIG_SYS_QMAN_CENA_SIZE) 618 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 619 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 620 621 #define CONFIG_SYS_DPAA_FMAN 622 623 #define CONFIG_SYS_DPAA_RMAN 624 625 /* Default address of microcode for the Linux Fman driver */ 626 #if defined(CONFIG_SPIFLASH) 627 /* 628 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 629 * env, so we got 0x110000. 630 */ 631 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 632 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 633 #elif defined(CONFIG_SDCARD) 634 /* 635 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 636 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 637 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 638 */ 639 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 640 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 641 #elif defined(CONFIG_NAND) 642 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 643 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 644 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 645 /* 646 * Slave has no ucode locally, it can fetch this from remote. When implementing 647 * in two corenet boards, slave's ucode could be stored in master's memory 648 * space, the address can be mapped from slave TLB->slave LAW-> 649 * slave SRIO or PCIE outbound window->master inbound window-> 650 * master LAW->the ucode address in master's memory space. 651 */ 652 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 653 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 654 #else 655 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 656 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 657 #endif 658 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 659 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 660 #endif /* CONFIG_NOBQFMAN */ 661 662 #ifdef CONFIG_SYS_DPAA_FMAN 663 #define CONFIG_FMAN_ENET 664 #define CONFIG_PHYLIB_10G 665 #define CONFIG_PHY_VITESSE 666 #define CONFIG_PHY_TERANETICS 667 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 668 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 669 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 670 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 671 #endif 672 673 #ifdef CONFIG_PCI 674 #define CONFIG_PCI_INDIRECT_BRIDGE 675 676 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 677 #endif /* CONFIG_PCI */ 678 679 #ifdef CONFIG_FMAN_ENET 680 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 681 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 682 683 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 684 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 685 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 686 687 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 688 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 689 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 690 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 691 692 #define CONFIG_MII /* MII PHY management */ 693 #define CONFIG_ETHPRIME "FM1@DTSEC1" 694 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 695 #endif 696 697 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR 698 699 /* 700 * Environment 701 */ 702 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 703 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 704 705 /* 706 * Command line configuration. 707 */ 708 #define CONFIG_CMD_DATE 709 #define CONFIG_CMD_EEPROM 710 #define CONFIG_CMD_ERRATA 711 #define CONFIG_CMD_IRQ 712 #define CONFIG_CMD_REGINFO 713 714 #ifdef CONFIG_PCI 715 #define CONFIG_CMD_PCI 716 #endif 717 718 /* Hash command with SHA acceleration supported in hardware */ 719 #ifdef CONFIG_FSL_CAAM 720 #define CONFIG_CMD_HASH 721 #define CONFIG_SHA_HW_ACCEL 722 #endif 723 724 /* 725 * USB 726 */ 727 #define CONFIG_HAS_FSL_DR_USB 728 729 #ifdef CONFIG_HAS_FSL_DR_USB 730 #define CONFIG_USB_EHCI 731 732 #ifdef CONFIG_USB_EHCI 733 #define CONFIG_USB_EHCI_FSL 734 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 735 #endif 736 #endif 737 738 /* 739 * Miscellaneous configurable options 740 */ 741 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 742 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 743 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 744 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 745 #ifdef CONFIG_CMD_KGDB 746 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 747 #else 748 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 749 #endif 750 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 751 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 752 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 753 754 /* 755 * For booting Linux, the board info and command line data 756 * have to be in the first 64 MB of memory, since this is 757 * the maximum mapped by the Linux kernel during initialization. 758 */ 759 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 760 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 761 762 #ifdef CONFIG_CMD_KGDB 763 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 764 #endif 765 766 /* 767 * Environment Configuration 768 */ 769 #define CONFIG_ROOTPATH "/opt/nfsroot" 770 #define CONFIG_BOOTFILE "uImage" 771 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 772 773 /* default location for tftp and bootm */ 774 #define CONFIG_LOADADDR 1000000 775 776 777 #define CONFIG_BAUDRATE 115200 778 779 #define __USB_PHY_TYPE ulpi 780 781 #ifdef CONFIG_ARCH_B4860 782 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 783 "bank_intlv=cs0_cs1;" \ 784 "en_cpc:cpc2;" 785 #else 786 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 787 #endif 788 789 #define CONFIG_EXTRA_ENV_SETTINGS \ 790 HWCONFIG \ 791 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 792 "netdev=eth0\0" \ 793 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 794 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 795 "tftpflash=tftpboot $loadaddr $uboot && " \ 796 "protect off $ubootaddr +$filesize && " \ 797 "erase $ubootaddr +$filesize && " \ 798 "cp.b $loadaddr $ubootaddr $filesize && " \ 799 "protect on $ubootaddr +$filesize && " \ 800 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 801 "consoledev=ttyS0\0" \ 802 "ramdiskaddr=2000000\0" \ 803 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 804 "fdtaddr=1e00000\0" \ 805 "fdtfile=b4860qds/b4860qds.dtb\0" \ 806 "bdev=sda3\0" 807 808 /* For emulation this causes u-boot to jump to the start of the proof point 809 app code automatically */ 810 #define CONFIG_PROOF_POINTS \ 811 "setenv bootargs root=/dev/$bdev rw " \ 812 "console=$consoledev,$baudrate $othbootargs;" \ 813 "cpu 1 release 0x29000000 - - -;" \ 814 "cpu 2 release 0x29000000 - - -;" \ 815 "cpu 3 release 0x29000000 - - -;" \ 816 "cpu 4 release 0x29000000 - - -;" \ 817 "cpu 5 release 0x29000000 - - -;" \ 818 "cpu 6 release 0x29000000 - - -;" \ 819 "cpu 7 release 0x29000000 - - -;" \ 820 "go 0x29000000" 821 822 #define CONFIG_HVBOOT \ 823 "setenv bootargs config-addr=0x60000000; " \ 824 "bootm 0x01000000 - 0x00f00000" 825 826 #define CONFIG_ALU \ 827 "setenv bootargs root=/dev/$bdev rw " \ 828 "console=$consoledev,$baudrate $othbootargs;" \ 829 "cpu 1 release 0x01000000 - - -;" \ 830 "cpu 2 release 0x01000000 - - -;" \ 831 "cpu 3 release 0x01000000 - - -;" \ 832 "cpu 4 release 0x01000000 - - -;" \ 833 "cpu 5 release 0x01000000 - - -;" \ 834 "cpu 6 release 0x01000000 - - -;" \ 835 "cpu 7 release 0x01000000 - - -;" \ 836 "go 0x01000000" 837 838 #define CONFIG_LINUX \ 839 "setenv bootargs root=/dev/ram rw " \ 840 "console=$consoledev,$baudrate $othbootargs;" \ 841 "setenv ramdiskaddr 0x02000000;" \ 842 "setenv fdtaddr 0x01e00000;" \ 843 "setenv loadaddr 0x1000000;" \ 844 "bootm $loadaddr $ramdiskaddr $fdtaddr" 845 846 #define CONFIG_HDBOOT \ 847 "setenv bootargs root=/dev/$bdev rw " \ 848 "console=$consoledev,$baudrate $othbootargs;" \ 849 "tftp $loadaddr $bootfile;" \ 850 "tftp $fdtaddr $fdtfile;" \ 851 "bootm $loadaddr - $fdtaddr" 852 853 #define CONFIG_NFSBOOTCOMMAND \ 854 "setenv bootargs root=/dev/nfs rw " \ 855 "nfsroot=$serverip:$rootpath " \ 856 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 857 "console=$consoledev,$baudrate $othbootargs;" \ 858 "tftp $loadaddr $bootfile;" \ 859 "tftp $fdtaddr $fdtfile;" \ 860 "bootm $loadaddr - $fdtaddr" 861 862 #define CONFIG_RAMBOOTCOMMAND \ 863 "setenv bootargs root=/dev/ram rw " \ 864 "console=$consoledev,$baudrate $othbootargs;" \ 865 "tftp $ramdiskaddr $ramdiskfile;" \ 866 "tftp $loadaddr $bootfile;" \ 867 "tftp $fdtaddr $fdtfile;" \ 868 "bootm $loadaddr $ramdiskaddr $fdtaddr" 869 870 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 871 872 #include <asm/fsl_secure_boot.h> 873 874 #endif /* __CONFIG_H */ 875