1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * B4860 QDS board configuration file 28 */ 29 #define CONFIG_B4860QDS 30 #define CONFIG_PHYS_64BIT 31 32 #ifdef CONFIG_RAMBOOT_PBL 33 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 39 #define CONFIG_E500 /* BOOKE e500 family */ 40 #define CONFIG_E500MC /* BOOKE e500mc family */ 41 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 42 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 43 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 44 #define CONFIG_MP /* support multiple processors */ 45 46 #ifndef CONFIG_SYS_TEXT_BASE 47 #define CONFIG_SYS_TEXT_BASE 0xeff80000 48 #endif 49 50 #ifndef CONFIG_RESET_VECTOR_ADDRESS 51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 52 #endif 53 54 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 55 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 56 #define CONFIG_FSL_IFC /* Enable IFC Support */ 57 #define CONFIG_PCI /* Enable PCI/PCIE */ 58 #define CONFIG_PCIE1 /* PCIE controler 1 */ 59 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 60 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 61 62 #ifndef CONFIG_PPC_B4420 63 #define CONFIG_SYS_SRIO 64 #define CONFIG_SRIO1 /* SRIO port 1 */ 65 #define CONFIG_SRIO2 /* SRIO port 2 */ 66 #endif 67 68 #define CONFIG_FSL_LAW /* Use common FSL init code */ 69 70 /* I2C bus multiplexer */ 71 #define I2C_MUX_PCA_ADDR 0x77 72 73 /* VSC Crossbar switches */ 74 #define CONFIG_VSC_CROSSBAR 75 #define I2C_CH_DEFAULT 0x8 76 #define I2C_CH_VSC3316 0xc 77 #define I2C_CH_VSC3308 0xd 78 79 #define VSC3316_TX_ADDRESS 0x70 80 #define VSC3316_RX_ADDRESS 0x71 81 #define VSC3308_TX_ADDRESS 0x02 82 #define VSC3308_RX_ADDRESS 0x03 83 84 #define CONFIG_ENV_OVERWRITE 85 86 #ifdef CONFIG_SYS_NO_FLASH 87 #define CONFIG_ENV_IS_NOWHERE 88 #else 89 #define CONFIG_FLASH_CFI_DRIVER 90 #define CONFIG_SYS_FLASH_CFI 91 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 92 #endif 93 94 #ifndef CONFIG_SYS_NO_FLASH 95 #if defined(CONFIG_SPIFLASH) 96 #define CONFIG_SYS_EXTRA_ENV_RELOC 97 #define CONFIG_ENV_IS_IN_SPI_FLASH 98 #define CONFIG_ENV_SPI_BUS 0 99 #define CONFIG_ENV_SPI_CS 0 100 #define CONFIG_ENV_SPI_MAX_HZ 10000000 101 #define CONFIG_ENV_SPI_MODE 0 102 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 103 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 104 #define CONFIG_ENV_SECT_SIZE 0x10000 105 #elif defined(CONFIG_SDCARD) 106 #define CONFIG_SYS_EXTRA_ENV_RELOC 107 #define CONFIG_ENV_IS_IN_MMC 108 #define CONFIG_SYS_MMC_ENV_DEV 0 109 #define CONFIG_ENV_SIZE 0x2000 110 #define CONFIG_ENV_OFFSET (512 * 1097) 111 #elif defined(CONFIG_NAND) 112 #define CONFIG_SYS_EXTRA_ENV_RELOC 113 #define CONFIG_ENV_IS_IN_NAND 114 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 115 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 116 #else 117 #define CONFIG_ENV_IS_IN_FLASH 118 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 119 #define CONFIG_ENV_SIZE 0x2000 120 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 121 #endif 122 #else /* CONFIG_SYS_NO_FLASH */ 123 #define CONFIG_ENV_SIZE 0x2000 124 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 125 #endif 126 127 #ifndef __ASSEMBLY__ 128 unsigned long get_board_sys_clk(void); 129 unsigned long get_board_ddr_clk(void); 130 #endif 131 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 132 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 133 134 /* 135 * These can be toggled for performance analysis, otherwise use default. 136 */ 137 #define CONFIG_SYS_CACHE_STASHING 138 #define CONFIG_BTB /* toggle branch predition */ 139 #define CONFIG_DDR_ECC 140 #ifdef CONFIG_DDR_ECC 141 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 142 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 143 #endif 144 145 #define CONFIG_ENABLE_36BIT_PHYS 146 147 #ifdef CONFIG_PHYS_64BIT 148 #define CONFIG_ADDR_MAP 149 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 150 #endif 151 152 #if 0 153 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 154 #endif 155 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 156 #define CONFIG_SYS_MEMTEST_END 0x00400000 157 #define CONFIG_SYS_ALT_MEMTEST 158 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 159 160 /* 161 * Config the L3 Cache as L3 SRAM 162 */ 163 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 164 165 #ifdef CONFIG_PHYS_64BIT 166 #define CONFIG_SYS_DCSRBAR 0xf0000000 167 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 168 #endif 169 170 /* EEPROM */ 171 #define CONFIG_SYS_I2C_EEPROM_NXID 172 #define CONFIG_SYS_EEPROM_BUS_NUM 0 173 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 174 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 175 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 176 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 177 178 /* 179 * DDR Setup 180 */ 181 #define CONFIG_VERY_BIG_RAM 182 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 183 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 184 185 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 186 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 187 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 188 189 #define CONFIG_DDR_SPD 190 #define CONFIG_SYS_DDR_RAW_TIMING 191 #define CONFIG_FSL_DDR3 192 #define CONFIG_FSL_DDR_INTERACTIVE 193 194 #define CONFIG_SYS_SPD_BUS_NUM 0 195 #define SPD_EEPROM_ADDRESS1 0x51 196 #define SPD_EEPROM_ADDRESS2 0x53 197 198 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 199 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 200 201 /* 202 * IFC Definitions 203 */ 204 #define CONFIG_SYS_FLASH_BASE 0xe0000000 205 #ifdef CONFIG_PHYS_64BIT 206 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 207 #else 208 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 209 #endif 210 211 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 212 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 213 + 0x8000000) | \ 214 CSPR_PORT_SIZE_16 | \ 215 CSPR_MSEL_NOR | \ 216 CSPR_V) 217 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 218 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 219 CSPR_PORT_SIZE_16 | \ 220 CSPR_MSEL_NOR | \ 221 CSPR_V) 222 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 223 /* NOR Flash Timing Params */ 224 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 225 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 226 FTIM0_NOR_TEADC(0x01) | \ 227 FTIM0_NOR_TEAHC(0x20)) 228 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 229 FTIM1_NOR_TRAD_NOR(0x1A) |\ 230 FTIM1_NOR_TSEQRAD_NOR(0x13)) 231 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 232 FTIM2_NOR_TCH(0x0E) | \ 233 FTIM2_NOR_TWPH(0x0E) | \ 234 FTIM2_NOR_TWP(0x1c)) 235 #define CONFIG_SYS_NOR_FTIM3 0x0 236 237 #define CONFIG_SYS_FLASH_QUIET_TEST 238 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 239 240 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 241 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 242 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 243 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 244 245 #define CONFIG_SYS_FLASH_EMPTY_INFO 246 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 247 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 248 249 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 250 #define CONFIG_FSL_QIXIS_V2 251 #define QIXIS_BASE 0xffdf0000 252 #ifdef CONFIG_PHYS_64BIT 253 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 254 #else 255 #define QIXIS_BASE_PHYS QIXIS_BASE 256 #endif 257 #define QIXIS_LBMAP_SWITCH 0x01 258 #define QIXIS_LBMAP_MASK 0x0f 259 #define QIXIS_LBMAP_SHIFT 0 260 #define QIXIS_LBMAP_DFLTBANK 0x00 261 #define QIXIS_LBMAP_ALTBANK 0x02 262 #define QIXIS_RST_CTL_RESET 0x31 263 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 264 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 265 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 266 267 #define CONFIG_SYS_CSPR3_EXT (0xf) 268 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 269 | CSPR_PORT_SIZE_8 \ 270 | CSPR_MSEL_GPCM \ 271 | CSPR_V) 272 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 273 #define CONFIG_SYS_CSOR3 0x0 274 /* QIXIS Timing parameters for IFC CS3 */ 275 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 276 FTIM0_GPCM_TEADC(0x0e) | \ 277 FTIM0_GPCM_TEAHC(0x0e)) 278 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 279 FTIM1_GPCM_TRAD(0x1f)) 280 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 281 FTIM2_GPCM_TCH(0x0) | \ 282 FTIM2_GPCM_TWP(0x1f)) 283 #define CONFIG_SYS_CS3_FTIM3 0x0 284 285 /* NAND Flash on IFC */ 286 #define CONFIG_NAND_FSL_IFC 287 #define CONFIG_SYS_NAND_BASE 0xff800000 288 #ifdef CONFIG_PHYS_64BIT 289 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 290 #else 291 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 292 #endif 293 294 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 295 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 296 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 297 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 298 | CSPR_V) 299 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 300 301 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 302 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 303 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 304 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 305 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 306 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 307 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 308 309 #define CONFIG_SYS_NAND_ONFI_DETECTION 310 311 /* ONFI NAND Flash mode0 Timing Params */ 312 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 313 FTIM0_NAND_TWP(0x18) | \ 314 FTIM0_NAND_TWCHT(0x07) | \ 315 FTIM0_NAND_TWH(0x0a)) 316 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 317 FTIM1_NAND_TWBE(0x39) | \ 318 FTIM1_NAND_TRR(0x0e) | \ 319 FTIM1_NAND_TRP(0x18)) 320 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 321 FTIM2_NAND_TREH(0x0a) | \ 322 FTIM2_NAND_TWHRE(0x1e)) 323 #define CONFIG_SYS_NAND_FTIM3 0x0 324 325 #define CONFIG_SYS_NAND_DDR_LAW 11 326 327 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 328 #define CONFIG_SYS_MAX_NAND_DEVICE 1 329 #define CONFIG_MTD_NAND_VERIFY_WRITE 330 #define CONFIG_CMD_NAND 331 332 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 333 334 #if defined(CONFIG_NAND) 335 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 336 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 337 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 338 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 339 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 340 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 341 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 342 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 343 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 344 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 345 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 346 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 347 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 348 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 349 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 350 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 351 #else 352 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 353 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 354 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 355 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 356 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 357 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 358 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 359 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 360 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 361 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 362 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 363 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 364 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 365 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 366 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 367 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 368 #endif 369 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 370 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 371 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 372 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 373 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 374 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 375 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 376 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 377 378 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 379 380 #if defined(CONFIG_RAMBOOT_PBL) 381 #define CONFIG_SYS_RAMBOOT 382 #endif 383 384 #define CONFIG_BOARD_EARLY_INIT_R 385 #define CONFIG_MISC_INIT_R 386 387 #define CONFIG_HWCONFIG 388 389 /* define to use L1 as initial stack */ 390 #define CONFIG_L1_INIT_RAM 391 #define CONFIG_SYS_INIT_RAM_LOCK 392 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 393 #ifdef CONFIG_PHYS_64BIT 394 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 395 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 396 /* The assembler doesn't like typecast */ 397 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 398 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 399 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 400 #else 401 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 402 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 403 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 404 #endif 405 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 406 407 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 408 GENERATED_GBL_DATA_SIZE) 409 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 410 411 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 412 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 413 414 /* Serial Port - controlled on board with jumper J8 415 * open - index 2 416 * shorted - index 1 417 */ 418 #define CONFIG_CONS_INDEX 1 419 #define CONFIG_SYS_NS16550 420 #define CONFIG_SYS_NS16550_SERIAL 421 #define CONFIG_SYS_NS16550_REG_SIZE 1 422 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 423 424 #define CONFIG_SYS_BAUDRATE_TABLE \ 425 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 426 427 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 428 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 429 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 430 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 431 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 432 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 433 434 435 /* Use the HUSH parser */ 436 #define CONFIG_SYS_HUSH_PARSER 437 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 438 439 /* pass open firmware flat tree */ 440 #define CONFIG_OF_LIBFDT 441 #define CONFIG_OF_BOARD_SETUP 442 #define CONFIG_OF_STDOUT_VIA_ALIAS 443 444 /* new uImage format support */ 445 #define CONFIG_FIT 446 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 447 448 /* I2C */ 449 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 450 #define CONFIG_HARD_I2C /* I2C with hardware support */ 451 #define CONFIG_I2C_MULTI_BUS 452 #define CONFIG_I2C_CMD_TREE 453 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed in Hz */ 454 #define CONFIG_SYS_I2C_SLAVE 0x7F 455 #define CONFIG_SYS_I2C_OFFSET 0x118000 456 #define CONFIG_SYS_I2C2_OFFSET 0x119000 457 458 /* 459 * RTC configuration 460 */ 461 #define RTC 462 #define CONFIG_RTC_DS3231 1 463 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 464 465 /* 466 * RapidIO 467 */ 468 #ifdef CONFIG_SYS_SRIO 469 #ifdef CONFIG_SRIO1 470 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 471 #ifdef CONFIG_PHYS_64BIT 472 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 473 #else 474 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 475 #endif 476 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 477 #endif 478 479 #ifdef CONFIG_SRIO2 480 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 481 #ifdef CONFIG_PHYS_64BIT 482 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 483 #else 484 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 485 #endif 486 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 487 #endif 488 #endif 489 490 /* 491 * for slave u-boot IMAGE instored in master memory space, 492 * PHYS must be aligned based on the SIZE 493 */ 494 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 495 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 496 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 497 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 498 /* 499 * for slave UCODE and ENV instored in master memory space, 500 * PHYS must be aligned based on the SIZE 501 */ 502 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 503 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 504 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 505 506 /* slave core release by master*/ 507 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 508 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 509 510 /* 511 * SRIO_PCIE_BOOT - SLAVE 512 */ 513 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 514 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 515 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 516 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 517 #endif 518 519 /* 520 * eSPI - Enhanced SPI 521 */ 522 #define CONFIG_FSL_ESPI 523 #define CONFIG_SPI_FLASH 524 #define CONFIG_SPI_FLASH_SST 525 #define CONFIG_CMD_SF 526 #define CONFIG_SF_DEFAULT_SPEED 10000000 527 #define CONFIG_SF_DEFAULT_MODE 0 528 529 /* 530 * MAPLE 531 */ 532 #ifdef CONFIG_PHYS_64BIT 533 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 534 #else 535 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 536 #endif 537 538 /* 539 * General PCI 540 * Memory space is mapped 1-1, but I/O space must start from 0. 541 */ 542 543 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 544 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 545 #ifdef CONFIG_PHYS_64BIT 546 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 547 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 548 #else 549 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 550 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 551 #endif 552 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 553 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 554 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 555 #ifdef CONFIG_PHYS_64BIT 556 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 557 #else 558 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 559 #endif 560 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 561 562 /* Qman/Bman */ 563 #ifndef CONFIG_NOBQFMAN 564 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 565 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 566 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 567 #ifdef CONFIG_PHYS_64BIT 568 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 569 #else 570 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 571 #endif 572 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 573 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 574 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 575 #ifdef CONFIG_PHYS_64BIT 576 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 577 #else 578 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 579 #endif 580 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 581 582 #define CONFIG_SYS_DPAA_FMAN 583 584 /* Default address of microcode for the Linux Fman driver */ 585 #if defined(CONFIG_SPIFLASH) 586 /* 587 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 588 * env, so we got 0x110000. 589 */ 590 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 591 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 592 #elif defined(CONFIG_SDCARD) 593 /* 594 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 595 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 596 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 597 */ 598 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 599 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 600 #elif defined(CONFIG_NAND) 601 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 602 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 603 #else 604 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 605 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 606 #endif 607 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 608 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 609 #endif /* CONFIG_NOBQFMAN */ 610 611 #ifdef CONFIG_SYS_DPAA_FMAN 612 #define CONFIG_FMAN_ENET 613 #define CONFIG_PHYLIB_10G 614 #define CONFIG_PHY_VITESSE 615 #define CONFIG_PHY_TERANETICS 616 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 617 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 618 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 619 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 620 #endif 621 622 #ifdef CONFIG_PCI 623 #define CONFIG_NET_MULTI 624 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 625 #define CONFIG_E1000 626 627 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 628 #define CONFIG_DOS_PARTITION 629 #endif /* CONFIG_PCI */ 630 631 #ifdef CONFIG_FMAN_ENET 632 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 633 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 634 635 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 636 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 637 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 638 639 640 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 641 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 642 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 643 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 644 645 #define CONFIG_MII /* MII PHY management */ 646 #define CONFIG_ETHPRIME "FM1@DTSEC1" 647 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 648 #endif 649 650 /* 651 * Environment 652 */ 653 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 654 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 655 656 /* 657 * Command line configuration. 658 */ 659 #include <config_cmd_default.h> 660 661 #define CONFIG_CMD_DATE 662 #define CONFIG_CMD_DHCP 663 #define CONFIG_CMD_EEPROM 664 #define CONFIG_CMD_ELF 665 #define CONFIG_CMD_ERRATA 666 #define CONFIG_CMD_GREPENV 667 #define CONFIG_CMD_IRQ 668 #define CONFIG_CMD_I2C 669 #define CONFIG_CMD_MII 670 #define CONFIG_CMD_PING 671 #define CONFIG_CMD_REGINFO 672 #define CONFIG_CMD_SETEXPR 673 674 #ifdef CONFIG_PCI 675 #define CONFIG_CMD_PCI 676 #define CONFIG_CMD_NET 677 #endif 678 679 /* 680 * USB 681 */ 682 #define CONFIG_HAS_FSL_DR_USB 683 684 #ifdef CONFIG_HAS_FSL_DR_USB 685 #define CONFIG_USB_EHCI 686 687 #ifdef CONFIG_USB_EHCI 688 #define CONFIG_CMD_USB 689 #define CONFIG_USB_STORAGE 690 #define CONFIG_USB_EHCI_FSL 691 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 692 #define CONFIG_CMD_EXT2 693 #endif 694 #endif 695 696 /* 697 * Miscellaneous configurable options 698 */ 699 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 700 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 701 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 702 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 703 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 704 #ifdef CONFIG_CMD_KGDB 705 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 706 #else 707 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 708 #endif 709 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 710 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 711 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 712 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ 713 714 /* 715 * For booting Linux, the board info and command line data 716 * have to be in the first 64 MB of memory, since this is 717 * the maximum mapped by the Linux kernel during initialization. 718 */ 719 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 720 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 721 722 #ifdef CONFIG_CMD_KGDB 723 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 724 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 725 #endif 726 727 /* 728 * Environment Configuration 729 */ 730 #define CONFIG_ROOTPATH "/opt/nfsroot" 731 #define CONFIG_BOOTFILE "uImage" 732 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 733 734 /* default location for tftp and bootm */ 735 #define CONFIG_LOADADDR 1000000 736 737 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 738 739 #define CONFIG_BAUDRATE 115200 740 741 #define __USB_PHY_TYPE ulpi 742 743 #define CONFIG_EXTRA_ENV_SETTINGS \ 744 "hwconfig=fsl_ddr:ctlr_intlv=null," \ 745 "bank_intlv=cs0_cs1;" \ 746 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 747 "netdev=eth0\0" \ 748 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 749 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 750 "tftpflash=tftpboot $loadaddr $uboot && " \ 751 "protect off $ubootaddr +$filesize && " \ 752 "erase $ubootaddr +$filesize && " \ 753 "cp.b $loadaddr $ubootaddr $filesize && " \ 754 "protect on $ubootaddr +$filesize && " \ 755 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 756 "consoledev=ttyS0\0" \ 757 "ramdiskaddr=2000000\0" \ 758 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 759 "fdtaddr=c00000\0" \ 760 "fdtfile=b4860qds/b4860qds.dtb\0" \ 761 "bdev=sda3\0" \ 762 "c=ffe\0" 763 764 /* For emulation this causes u-boot to jump to the start of the proof point 765 app code automatically */ 766 #define CONFIG_PROOF_POINTS \ 767 "setenv bootargs root=/dev/$bdev rw " \ 768 "console=$consoledev,$baudrate $othbootargs;" \ 769 "cpu 1 release 0x29000000 - - -;" \ 770 "cpu 2 release 0x29000000 - - -;" \ 771 "cpu 3 release 0x29000000 - - -;" \ 772 "cpu 4 release 0x29000000 - - -;" \ 773 "cpu 5 release 0x29000000 - - -;" \ 774 "cpu 6 release 0x29000000 - - -;" \ 775 "cpu 7 release 0x29000000 - - -;" \ 776 "go 0x29000000" 777 778 #define CONFIG_HVBOOT \ 779 "setenv bootargs config-addr=0x60000000; " \ 780 "bootm 0x01000000 - 0x00f00000" 781 782 #define CONFIG_ALU \ 783 "setenv bootargs root=/dev/$bdev rw " \ 784 "console=$consoledev,$baudrate $othbootargs;" \ 785 "cpu 1 release 0x01000000 - - -;" \ 786 "cpu 2 release 0x01000000 - - -;" \ 787 "cpu 3 release 0x01000000 - - -;" \ 788 "cpu 4 release 0x01000000 - - -;" \ 789 "cpu 5 release 0x01000000 - - -;" \ 790 "cpu 6 release 0x01000000 - - -;" \ 791 "cpu 7 release 0x01000000 - - -;" \ 792 "go 0x01000000" 793 794 #define CONFIG_LINUX \ 795 "setenv bootargs root=/dev/ram rw " \ 796 "console=$consoledev,$baudrate $othbootargs;" \ 797 "setenv ramdiskaddr 0x02000000;" \ 798 "setenv fdtaddr 0x00c00000;" \ 799 "setenv loadaddr 0x1000000;" \ 800 "bootm $loadaddr $ramdiskaddr $fdtaddr" 801 802 #define CONFIG_HDBOOT \ 803 "setenv bootargs root=/dev/$bdev rw " \ 804 "console=$consoledev,$baudrate $othbootargs;" \ 805 "tftp $loadaddr $bootfile;" \ 806 "tftp $fdtaddr $fdtfile;" \ 807 "bootm $loadaddr - $fdtaddr" 808 809 #define CONFIG_NFSBOOTCOMMAND \ 810 "setenv bootargs root=/dev/nfs rw " \ 811 "nfsroot=$serverip:$rootpath " \ 812 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 813 "console=$consoledev,$baudrate $othbootargs;" \ 814 "tftp $loadaddr $bootfile;" \ 815 "tftp $fdtaddr $fdtfile;" \ 816 "bootm $loadaddr - $fdtaddr" 817 818 #define CONFIG_RAMBOOTCOMMAND \ 819 "setenv bootargs root=/dev/ram rw " \ 820 "console=$consoledev,$baudrate $othbootargs;" \ 821 "tftp $ramdiskaddr $ramdiskfile;" \ 822 "tftp $loadaddr $bootfile;" \ 823 "tftp $fdtaddr $fdtfile;" \ 824 "bootm $loadaddr $ramdiskaddr $fdtaddr" 825 826 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 827 828 #ifdef CONFIG_SECURE_BOOT 829 #include <asm/fsl_secure_boot.h> 830 #endif 831 832 #endif /* __CONFIG_H */ 833