1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 /* 10 * B4860 QDS board configuration file 11 */ 12 #ifdef CONFIG_RAMBOOT_PBL 13 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 14 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 15 #ifndef CONFIG_NAND 16 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 18 #else 19 #define CONFIG_SPL_FLUSH_IMAGE 20 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 21 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 22 #define CONFIG_SPL_PAD_TO 0x40000 23 #define CONFIG_SPL_MAX_SIZE 0x28000 24 #define RESET_VECTOR_OFFSET 0x27FFC 25 #define BOOT_PAGE_OFFSET 0x27000 26 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 27 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 28 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 29 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 30 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 31 #define CONFIG_SPL_NAND_BOOT 32 #ifdef CONFIG_SPL_BUILD 33 #define CONFIG_SPL_SKIP_RELOCATE 34 #define CONFIG_SPL_COMMON_INIT_DDR 35 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 36 #endif 37 #endif 38 #endif 39 40 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 41 /* Set 1M boot space */ 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 43 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 44 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 45 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 46 #endif 47 48 /* High Level Configuration Options */ 49 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 50 51 #ifndef CONFIG_RESET_VECTOR_ADDRESS 52 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 53 #endif 54 55 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 56 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 57 #define CONFIG_PCIE1 /* PCIE controller 1 */ 58 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 59 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 60 61 #ifndef CONFIG_ARCH_B4420 62 #define CONFIG_SYS_SRIO 63 #define CONFIG_SRIO1 /* SRIO port 1 */ 64 #define CONFIG_SRIO2 /* SRIO port 2 */ 65 #define CONFIG_SRIO_PCIE_BOOT_MASTER 66 #endif 67 68 /* I2C bus multiplexer */ 69 #define I2C_MUX_PCA_ADDR 0x77 70 71 /* VSC Crossbar switches */ 72 #define CONFIG_VSC_CROSSBAR 73 #define I2C_CH_DEFAULT 0x8 74 #define I2C_CH_VSC3316 0xc 75 #define I2C_CH_VSC3308 0xd 76 77 #define VSC3316_TX_ADDRESS 0x70 78 #define VSC3316_RX_ADDRESS 0x71 79 #define VSC3308_TX_ADDRESS 0x02 80 #define VSC3308_RX_ADDRESS 0x03 81 82 /* IDT clock synthesizers */ 83 #define CONFIG_IDT8T49N222A 84 #define I2C_CH_IDT 0x9 85 86 #define IDT_SERDES1_ADDRESS 0x6E 87 #define IDT_SERDES2_ADDRESS 0x6C 88 89 /* Voltage monitor on channel 2*/ 90 #define I2C_MUX_CH_VOL_MONITOR 0xa 91 #define I2C_VOL_MONITOR_ADDR 0x40 92 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 93 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 94 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 95 96 #define CONFIG_ZM7300 97 #define I2C_MUX_CH_DPM 0xa 98 #define I2C_DPM_ADDR 0x28 99 100 #define CONFIG_ENV_OVERWRITE 101 102 #ifndef CONFIG_MTD_NOR_FLASH 103 #else 104 #define CONFIG_FLASH_CFI_DRIVER 105 #define CONFIG_SYS_FLASH_CFI 106 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 107 #endif 108 109 #if defined(CONFIG_SPIFLASH) 110 #define CONFIG_SYS_EXTRA_ENV_RELOC 111 #define CONFIG_ENV_SPI_BUS 0 112 #define CONFIG_ENV_SPI_CS 0 113 #define CONFIG_ENV_SPI_MAX_HZ 10000000 114 #define CONFIG_ENV_SPI_MODE 0 115 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 116 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 117 #define CONFIG_ENV_SECT_SIZE 0x10000 118 #elif defined(CONFIG_SDCARD) 119 #define CONFIG_SYS_EXTRA_ENV_RELOC 120 #define CONFIG_SYS_MMC_ENV_DEV 0 121 #define CONFIG_ENV_SIZE 0x2000 122 #define CONFIG_ENV_OFFSET (512 * 1097) 123 #elif defined(CONFIG_NAND) 124 #define CONFIG_SYS_EXTRA_ENV_RELOC 125 #define CONFIG_ENV_SIZE 0x2000 126 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 127 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 128 #define CONFIG_ENV_ADDR 0xffe20000 129 #define CONFIG_ENV_SIZE 0x2000 130 #elif defined(CONFIG_ENV_IS_NOWHERE) 131 #define CONFIG_ENV_SIZE 0x2000 132 #else 133 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 134 #define CONFIG_ENV_SIZE 0x2000 135 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 136 #endif 137 138 #ifndef __ASSEMBLY__ 139 unsigned long get_board_sys_clk(void); 140 unsigned long get_board_ddr_clk(void); 141 #endif 142 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 143 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 144 145 /* 146 * These can be toggled for performance analysis, otherwise use default. 147 */ 148 #define CONFIG_SYS_CACHE_STASHING 149 #define CONFIG_BTB /* toggle branch predition */ 150 #define CONFIG_DDR_ECC 151 #ifdef CONFIG_DDR_ECC 152 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 153 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 154 #endif 155 156 #define CONFIG_ENABLE_36BIT_PHYS 157 158 #ifdef CONFIG_PHYS_64BIT 159 #define CONFIG_ADDR_MAP 160 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 161 #endif 162 163 #if 0 164 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 165 #endif 166 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 167 #define CONFIG_SYS_MEMTEST_END 0x00400000 168 169 /* 170 * Config the L3 Cache as L3 SRAM 171 */ 172 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 173 #define CONFIG_SYS_L3_SIZE 256 << 10 174 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 175 #ifdef CONFIG_NAND 176 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 177 #endif 178 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 179 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 180 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 181 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 182 183 #ifdef CONFIG_PHYS_64BIT 184 #define CONFIG_SYS_DCSRBAR 0xf0000000 185 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 186 #endif 187 188 /* EEPROM */ 189 #define CONFIG_ID_EEPROM 190 #define CONFIG_SYS_I2C_EEPROM_NXID 191 #define CONFIG_SYS_EEPROM_BUS_NUM 0 192 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 193 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 194 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 195 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 196 197 /* 198 * DDR Setup 199 */ 200 #define CONFIG_VERY_BIG_RAM 201 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 202 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 203 204 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 205 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 206 207 #define CONFIG_DDR_SPD 208 #define CONFIG_SYS_DDR_RAW_TIMING 209 #ifndef CONFIG_SPL_BUILD 210 #define CONFIG_FSL_DDR_INTERACTIVE 211 #endif 212 213 #define CONFIG_SYS_SPD_BUS_NUM 0 214 #define SPD_EEPROM_ADDRESS1 0x51 215 #define SPD_EEPROM_ADDRESS2 0x53 216 217 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 218 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 219 220 /* 221 * IFC Definitions 222 */ 223 #define CONFIG_SYS_FLASH_BASE 0xe0000000 224 #ifdef CONFIG_PHYS_64BIT 225 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 226 #else 227 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 228 #endif 229 230 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 231 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 232 + 0x8000000) | \ 233 CSPR_PORT_SIZE_16 | \ 234 CSPR_MSEL_NOR | \ 235 CSPR_V) 236 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 237 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 238 CSPR_PORT_SIZE_16 | \ 239 CSPR_MSEL_NOR | \ 240 CSPR_V) 241 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 242 /* NOR Flash Timing Params */ 243 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 244 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 245 FTIM0_NOR_TEADC(0x04) | \ 246 FTIM0_NOR_TEAHC(0x20)) 247 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 248 FTIM1_NOR_TRAD_NOR(0x1A) |\ 249 FTIM1_NOR_TSEQRAD_NOR(0x13)) 250 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 251 FTIM2_NOR_TCH(0x0E) | \ 252 FTIM2_NOR_TWPH(0x0E) | \ 253 FTIM2_NOR_TWP(0x1c)) 254 #define CONFIG_SYS_NOR_FTIM3 0x0 255 256 #define CONFIG_SYS_FLASH_QUIET_TEST 257 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 258 259 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 260 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 261 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 262 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 263 264 #define CONFIG_SYS_FLASH_EMPTY_INFO 265 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 266 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 267 268 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 269 #define CONFIG_FSL_QIXIS_V2 270 #define QIXIS_BASE 0xffdf0000 271 #ifdef CONFIG_PHYS_64BIT 272 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 273 #else 274 #define QIXIS_BASE_PHYS QIXIS_BASE 275 #endif 276 #define QIXIS_LBMAP_SWITCH 0x01 277 #define QIXIS_LBMAP_MASK 0x0f 278 #define QIXIS_LBMAP_SHIFT 0 279 #define QIXIS_LBMAP_DFLTBANK 0x00 280 #define QIXIS_LBMAP_ALTBANK 0x02 281 #define QIXIS_RST_CTL_RESET 0x31 282 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 283 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 284 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 285 286 #define CONFIG_SYS_CSPR3_EXT (0xf) 287 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 288 | CSPR_PORT_SIZE_8 \ 289 | CSPR_MSEL_GPCM \ 290 | CSPR_V) 291 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 292 #define CONFIG_SYS_CSOR3 0x0 293 /* QIXIS Timing parameters for IFC CS3 */ 294 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 295 FTIM0_GPCM_TEADC(0x0e) | \ 296 FTIM0_GPCM_TEAHC(0x0e)) 297 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 298 FTIM1_GPCM_TRAD(0x1f)) 299 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 300 FTIM2_GPCM_TCH(0x8) | \ 301 FTIM2_GPCM_TWP(0x1f)) 302 #define CONFIG_SYS_CS3_FTIM3 0x0 303 304 /* NAND Flash on IFC */ 305 #define CONFIG_NAND_FSL_IFC 306 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 307 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 308 #define CONFIG_SYS_NAND_BASE 0xff800000 309 #ifdef CONFIG_PHYS_64BIT 310 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 311 #else 312 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 313 #endif 314 315 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 316 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 317 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 318 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 319 | CSPR_V) 320 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 321 322 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 323 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 324 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 325 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 326 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 327 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 328 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 329 330 #define CONFIG_SYS_NAND_ONFI_DETECTION 331 332 /* ONFI NAND Flash mode0 Timing Params */ 333 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 334 FTIM0_NAND_TWP(0x18) | \ 335 FTIM0_NAND_TWCHT(0x07) | \ 336 FTIM0_NAND_TWH(0x0a)) 337 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 338 FTIM1_NAND_TWBE(0x39) | \ 339 FTIM1_NAND_TRR(0x0e) | \ 340 FTIM1_NAND_TRP(0x18)) 341 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 342 FTIM2_NAND_TREH(0x0a) | \ 343 FTIM2_NAND_TWHRE(0x1e)) 344 #define CONFIG_SYS_NAND_FTIM3 0x0 345 346 #define CONFIG_SYS_NAND_DDR_LAW 11 347 348 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 349 #define CONFIG_SYS_MAX_NAND_DEVICE 1 350 351 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 352 353 #if defined(CONFIG_NAND) 354 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 355 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 356 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 357 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 358 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 359 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 360 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 361 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 362 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 363 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 364 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 365 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 366 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 367 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 368 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 369 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 370 #else 371 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 372 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 373 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 374 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 375 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 376 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 377 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 378 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 379 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 380 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 381 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 382 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 383 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 384 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 385 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 386 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 387 #endif 388 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 389 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 390 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 391 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 392 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 393 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 394 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 395 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 396 397 #ifdef CONFIG_SPL_BUILD 398 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 399 #else 400 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 401 #endif 402 403 #if defined(CONFIG_RAMBOOT_PBL) 404 #define CONFIG_SYS_RAMBOOT 405 #endif 406 407 #define CONFIG_MISC_INIT_R 408 409 #define CONFIG_HWCONFIG 410 411 /* define to use L1 as initial stack */ 412 #define CONFIG_L1_INIT_RAM 413 #define CONFIG_SYS_INIT_RAM_LOCK 414 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 415 #ifdef CONFIG_PHYS_64BIT 416 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 417 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 418 /* The assembler doesn't like typecast */ 419 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 420 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 421 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 422 #else 423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 424 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 425 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 426 #endif 427 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 428 429 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 430 GENERATED_GBL_DATA_SIZE) 431 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 432 433 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 434 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 435 436 /* Serial Port - controlled on board with jumper J8 437 * open - index 2 438 * shorted - index 1 439 */ 440 #define CONFIG_SYS_NS16550_SERIAL 441 #define CONFIG_SYS_NS16550_REG_SIZE 1 442 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 443 444 #define CONFIG_SYS_BAUDRATE_TABLE \ 445 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 446 447 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 448 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 449 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 450 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 451 452 /* I2C */ 453 #define CONFIG_SYS_I2C 454 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 455 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 456 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 457 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 458 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 459 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 460 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 461 462 /* 463 * RTC configuration 464 */ 465 #define RTC 466 #define CONFIG_RTC_DS3231 1 467 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 468 469 /* 470 * RapidIO 471 */ 472 #ifdef CONFIG_SYS_SRIO 473 #ifdef CONFIG_SRIO1 474 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 475 #ifdef CONFIG_PHYS_64BIT 476 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 477 #else 478 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 479 #endif 480 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 481 #endif 482 483 #ifdef CONFIG_SRIO2 484 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 485 #ifdef CONFIG_PHYS_64BIT 486 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 487 #else 488 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 489 #endif 490 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 491 #endif 492 #endif 493 494 /* 495 * for slave u-boot IMAGE instored in master memory space, 496 * PHYS must be aligned based on the SIZE 497 */ 498 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 499 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 500 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 501 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 502 /* 503 * for slave UCODE and ENV instored in master memory space, 504 * PHYS must be aligned based on the SIZE 505 */ 506 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 507 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 508 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 509 510 /* slave core release by master*/ 511 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 512 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 513 514 /* 515 * SRIO_PCIE_BOOT - SLAVE 516 */ 517 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 518 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 519 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 520 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 521 #endif 522 523 /* 524 * eSPI - Enhanced SPI 525 */ 526 #define CONFIG_SF_DEFAULT_SPEED 10000000 527 #define CONFIG_SF_DEFAULT_MODE 0 528 529 /* 530 * MAPLE 531 */ 532 #ifdef CONFIG_PHYS_64BIT 533 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 534 #else 535 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 536 #endif 537 538 /* 539 * General PCI 540 * Memory space is mapped 1-1, but I/O space must start from 0. 541 */ 542 543 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 544 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 545 #ifdef CONFIG_PHYS_64BIT 546 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 547 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 548 #else 549 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 550 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 551 #endif 552 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 553 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 554 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 555 #ifdef CONFIG_PHYS_64BIT 556 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 557 #else 558 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 559 #endif 560 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 561 562 /* Qman/Bman */ 563 #ifndef CONFIG_NOBQFMAN 564 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 565 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 566 #ifdef CONFIG_PHYS_64BIT 567 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 568 #else 569 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 570 #endif 571 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 572 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 573 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 574 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 575 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 576 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 577 CONFIG_SYS_BMAN_CENA_SIZE) 578 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 579 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 580 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 581 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 582 #ifdef CONFIG_PHYS_64BIT 583 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 584 #else 585 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 586 #endif 587 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 588 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 589 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 590 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 591 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 592 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 593 CONFIG_SYS_QMAN_CENA_SIZE) 594 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 595 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 596 597 #define CONFIG_SYS_DPAA_FMAN 598 599 #define CONFIG_SYS_DPAA_RMAN 600 601 /* Default address of microcode for the Linux Fman driver */ 602 #if defined(CONFIG_SPIFLASH) 603 /* 604 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 605 * env, so we got 0x110000. 606 */ 607 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 608 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 609 #elif defined(CONFIG_SDCARD) 610 /* 611 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 612 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 613 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 614 */ 615 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 616 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 617 #elif defined(CONFIG_NAND) 618 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 619 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 620 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 621 /* 622 * Slave has no ucode locally, it can fetch this from remote. When implementing 623 * in two corenet boards, slave's ucode could be stored in master's memory 624 * space, the address can be mapped from slave TLB->slave LAW-> 625 * slave SRIO or PCIE outbound window->master inbound window-> 626 * master LAW->the ucode address in master's memory space. 627 */ 628 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 629 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 630 #else 631 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 632 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 633 #endif 634 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 635 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 636 #endif /* CONFIG_NOBQFMAN */ 637 638 #ifdef CONFIG_SYS_DPAA_FMAN 639 #define CONFIG_FMAN_ENET 640 #define CONFIG_PHYLIB_10G 641 #define CONFIG_PHY_VITESSE 642 #define CONFIG_PHY_TERANETICS 643 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 644 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 645 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 646 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 647 #endif 648 649 #ifdef CONFIG_PCI 650 #define CONFIG_PCI_INDIRECT_BRIDGE 651 652 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 653 #endif /* CONFIG_PCI */ 654 655 #ifdef CONFIG_FMAN_ENET 656 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 657 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 658 659 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 660 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 661 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 662 663 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 664 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 665 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 666 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 667 668 #define CONFIG_MII /* MII PHY management */ 669 #define CONFIG_ETHPRIME "FM1@DTSEC1" 670 #endif 671 672 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR 673 674 /* 675 * Environment 676 */ 677 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 678 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 679 680 /* 681 * USB 682 */ 683 #define CONFIG_HAS_FSL_DR_USB 684 685 #ifdef CONFIG_HAS_FSL_DR_USB 686 #ifdef CONFIG_USB_EHCI_HCD 687 #define CONFIG_USB_EHCI_FSL 688 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 689 #endif 690 #endif 691 692 /* 693 * Miscellaneous configurable options 694 */ 695 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 696 697 /* 698 * For booting Linux, the board info and command line data 699 * have to be in the first 64 MB of memory, since this is 700 * the maximum mapped by the Linux kernel during initialization. 701 */ 702 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 703 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 704 705 #ifdef CONFIG_CMD_KGDB 706 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 707 #endif 708 709 /* 710 * Environment Configuration 711 */ 712 #define CONFIG_ROOTPATH "/opt/nfsroot" 713 #define CONFIG_BOOTFILE "uImage" 714 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 715 716 /* default location for tftp and bootm */ 717 #define CONFIG_LOADADDR 1000000 718 719 #define __USB_PHY_TYPE ulpi 720 721 #ifdef CONFIG_ARCH_B4860 722 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 723 "bank_intlv=cs0_cs1;" \ 724 "en_cpc:cpc2;" 725 #else 726 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 727 #endif 728 729 #define CONFIG_EXTRA_ENV_SETTINGS \ 730 HWCONFIG \ 731 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 732 "netdev=eth0\0" \ 733 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 734 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 735 "tftpflash=tftpboot $loadaddr $uboot && " \ 736 "protect off $ubootaddr +$filesize && " \ 737 "erase $ubootaddr +$filesize && " \ 738 "cp.b $loadaddr $ubootaddr $filesize && " \ 739 "protect on $ubootaddr +$filesize && " \ 740 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 741 "consoledev=ttyS0\0" \ 742 "ramdiskaddr=2000000\0" \ 743 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 744 "fdtaddr=1e00000\0" \ 745 "fdtfile=b4860qds/b4860qds.dtb\0" \ 746 "bdev=sda3\0" 747 748 /* For emulation this causes u-boot to jump to the start of the proof point 749 app code automatically */ 750 #define CONFIG_PROOF_POINTS \ 751 "setenv bootargs root=/dev/$bdev rw " \ 752 "console=$consoledev,$baudrate $othbootargs;" \ 753 "cpu 1 release 0x29000000 - - -;" \ 754 "cpu 2 release 0x29000000 - - -;" \ 755 "cpu 3 release 0x29000000 - - -;" \ 756 "cpu 4 release 0x29000000 - - -;" \ 757 "cpu 5 release 0x29000000 - - -;" \ 758 "cpu 6 release 0x29000000 - - -;" \ 759 "cpu 7 release 0x29000000 - - -;" \ 760 "go 0x29000000" 761 762 #define CONFIG_HVBOOT \ 763 "setenv bootargs config-addr=0x60000000; " \ 764 "bootm 0x01000000 - 0x00f00000" 765 766 #define CONFIG_ALU \ 767 "setenv bootargs root=/dev/$bdev rw " \ 768 "console=$consoledev,$baudrate $othbootargs;" \ 769 "cpu 1 release 0x01000000 - - -;" \ 770 "cpu 2 release 0x01000000 - - -;" \ 771 "cpu 3 release 0x01000000 - - -;" \ 772 "cpu 4 release 0x01000000 - - -;" \ 773 "cpu 5 release 0x01000000 - - -;" \ 774 "cpu 6 release 0x01000000 - - -;" \ 775 "cpu 7 release 0x01000000 - - -;" \ 776 "go 0x01000000" 777 778 #define CONFIG_LINUX \ 779 "setenv bootargs root=/dev/ram rw " \ 780 "console=$consoledev,$baudrate $othbootargs;" \ 781 "setenv ramdiskaddr 0x02000000;" \ 782 "setenv fdtaddr 0x01e00000;" \ 783 "setenv loadaddr 0x1000000;" \ 784 "bootm $loadaddr $ramdiskaddr $fdtaddr" 785 786 #define CONFIG_HDBOOT \ 787 "setenv bootargs root=/dev/$bdev rw " \ 788 "console=$consoledev,$baudrate $othbootargs;" \ 789 "tftp $loadaddr $bootfile;" \ 790 "tftp $fdtaddr $fdtfile;" \ 791 "bootm $loadaddr - $fdtaddr" 792 793 #define CONFIG_NFSBOOTCOMMAND \ 794 "setenv bootargs root=/dev/nfs rw " \ 795 "nfsroot=$serverip:$rootpath " \ 796 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 797 "console=$consoledev,$baudrate $othbootargs;" \ 798 "tftp $loadaddr $bootfile;" \ 799 "tftp $fdtaddr $fdtfile;" \ 800 "bootm $loadaddr - $fdtaddr" 801 802 #define CONFIG_RAMBOOTCOMMAND \ 803 "setenv bootargs root=/dev/ram rw " \ 804 "console=$consoledev,$baudrate $othbootargs;" \ 805 "tftp $ramdiskaddr $ramdiskfile;" \ 806 "tftp $loadaddr $bootfile;" \ 807 "tftp $fdtaddr $fdtfile;" \ 808 "bootm $loadaddr $ramdiskaddr $fdtaddr" 809 810 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 811 812 #include <asm/fsl_secure_boot.h> 813 814 #endif /* __CONFIG_H */ 815