1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_DISPLAY_BOARDINFO 11 12 /* 13 * B4860 QDS board configuration file 14 */ 15 #define CONFIG_B4860QDS 16 17 #ifdef CONFIG_RAMBOOT_PBL 18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 19 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 20 #ifndef CONFIG_NAND 21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 23 #else 24 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 25 #define CONFIG_SPL_ENV_SUPPORT 26 #define CONFIG_SPL_SERIAL_SUPPORT 27 #define CONFIG_SPL_FLUSH_IMAGE 28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 29 #define CONFIG_SPL_LIBGENERIC_SUPPORT 30 #define CONFIG_SPL_LIBCOMMON_SUPPORT 31 #define CONFIG_SPL_I2C_SUPPORT 32 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 33 #define CONFIG_FSL_LAW /* Use common FSL init code */ 34 #define CONFIG_SYS_TEXT_BASE 0x00201000 35 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 36 #define CONFIG_SPL_PAD_TO 0x40000 37 #define CONFIG_SPL_MAX_SIZE 0x28000 38 #define RESET_VECTOR_OFFSET 0x27FFC 39 #define BOOT_PAGE_OFFSET 0x27000 40 #define CONFIG_SPL_NAND_SUPPORT 41 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 42 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 43 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 44 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 45 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 46 #define CONFIG_SPL_NAND_BOOT 47 #ifdef CONFIG_SPL_BUILD 48 #define CONFIG_SPL_SKIP_RELOCATE 49 #define CONFIG_SPL_COMMON_INIT_DDR 50 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 51 #define CONFIG_SYS_NO_FLASH 52 #endif 53 #endif 54 #endif 55 56 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 57 /* Set 1M boot space */ 58 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 59 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 60 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 61 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 62 #define CONFIG_SYS_NO_FLASH 63 #endif 64 65 /* High Level Configuration Options */ 66 #define CONFIG_BOOKE 67 #define CONFIG_E500 /* BOOKE e500 family */ 68 #define CONFIG_E500MC /* BOOKE e500mc family */ 69 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 70 #define CONFIG_MP /* support multiple processors */ 71 72 #ifndef CONFIG_SYS_TEXT_BASE 73 #define CONFIG_SYS_TEXT_BASE 0xeff40000 74 #endif 75 76 #ifndef CONFIG_RESET_VECTOR_ADDRESS 77 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 78 #endif 79 80 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 81 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 82 #define CONFIG_FSL_IFC /* Enable IFC Support */ 83 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 84 #define CONFIG_PCI /* Enable PCI/PCIE */ 85 #define CONFIG_PCIE1 /* PCIE controller 1 */ 86 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 87 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 88 89 #ifndef CONFIG_PPC_B4420 90 #define CONFIG_SYS_SRIO 91 #define CONFIG_SRIO1 /* SRIO port 1 */ 92 #define CONFIG_SRIO2 /* SRIO port 2 */ 93 #define CONFIG_SRIO_PCIE_BOOT_MASTER 94 #endif 95 96 #define CONFIG_FSL_LAW /* Use common FSL init code */ 97 98 /* I2C bus multiplexer */ 99 #define I2C_MUX_PCA_ADDR 0x77 100 101 /* VSC Crossbar switches */ 102 #define CONFIG_VSC_CROSSBAR 103 #define I2C_CH_DEFAULT 0x8 104 #define I2C_CH_VSC3316 0xc 105 #define I2C_CH_VSC3308 0xd 106 107 #define VSC3316_TX_ADDRESS 0x70 108 #define VSC3316_RX_ADDRESS 0x71 109 #define VSC3308_TX_ADDRESS 0x02 110 #define VSC3308_RX_ADDRESS 0x03 111 112 /* IDT clock synthesizers */ 113 #define CONFIG_IDT8T49N222A 114 #define I2C_CH_IDT 0x9 115 116 #define IDT_SERDES1_ADDRESS 0x6E 117 #define IDT_SERDES2_ADDRESS 0x6C 118 119 /* Voltage monitor on channel 2*/ 120 #define I2C_MUX_CH_VOL_MONITOR 0xa 121 #define I2C_VOL_MONITOR_ADDR 0x40 122 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 123 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 124 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 125 126 #define CONFIG_ZM7300 127 #define I2C_MUX_CH_DPM 0xa 128 #define I2C_DPM_ADDR 0x28 129 130 #define CONFIG_ENV_OVERWRITE 131 132 #ifdef CONFIG_SYS_NO_FLASH 133 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 134 #define CONFIG_ENV_IS_NOWHERE 135 #endif 136 #else 137 #define CONFIG_FLASH_CFI_DRIVER 138 #define CONFIG_SYS_FLASH_CFI 139 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 140 #endif 141 142 #if defined(CONFIG_SPIFLASH) 143 #define CONFIG_SYS_EXTRA_ENV_RELOC 144 #define CONFIG_ENV_IS_IN_SPI_FLASH 145 #define CONFIG_ENV_SPI_BUS 0 146 #define CONFIG_ENV_SPI_CS 0 147 #define CONFIG_ENV_SPI_MAX_HZ 10000000 148 #define CONFIG_ENV_SPI_MODE 0 149 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 150 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 151 #define CONFIG_ENV_SECT_SIZE 0x10000 152 #elif defined(CONFIG_SDCARD) 153 #define CONFIG_SYS_EXTRA_ENV_RELOC 154 #define CONFIG_ENV_IS_IN_MMC 155 #define CONFIG_SYS_MMC_ENV_DEV 0 156 #define CONFIG_ENV_SIZE 0x2000 157 #define CONFIG_ENV_OFFSET (512 * 1097) 158 #elif defined(CONFIG_NAND) 159 #define CONFIG_SYS_EXTRA_ENV_RELOC 160 #define CONFIG_ENV_IS_IN_NAND 161 #define CONFIG_ENV_SIZE 0x2000 162 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 163 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 164 #define CONFIG_ENV_IS_IN_REMOTE 165 #define CONFIG_ENV_ADDR 0xffe20000 166 #define CONFIG_ENV_SIZE 0x2000 167 #elif defined(CONFIG_ENV_IS_NOWHERE) 168 #define CONFIG_ENV_SIZE 0x2000 169 #else 170 #define CONFIG_ENV_IS_IN_FLASH 171 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 172 #define CONFIG_ENV_SIZE 0x2000 173 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 174 #endif 175 176 #ifndef __ASSEMBLY__ 177 unsigned long get_board_sys_clk(void); 178 unsigned long get_board_ddr_clk(void); 179 #endif 180 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 181 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 182 183 /* 184 * These can be toggled for performance analysis, otherwise use default. 185 */ 186 #define CONFIG_SYS_CACHE_STASHING 187 #define CONFIG_BTB /* toggle branch predition */ 188 #define CONFIG_DDR_ECC 189 #ifdef CONFIG_DDR_ECC 190 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 191 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 192 #endif 193 194 #define CONFIG_ENABLE_36BIT_PHYS 195 196 #ifdef CONFIG_PHYS_64BIT 197 #define CONFIG_ADDR_MAP 198 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 199 #endif 200 201 #if 0 202 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 203 #endif 204 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 205 #define CONFIG_SYS_MEMTEST_END 0x00400000 206 #define CONFIG_SYS_ALT_MEMTEST 207 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 208 209 /* 210 * Config the L3 Cache as L3 SRAM 211 */ 212 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 213 #define CONFIG_SYS_L3_SIZE 256 << 10 214 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 215 #ifdef CONFIG_NAND 216 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 217 #endif 218 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 219 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 220 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 221 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 222 223 #ifdef CONFIG_PHYS_64BIT 224 #define CONFIG_SYS_DCSRBAR 0xf0000000 225 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 226 #endif 227 228 /* EEPROM */ 229 #define CONFIG_ID_EEPROM 230 #define CONFIG_SYS_I2C_EEPROM_NXID 231 #define CONFIG_SYS_EEPROM_BUS_NUM 0 232 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 233 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 234 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 235 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 236 237 /* 238 * DDR Setup 239 */ 240 #define CONFIG_VERY_BIG_RAM 241 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 242 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 243 244 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 245 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 246 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 247 248 #define CONFIG_DDR_SPD 249 #define CONFIG_SYS_DDR_RAW_TIMING 250 #define CONFIG_SYS_FSL_DDR3 251 #ifndef CONFIG_SPL_BUILD 252 #define CONFIG_FSL_DDR_INTERACTIVE 253 #endif 254 255 #define CONFIG_SYS_SPD_BUS_NUM 0 256 #define SPD_EEPROM_ADDRESS1 0x51 257 #define SPD_EEPROM_ADDRESS2 0x53 258 259 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 260 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 261 262 /* 263 * IFC Definitions 264 */ 265 #define CONFIG_SYS_FLASH_BASE 0xe0000000 266 #ifdef CONFIG_PHYS_64BIT 267 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 268 #else 269 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 270 #endif 271 272 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 273 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 274 + 0x8000000) | \ 275 CSPR_PORT_SIZE_16 | \ 276 CSPR_MSEL_NOR | \ 277 CSPR_V) 278 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 279 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 280 CSPR_PORT_SIZE_16 | \ 281 CSPR_MSEL_NOR | \ 282 CSPR_V) 283 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 284 /* NOR Flash Timing Params */ 285 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 286 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 287 FTIM0_NOR_TEADC(0x04) | \ 288 FTIM0_NOR_TEAHC(0x20)) 289 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 290 FTIM1_NOR_TRAD_NOR(0x1A) |\ 291 FTIM1_NOR_TSEQRAD_NOR(0x13)) 292 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 293 FTIM2_NOR_TCH(0x0E) | \ 294 FTIM2_NOR_TWPH(0x0E) | \ 295 FTIM2_NOR_TWP(0x1c)) 296 #define CONFIG_SYS_NOR_FTIM3 0x0 297 298 #define CONFIG_SYS_FLASH_QUIET_TEST 299 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 300 301 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 302 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 303 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 304 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 305 306 #define CONFIG_SYS_FLASH_EMPTY_INFO 307 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 308 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 309 310 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 311 #define CONFIG_FSL_QIXIS_V2 312 #define QIXIS_BASE 0xffdf0000 313 #ifdef CONFIG_PHYS_64BIT 314 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 315 #else 316 #define QIXIS_BASE_PHYS QIXIS_BASE 317 #endif 318 #define QIXIS_LBMAP_SWITCH 0x01 319 #define QIXIS_LBMAP_MASK 0x0f 320 #define QIXIS_LBMAP_SHIFT 0 321 #define QIXIS_LBMAP_DFLTBANK 0x00 322 #define QIXIS_LBMAP_ALTBANK 0x02 323 #define QIXIS_RST_CTL_RESET 0x31 324 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 325 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 326 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 327 328 #define CONFIG_SYS_CSPR3_EXT (0xf) 329 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 330 | CSPR_PORT_SIZE_8 \ 331 | CSPR_MSEL_GPCM \ 332 | CSPR_V) 333 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 334 #define CONFIG_SYS_CSOR3 0x0 335 /* QIXIS Timing parameters for IFC CS3 */ 336 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 337 FTIM0_GPCM_TEADC(0x0e) | \ 338 FTIM0_GPCM_TEAHC(0x0e)) 339 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 340 FTIM1_GPCM_TRAD(0x1f)) 341 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 342 FTIM2_GPCM_TCH(0x8) | \ 343 FTIM2_GPCM_TWP(0x1f)) 344 #define CONFIG_SYS_CS3_FTIM3 0x0 345 346 /* NAND Flash on IFC */ 347 #define CONFIG_NAND_FSL_IFC 348 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 349 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 350 #define CONFIG_SYS_NAND_BASE 0xff800000 351 #ifdef CONFIG_PHYS_64BIT 352 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 353 #else 354 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 355 #endif 356 357 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 358 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 359 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 360 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 361 | CSPR_V) 362 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 363 364 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 365 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 366 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 367 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 368 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 369 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 370 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 371 372 #define CONFIG_SYS_NAND_ONFI_DETECTION 373 374 /* ONFI NAND Flash mode0 Timing Params */ 375 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 376 FTIM0_NAND_TWP(0x18) | \ 377 FTIM0_NAND_TWCHT(0x07) | \ 378 FTIM0_NAND_TWH(0x0a)) 379 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 380 FTIM1_NAND_TWBE(0x39) | \ 381 FTIM1_NAND_TRR(0x0e) | \ 382 FTIM1_NAND_TRP(0x18)) 383 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 384 FTIM2_NAND_TREH(0x0a) | \ 385 FTIM2_NAND_TWHRE(0x1e)) 386 #define CONFIG_SYS_NAND_FTIM3 0x0 387 388 #define CONFIG_SYS_NAND_DDR_LAW 11 389 390 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 391 #define CONFIG_SYS_MAX_NAND_DEVICE 1 392 #define CONFIG_CMD_NAND 393 394 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 395 396 #if defined(CONFIG_NAND) 397 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 398 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 399 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 400 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 401 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 402 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 403 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 404 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 405 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 406 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 407 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 408 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 409 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 410 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 411 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 412 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 413 #else 414 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 415 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 416 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 417 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 418 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 419 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 420 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 421 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 422 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 423 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 424 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 425 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 426 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 427 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 428 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 429 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 430 #endif 431 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 432 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 433 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 434 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 435 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 436 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 437 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 438 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 439 440 #ifdef CONFIG_SPL_BUILD 441 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 442 #else 443 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 444 #endif 445 446 #if defined(CONFIG_RAMBOOT_PBL) 447 #define CONFIG_SYS_RAMBOOT 448 #endif 449 450 #define CONFIG_BOARD_EARLY_INIT_R 451 #define CONFIG_MISC_INIT_R 452 453 #define CONFIG_HWCONFIG 454 455 /* define to use L1 as initial stack */ 456 #define CONFIG_L1_INIT_RAM 457 #define CONFIG_SYS_INIT_RAM_LOCK 458 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 459 #ifdef CONFIG_PHYS_64BIT 460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 461 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 462 /* The assembler doesn't like typecast */ 463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 464 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 465 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 466 #else 467 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 468 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 469 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 470 #endif 471 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 472 473 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 474 GENERATED_GBL_DATA_SIZE) 475 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 476 477 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 478 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 479 480 /* Serial Port - controlled on board with jumper J8 481 * open - index 2 482 * shorted - index 1 483 */ 484 #define CONFIG_CONS_INDEX 1 485 #define CONFIG_SYS_NS16550_SERIAL 486 #define CONFIG_SYS_NS16550_REG_SIZE 1 487 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 488 489 #define CONFIG_SYS_BAUDRATE_TABLE \ 490 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 491 492 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 493 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 494 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 495 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 496 #ifndef CONFIG_SPL_BUILD 497 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 498 #endif 499 500 /* I2C */ 501 #define CONFIG_SYS_I2C 502 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 503 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 504 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 505 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 506 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 507 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 508 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 509 510 /* 511 * RTC configuration 512 */ 513 #define RTC 514 #define CONFIG_RTC_DS3231 1 515 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 516 517 /* 518 * RapidIO 519 */ 520 #ifdef CONFIG_SYS_SRIO 521 #ifdef CONFIG_SRIO1 522 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 523 #ifdef CONFIG_PHYS_64BIT 524 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 525 #else 526 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 527 #endif 528 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 529 #endif 530 531 #ifdef CONFIG_SRIO2 532 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 533 #ifdef CONFIG_PHYS_64BIT 534 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 535 #else 536 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 537 #endif 538 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 539 #endif 540 #endif 541 542 /* 543 * for slave u-boot IMAGE instored in master memory space, 544 * PHYS must be aligned based on the SIZE 545 */ 546 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 547 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 548 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 549 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 550 /* 551 * for slave UCODE and ENV instored in master memory space, 552 * PHYS must be aligned based on the SIZE 553 */ 554 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 555 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 556 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 557 558 /* slave core release by master*/ 559 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 560 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 561 562 /* 563 * SRIO_PCIE_BOOT - SLAVE 564 */ 565 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 566 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 567 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 568 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 569 #endif 570 571 /* 572 * eSPI - Enhanced SPI 573 */ 574 #define CONFIG_SF_DEFAULT_SPEED 10000000 575 #define CONFIG_SF_DEFAULT_MODE 0 576 577 /* 578 * MAPLE 579 */ 580 #ifdef CONFIG_PHYS_64BIT 581 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 582 #else 583 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 584 #endif 585 586 /* 587 * General PCI 588 * Memory space is mapped 1-1, but I/O space must start from 0. 589 */ 590 591 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 592 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 593 #ifdef CONFIG_PHYS_64BIT 594 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 595 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 596 #else 597 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 598 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 599 #endif 600 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 601 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 602 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 603 #ifdef CONFIG_PHYS_64BIT 604 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 605 #else 606 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 607 #endif 608 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 609 610 /* Qman/Bman */ 611 #ifndef CONFIG_NOBQFMAN 612 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 613 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 614 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 615 #ifdef CONFIG_PHYS_64BIT 616 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 617 #else 618 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 619 #endif 620 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 621 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 622 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 623 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 624 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 625 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 626 CONFIG_SYS_BMAN_CENA_SIZE) 627 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 628 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 629 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 630 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 631 #ifdef CONFIG_PHYS_64BIT 632 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 633 #else 634 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 635 #endif 636 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 637 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 638 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 639 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 640 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 641 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 642 CONFIG_SYS_QMAN_CENA_SIZE) 643 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 644 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 645 646 #define CONFIG_SYS_DPAA_FMAN 647 648 #define CONFIG_SYS_DPAA_RMAN 649 650 /* Default address of microcode for the Linux Fman driver */ 651 #if defined(CONFIG_SPIFLASH) 652 /* 653 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 654 * env, so we got 0x110000. 655 */ 656 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 657 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 658 #elif defined(CONFIG_SDCARD) 659 /* 660 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 661 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 662 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 663 */ 664 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 665 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 666 #elif defined(CONFIG_NAND) 667 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 668 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 669 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 670 /* 671 * Slave has no ucode locally, it can fetch this from remote. When implementing 672 * in two corenet boards, slave's ucode could be stored in master's memory 673 * space, the address can be mapped from slave TLB->slave LAW-> 674 * slave SRIO or PCIE outbound window->master inbound window-> 675 * master LAW->the ucode address in master's memory space. 676 */ 677 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 678 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 679 #else 680 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 681 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 682 #endif 683 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 684 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 685 #endif /* CONFIG_NOBQFMAN */ 686 687 #ifdef CONFIG_SYS_DPAA_FMAN 688 #define CONFIG_FMAN_ENET 689 #define CONFIG_PHYLIB_10G 690 #define CONFIG_PHY_VITESSE 691 #define CONFIG_PHY_TERANETICS 692 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 693 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 694 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 695 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 696 #endif 697 698 #ifdef CONFIG_PCI 699 #define CONFIG_PCI_INDIRECT_BRIDGE 700 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 701 702 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 703 #define CONFIG_DOS_PARTITION 704 #endif /* CONFIG_PCI */ 705 706 #ifdef CONFIG_FMAN_ENET 707 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 708 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 709 710 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 711 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 712 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 713 714 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 715 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 716 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 717 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 718 719 #define CONFIG_MII /* MII PHY management */ 720 #define CONFIG_ETHPRIME "FM1@DTSEC1" 721 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 722 #endif 723 724 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR 725 726 /* 727 * Environment 728 */ 729 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 730 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 731 732 /* 733 * Command line configuration. 734 */ 735 #define CONFIG_CMD_DATE 736 #define CONFIG_CMD_EEPROM 737 #define CONFIG_CMD_ERRATA 738 #define CONFIG_CMD_IRQ 739 #define CONFIG_CMD_REGINFO 740 741 #ifdef CONFIG_PCI 742 #define CONFIG_CMD_PCI 743 #endif 744 745 /* Hash command with SHA acceleration supported in hardware */ 746 #ifdef CONFIG_FSL_CAAM 747 #define CONFIG_CMD_HASH 748 #define CONFIG_SHA_HW_ACCEL 749 #endif 750 751 /* 752 * USB 753 */ 754 #define CONFIG_HAS_FSL_DR_USB 755 756 #ifdef CONFIG_HAS_FSL_DR_USB 757 #define CONFIG_USB_EHCI 758 759 #ifdef CONFIG_USB_EHCI 760 #define CONFIG_USB_STORAGE 761 #define CONFIG_USB_EHCI_FSL 762 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 763 #endif 764 #endif 765 766 /* 767 * Miscellaneous configurable options 768 */ 769 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 770 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 771 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 772 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 773 #ifdef CONFIG_CMD_KGDB 774 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 775 #else 776 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 777 #endif 778 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 779 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 780 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 781 782 /* 783 * For booting Linux, the board info and command line data 784 * have to be in the first 64 MB of memory, since this is 785 * the maximum mapped by the Linux kernel during initialization. 786 */ 787 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 788 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 789 790 #ifdef CONFIG_CMD_KGDB 791 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 792 #endif 793 794 /* 795 * Environment Configuration 796 */ 797 #define CONFIG_ROOTPATH "/opt/nfsroot" 798 #define CONFIG_BOOTFILE "uImage" 799 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 800 801 /* default location for tftp and bootm */ 802 #define CONFIG_LOADADDR 1000000 803 804 805 #define CONFIG_BAUDRATE 115200 806 807 #define __USB_PHY_TYPE ulpi 808 809 #ifdef CONFIG_PPC_B4860 810 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 811 "bank_intlv=cs0_cs1;" \ 812 "en_cpc:cpc2;" 813 #else 814 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 815 #endif 816 817 #define CONFIG_EXTRA_ENV_SETTINGS \ 818 HWCONFIG \ 819 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 820 "netdev=eth0\0" \ 821 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 822 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 823 "tftpflash=tftpboot $loadaddr $uboot && " \ 824 "protect off $ubootaddr +$filesize && " \ 825 "erase $ubootaddr +$filesize && " \ 826 "cp.b $loadaddr $ubootaddr $filesize && " \ 827 "protect on $ubootaddr +$filesize && " \ 828 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 829 "consoledev=ttyS0\0" \ 830 "ramdiskaddr=2000000\0" \ 831 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 832 "fdtaddr=1e00000\0" \ 833 "fdtfile=b4860qds/b4860qds.dtb\0" \ 834 "bdev=sda3\0" 835 836 /* For emulation this causes u-boot to jump to the start of the proof point 837 app code automatically */ 838 #define CONFIG_PROOF_POINTS \ 839 "setenv bootargs root=/dev/$bdev rw " \ 840 "console=$consoledev,$baudrate $othbootargs;" \ 841 "cpu 1 release 0x29000000 - - -;" \ 842 "cpu 2 release 0x29000000 - - -;" \ 843 "cpu 3 release 0x29000000 - - -;" \ 844 "cpu 4 release 0x29000000 - - -;" \ 845 "cpu 5 release 0x29000000 - - -;" \ 846 "cpu 6 release 0x29000000 - - -;" \ 847 "cpu 7 release 0x29000000 - - -;" \ 848 "go 0x29000000" 849 850 #define CONFIG_HVBOOT \ 851 "setenv bootargs config-addr=0x60000000; " \ 852 "bootm 0x01000000 - 0x00f00000" 853 854 #define CONFIG_ALU \ 855 "setenv bootargs root=/dev/$bdev rw " \ 856 "console=$consoledev,$baudrate $othbootargs;" \ 857 "cpu 1 release 0x01000000 - - -;" \ 858 "cpu 2 release 0x01000000 - - -;" \ 859 "cpu 3 release 0x01000000 - - -;" \ 860 "cpu 4 release 0x01000000 - - -;" \ 861 "cpu 5 release 0x01000000 - - -;" \ 862 "cpu 6 release 0x01000000 - - -;" \ 863 "cpu 7 release 0x01000000 - - -;" \ 864 "go 0x01000000" 865 866 #define CONFIG_LINUX \ 867 "setenv bootargs root=/dev/ram rw " \ 868 "console=$consoledev,$baudrate $othbootargs;" \ 869 "setenv ramdiskaddr 0x02000000;" \ 870 "setenv fdtaddr 0x01e00000;" \ 871 "setenv loadaddr 0x1000000;" \ 872 "bootm $loadaddr $ramdiskaddr $fdtaddr" 873 874 #define CONFIG_HDBOOT \ 875 "setenv bootargs root=/dev/$bdev rw " \ 876 "console=$consoledev,$baudrate $othbootargs;" \ 877 "tftp $loadaddr $bootfile;" \ 878 "tftp $fdtaddr $fdtfile;" \ 879 "bootm $loadaddr - $fdtaddr" 880 881 #define CONFIG_NFSBOOTCOMMAND \ 882 "setenv bootargs root=/dev/nfs rw " \ 883 "nfsroot=$serverip:$rootpath " \ 884 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 885 "console=$consoledev,$baudrate $othbootargs;" \ 886 "tftp $loadaddr $bootfile;" \ 887 "tftp $fdtaddr $fdtfile;" \ 888 "bootm $loadaddr - $fdtaddr" 889 890 #define CONFIG_RAMBOOTCOMMAND \ 891 "setenv bootargs root=/dev/ram rw " \ 892 "console=$consoledev,$baudrate $othbootargs;" \ 893 "tftp $ramdiskaddr $ramdiskfile;" \ 894 "tftp $loadaddr $bootfile;" \ 895 "tftp $fdtaddr $fdtfile;" \ 896 "bootm $loadaddr $ramdiskaddr $fdtaddr" 897 898 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 899 900 #include <asm/fsl_secure_boot.h> 901 902 #endif /* __CONFIG_H */ 903